1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Display Control Unit (DCU4) 31 * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/watchdog.h> 47 #include <sys/fbio.h> 48 #include <sys/consio.h> 49 #include <sys/eventhandler.h> 50 #include <sys/gpio.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 55 #include <dev/ofw/openfirm.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 59 #include <dev/vt/vt.h> 60 #include <dev/vt/colors/vt_termcolors.h> 61 62 #include "gpio_if.h" 63 64 #include <machine/bus.h> 65 #include <machine/fdt.h> 66 #include <machine/cpu.h> 67 #include <machine/intr.h> 68 69 #include "fb_if.h" 70 71 #include <arm/freescale/vybrid/vf_common.h> 72 73 #define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 74 #define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 75 #define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 76 #define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 77 #define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 78 #define DCU_MODE_M 0x3 79 #define DCU_MODE_S 0 80 #define DCU_MODE_NORMAL 0x1 81 #define DCU_MODE_TEST 0x2 82 #define DCU_MODE_COLBAR 0x3 83 #define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 84 #define PDI_EN (1 << 13) 85 #define PDI_DE_MODE (1 << 11) 86 #define PDI_MODE_M 2 87 #define DCU_BGND 0x014 /* Background */ 88 #define DCU_DISP_SIZE 0x018 /* Display Size */ 89 #define DELTA_M 0x7ff 90 #define DELTA_Y_S 16 91 #define DELTA_X_S 0 92 #define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 93 #define BP_H_SHIFT 22 94 #define PW_H_SHIFT 11 95 #define FP_H_SHIFT 0 96 #define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 97 #define BP_V_SHIFT 22 98 #define PW_V_SHIFT 11 99 #define FP_V_SHIFT 0 100 #define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 101 #define INV_HS (1 << 0) 102 #define INV_VS (1 << 1) 103 #define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ 104 #define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ 105 #define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ 106 #define DCU_THRESHOLD 0x028 /* Threshold */ 107 #define LS_BF_VS_SHIFT 16 108 #define OUT_BUF_HIGH_SHIFT 8 109 #define OUT_BUF_LOW_SHIFT 0 110 #define DCU_INT_STATUS 0x02C /* Interrupt Status */ 111 #define DCU_INT_MASK 0x030 /* Interrupt Mask */ 112 #define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 113 #define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 114 #define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 115 #define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 116 #define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 117 #define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 118 #define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 119 #define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 120 #define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 121 #define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 122 #define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 123 #define DCU_CRC_VAL 0x060 /* CRC Value */ 124 #define DCU_PDI_STATUS 0x064 /* PDI Status */ 125 #define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 126 #define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 127 #define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 128 #define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 129 #define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 130 #define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 131 #define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 132 #define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 133 #define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 134 #define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 135 #define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 136 #define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 137 #define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 138 #define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 139 #define DCU_CRC_POS 0x0B0 /* CRC Position */ 140 #define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 141 #define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 142 #define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 143 #define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 144 #define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 145 #define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 146 #define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 147 #define READREG (1 << 30) 148 #define MODE (1 << 31) 149 #define DCU_UNDERRUN 0x0D0 /* Underrun */ 150 #define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 151 #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 152 #define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 153 #define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 154 #define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 155 #define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 156 #define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 157 #define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 158 159 /* Control Descriptor */ 160 #define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 161 #define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 162 #define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 163 #define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 164 #define TRANS_SHIFT 20 165 #define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 166 #define BPP_MASK 0xf /* Bit per pixel Mask */ 167 #define BPP_SHIFT 16 /* Bit per pixel Shift */ 168 #define BPP24 0x5 169 #define EN_LAYER (1 << 31) /* Enable the layer */ 170 #define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 171 #define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 172 #define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 173 #define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 174 #define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 175 176 #define NUM_LAYERS 64 177 178 struct panel_info { 179 uint32_t width; 180 uint32_t height; 181 uint32_t h_back_porch; 182 uint32_t h_pulse_width; 183 uint32_t h_front_porch; 184 uint32_t v_back_porch; 185 uint32_t v_pulse_width; 186 uint32_t v_front_porch; 187 uint32_t clk_div; 188 uint32_t backlight_pin; 189 }; 190 191 struct dcu_softc { 192 struct resource *res[2]; 193 bus_space_tag_t bst; 194 bus_space_handle_t bsh; 195 void *ih; 196 device_t dev; 197 device_t sc_fbd; /* fbd child */ 198 struct fb_info sc_info; 199 struct panel_info *panel; 200 }; 201 202 static struct resource_spec dcu_spec[] = { 203 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 204 { SYS_RES_IRQ, 0, RF_ACTIVE }, 205 { -1, 0 } 206 }; 207 208 static int 209 dcu_probe(device_t dev) 210 { 211 212 if (!ofw_bus_status_okay(dev)) 213 return (ENXIO); 214 215 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 216 return (ENXIO); 217 218 device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 219 return (BUS_PROBE_DEFAULT); 220 } 221 222 static void 223 dcu_intr(void *arg) 224 { 225 struct dcu_softc *sc; 226 int reg; 227 228 sc = arg; 229 230 /* Ack interrupts */ 231 reg = READ4(sc, DCU_INT_STATUS); 232 WRITE4(sc, DCU_INT_STATUS, reg); 233 234 /* TODO interrupt handler */ 235 } 236 237 static int 238 get_panel_info(struct dcu_softc *sc, struct panel_info *panel) 239 { 240 phandle_t node; 241 pcell_t dts_value[3]; 242 int len; 243 244 if ((node = ofw_bus_get_node(sc->dev)) == -1) 245 return (ENXIO); 246 247 /* panel size */ 248 if ((len = OF_getproplen(node, "panel-size")) <= 0) 249 return (ENXIO); 250 OF_getencprop(node, "panel-size", dts_value, len); 251 panel->width = dts_value[0]; 252 panel->height = dts_value[1]; 253 254 /* hsync */ 255 if ((len = OF_getproplen(node, "panel-hsync")) <= 0) 256 return (ENXIO); 257 OF_getencprop(node, "panel-hsync", dts_value, len); 258 panel->h_back_porch = dts_value[0]; 259 panel->h_pulse_width = dts_value[1]; 260 panel->h_front_porch = dts_value[2]; 261 262 /* vsync */ 263 if ((len = OF_getproplen(node, "panel-vsync")) <= 0) 264 return (ENXIO); 265 OF_getencprop(node, "panel-vsync", dts_value, len); 266 panel->v_back_porch = dts_value[0]; 267 panel->v_pulse_width = dts_value[1]; 268 panel->v_front_porch = dts_value[2]; 269 270 /* clk divider */ 271 if ((len = OF_getproplen(node, "panel-clk-div")) <= 0) 272 return (ENXIO); 273 OF_getencprop(node, "panel-clk-div", dts_value, len); 274 panel->clk_div = dts_value[0]; 275 276 /* backlight pin */ 277 if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0) 278 return (ENXIO); 279 OF_getencprop(node, "panel-backlight-pin", dts_value, len); 280 panel->backlight_pin = dts_value[0]; 281 282 return (0); 283 } 284 285 static int 286 dcu_init(struct dcu_softc *sc) 287 { 288 struct panel_info *panel; 289 int reg; 290 int i; 291 292 panel = sc->panel; 293 294 /* Configure DCU */ 295 reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 296 reg |= (sc->sc_info.fb_width / 16); 297 WRITE4(sc, DCU_DISP_SIZE, reg); 298 299 reg = (panel->h_back_porch << BP_H_SHIFT); 300 reg |= (panel->h_pulse_width << PW_H_SHIFT); 301 reg |= (panel->h_front_porch << FP_H_SHIFT); 302 WRITE4(sc, DCU_HSYN_PARA, reg); 303 304 reg = (panel->v_back_porch << BP_V_SHIFT); 305 reg |= (panel->v_pulse_width << PW_V_SHIFT); 306 reg |= (panel->v_front_porch << FP_V_SHIFT); 307 WRITE4(sc, DCU_VSYN_PARA, reg); 308 309 WRITE4(sc, DCU_BGND, 0); 310 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); 311 312 reg = (INV_VS | INV_HS); 313 WRITE4(sc, DCU_SYNPOL, reg); 314 315 /* TODO: export to panel info */ 316 reg = (0x3 << LS_BF_VS_SHIFT); 317 reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 318 reg |= (0 << OUT_BUF_LOW_SHIFT); 319 WRITE4(sc, DCU_THRESHOLD, reg); 320 321 /* Mask all the interrupts */ 322 WRITE4(sc, DCU_INT_MASK, 0xffffffff); 323 324 /* Reset all layers */ 325 for (i = 0; i < NUM_LAYERS; i++) { 326 WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0); 327 WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0); 328 WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0); 329 WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0); 330 WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0); 331 WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0); 332 WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0); 333 WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0); 334 WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0); 335 } 336 337 /* Setup first layer */ 338 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 339 WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 340 WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 341 WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 342 reg = (BPP24 << BPP_SHIFT); 343 reg |= EN_LAYER; 344 reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 345 WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 346 WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 347 WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 348 WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 349 WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 350 WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 351 352 /* Enable DCU in normal mode */ 353 reg = READ4(sc, DCU_DCU_MODE); 354 reg &= ~(DCU_MODE_M << DCU_MODE_S); 355 reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 356 reg |= (RASTER_EN); 357 WRITE4(sc, DCU_DCU_MODE, reg); 358 WRITE4(sc, DCU_UPDATE_MODE, READREG); 359 360 return (0); 361 } 362 363 static int 364 dcu_attach(device_t dev) 365 { 366 struct panel_info panel; 367 struct dcu_softc *sc; 368 device_t gpio_dev; 369 int err; 370 371 sc = device_get_softc(dev); 372 sc->dev = dev; 373 374 if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 375 device_printf(dev, "could not allocate resources\n"); 376 return (ENXIO); 377 } 378 379 /* Memory interface */ 380 sc->bst = rman_get_bustag(sc->res[0]); 381 sc->bsh = rman_get_bushandle(sc->res[0]); 382 383 /* Setup interrupt handler */ 384 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 385 NULL, dcu_intr, sc, &sc->ih); 386 if (err) { 387 device_printf(dev, "Unable to alloc interrupt resource.\n"); 388 return (ENXIO); 389 } 390 391 if (get_panel_info(sc, &panel)) { 392 device_printf(dev, "Can't get panel info\n"); 393 return (ENXIO); 394 } 395 396 sc->panel = &panel; 397 398 /* Bypass timing control (used for raw lcd panels) */ 399 tcon_bypass(); 400 401 /* Get the GPIO device, we need this to give power to USB */ 402 gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 403 if (gpio_dev == NULL) { 404 device_printf(sc->dev, "Error: failed to get the GPIO dev\n"); 405 return (1); 406 } 407 408 /* Turn on backlight */ 409 /* TODO: Use FlexTimer/PWM */ 410 GPIO_PIN_SETFLAGS(gpio_dev, panel.backlight_pin, GPIO_PIN_OUTPUT); 411 GPIO_PIN_SET(gpio_dev, panel.backlight_pin, GPIO_PIN_HIGH); 412 413 sc->sc_info.fb_width = panel.width; 414 sc->sc_info.fb_height = panel.height; 415 sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 416 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 417 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 418 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 419 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 420 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 421 422 #if 0 423 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 424 sc->sc_info.fb_stride); 425 printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 426 #endif 427 428 memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 429 430 dcu_init(sc); 431 432 sc->sc_info.fb_name = device_get_nameunit(dev); 433 434 /* Ask newbus to attach framebuffer device to me. */ 435 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 436 if (sc->sc_fbd == NULL) 437 device_printf(dev, "Can't attach fbd device\n"); 438 439 if (device_probe_and_attach(sc->sc_fbd) != 0) { 440 device_printf(sc->dev, "Failed to attach fbd device\n"); 441 } 442 443 return (0); 444 } 445 446 static struct fb_info * 447 dcu4_fb_getinfo(device_t dev) 448 { 449 struct dcu_softc *sc = device_get_softc(dev); 450 451 return (&sc->sc_info); 452 } 453 454 static device_method_t dcu_methods[] = { 455 DEVMETHOD(device_probe, dcu_probe), 456 DEVMETHOD(device_attach, dcu_attach), 457 458 /* Framebuffer service methods */ 459 DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 460 { 0, 0 } 461 }; 462 463 static driver_t dcu_driver = { 464 "fb", 465 dcu_methods, 466 sizeof(struct dcu_softc), 467 }; 468 469 DRIVER_MODULE(fb, simplebus, dcu_driver, 0, 0); 470