1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Clock Controller Module (CCM) 31 * Chapter 10, Vybrid Reference Manual, Rev. 5, 07/2013 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/watchdog.h> 47 48 #include <dev/fdt/fdt_common.h> 49 #include <dev/ofw/openfirm.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <machine/bus.h> 54 #include <machine/cpu.h> 55 #include <machine/intr.h> 56 57 #include <arm/freescale/vybrid/vf_common.h> 58 59 #define CCM_CCR 0x00 /* Control Register */ 60 #define CCM_CSR 0x04 /* Status Register */ 61 #define CCM_CCSR 0x08 /* Clock Switcher Register */ 62 #define CCM_CACRR 0x0C /* ARM Clock Root Register */ 63 #define CCM_CSCMR1 0x10 /* Serial Clock Multiplexer Register 1 */ 64 #define CCM_CSCDR1 0x14 /* Serial Clock Divider Register 1 */ 65 #define CCM_CSCDR2 0x18 /* Serial Clock Divider Register 2 */ 66 #define CCM_CSCDR3 0x1C /* Serial Clock Divider Register 3 */ 67 #define CCM_CSCMR2 0x20 /* Serial Clock Multiplexer Register 2 */ 68 #define CCM_CTOR 0x28 /* Testing Observability Register */ 69 #define CCM_CLPCR 0x2C /* Low Power Control Register */ 70 #define CCM_CISR 0x30 /* Interrupt Status Register */ 71 #define CCM_CIMR 0x34 /* Interrupt Mask Register */ 72 #define CCM_CCOSR 0x38 /* Clock Output Source Register */ 73 #define CCM_CGPR 0x3C /* General Purpose Register */ 74 75 #define CCM_CCGRN 12 76 #define CCM_CCGR(n) (0x40 + (n * 0x04)) /* Clock Gating Register */ 77 #define CCM_CMEOR(n) (0x70 + (n * 0x70)) /* Module Enable Override */ 78 #define CCM_CCPGR(n) (0x90 + (n * 0x04)) /* Platform Clock Gating */ 79 80 #define CCM_CPPDSR 0x88 /* PLL PFD Disable Status Register */ 81 #define CCM_CCOWR 0x8C /* CORE Wakeup Register */ 82 83 #define PLL3_PFD4_EN (1U << 31) 84 #define PLL3_PFD3_EN (1 << 30) 85 #define PLL3_PFD2_EN (1 << 29) 86 #define PLL3_PFD1_EN (1 << 28) 87 #define PLL2_PFD4_EN (1 << 15) 88 #define PLL2_PFD3_EN (1 << 14) 89 #define PLL2_PFD2_EN (1 << 13) 90 #define PLL2_PFD1_EN (1 << 12) 91 #define PLL1_PFD4_EN (1 << 11) 92 #define PLL1_PFD3_EN (1 << 10) 93 #define PLL1_PFD2_EN (1 << 9) 94 #define PLL1_PFD1_EN (1 << 8) 95 96 /* CCM_CCR */ 97 #define FIRC_EN (1 << 16) 98 #define FXOSC_EN (1 << 12) 99 #define FXOSC_RDY (1 << 5) 100 101 /* CCM_CSCDR1 */ 102 #define ENET_TS_EN (1 << 23) 103 #define RMII_CLK_EN (1 << 24) 104 #define SAI3_EN (1 << 19) 105 106 /* CCM_CSCDR2 */ 107 #define ESAI_EN (1 << 30) 108 #define ESDHC1_EN (1 << 29) 109 #define ESDHC0_EN (1 << 28) 110 #define NFC_EN (1 << 9) 111 #define ESDHC1_DIV_S 20 112 #define ESDHC1_DIV_M 0xf 113 #define ESDHC0_DIV_S 16 114 #define ESDHC0_DIV_M 0xf 115 116 /* CCM_CSCDR3 */ 117 #define DCU0_EN (1 << 19) 118 119 #define QSPI1_EN (1 << 12) 120 #define QSPI1_DIV (1 << 11) 121 #define QSPI1_X2_DIV (1 << 10) 122 #define QSPI1_X4_DIV_M 0x3 123 #define QSPI1_X4_DIV_S 8 124 125 #define QSPI0_EN (1 << 4) 126 #define QSPI0_DIV (1 << 3) 127 #define QSPI0_X2_DIV (1 << 2) 128 #define QSPI0_X4_DIV_M 0x3 129 #define QSPI0_X4_DIV_S 0 130 131 #define SAI3_DIV_SHIFT 12 132 #define SAI3_DIV_MASK 0xf 133 #define ESAI_DIV_SHIFT 24 134 #define ESAI_DIV_MASK 0xf 135 136 #define PLL4_CLK_DIV_SHIFT 6 137 #define PLL4_CLK_DIV_MASK 0x7 138 139 #define IPG_CLK_DIV_SHIFT 11 140 #define IPG_CLK_DIV_MASK 0x3 141 142 #define ESAI_CLK_SEL_SHIFT 20 143 #define ESAI_CLK_SEL_MASK 0x3 144 145 #define SAI3_CLK_SEL_SHIFT 6 146 #define SAI3_CLK_SEL_MASK 0x3 147 148 #define CKO1_EN (1 << 10) 149 #define CKO1_DIV_MASK 0xf 150 #define CKO1_DIV_SHIFT 6 151 #define CKO1_SEL_MASK 0x3f 152 #define CKO1_SEL_SHIFT 0 153 #define CKO1_PLL4_MAIN 0x6 154 #define CKO1_PLL4_DIVD 0x7 155 156 struct clk { 157 uint32_t reg; 158 uint32_t enable_reg; 159 uint32_t div_mask; 160 uint32_t div_shift; 161 uint32_t div_val; 162 uint32_t sel_reg; 163 uint32_t sel_mask; 164 uint32_t sel_shift; 165 uint32_t sel_val; 166 }; 167 168 static struct clk ipg_clk = { 169 .reg = CCM_CACRR, 170 .enable_reg = 0, 171 .div_mask = IPG_CLK_DIV_MASK, 172 .div_shift = IPG_CLK_DIV_SHIFT, 173 .div_val = 1, /* Divide by 2 */ 174 .sel_reg = 0, 175 .sel_mask = 0, 176 .sel_shift = 0, 177 .sel_val = 0, 178 }; 179 180 /* 181 PLL4 clock divider (before switching the clocks should be gated) 182 000 Divide by 1 (only if PLL frequency less than or equal to 650 MHz) 183 001 Divide by 4 184 010 Divide by 6 185 011 Divide by 8 186 100 Divide by 10 187 101 Divide by 12 188 110 Divide by 14 189 111 Divide by 16 190 */ 191 192 static struct clk pll4_clk = { 193 .reg = CCM_CACRR, 194 .enable_reg = 0, 195 .div_mask = PLL4_CLK_DIV_MASK, 196 .div_shift = PLL4_CLK_DIV_SHIFT, 197 .div_val = 5, /* Divide by 12 */ 198 .sel_reg = 0, 199 .sel_mask = 0, 200 .sel_shift = 0, 201 .sel_val = 0, 202 }; 203 204 static struct clk sai3_clk = { 205 .reg = CCM_CSCDR1, 206 .enable_reg = SAI3_EN, 207 .div_mask = SAI3_DIV_MASK, 208 .div_shift = SAI3_DIV_SHIFT, 209 .div_val = 1, 210 .sel_reg = CCM_CSCMR1, 211 .sel_mask = SAI3_CLK_SEL_MASK, 212 .sel_shift = SAI3_CLK_SEL_SHIFT, 213 .sel_val = 0x3, /* Divided PLL4 main clock */ 214 }; 215 216 static struct clk cko1_clk = { 217 .reg = CCM_CCOSR, 218 .enable_reg = CKO1_EN, 219 .div_mask = CKO1_DIV_MASK, 220 .div_shift = CKO1_DIV_SHIFT, 221 .div_val = 1, 222 .sel_reg = CCM_CCOSR, 223 .sel_mask = CKO1_SEL_MASK, 224 .sel_shift = CKO1_SEL_SHIFT, 225 .sel_val = CKO1_PLL4_DIVD, 226 }; 227 228 static struct clk esdhc0_clk = { 229 .reg = CCM_CSCDR2, 230 .enable_reg = ESDHC0_EN, 231 .div_mask = ESDHC0_DIV_M, 232 .div_shift = ESDHC0_DIV_S, 233 .div_val = 0x9, 234 .sel_reg = 0, 235 .sel_mask = 0, 236 .sel_shift = 0, 237 .sel_val = 0, 238 }; 239 240 static struct clk esdhc1_clk = { 241 .reg = CCM_CSCDR2, 242 .enable_reg = ESDHC1_EN, 243 .div_mask = ESDHC1_DIV_M, 244 .div_shift = ESDHC1_DIV_S, 245 .div_val = 0x9, 246 .sel_reg = 0, 247 .sel_mask = 0, 248 .sel_shift = 0, 249 .sel_val = 0, 250 }; 251 252 static struct clk qspi0_clk = { 253 .reg = CCM_CSCDR3, 254 .enable_reg = QSPI0_EN, 255 .div_mask = 0, 256 .div_shift = 0, 257 .div_val = 0, 258 .sel_reg = 0, 259 .sel_mask = 0, 260 .sel_shift = 0, 261 .sel_val = 0, 262 }; 263 264 static struct clk dcu0_clk = { 265 .reg = CCM_CSCDR3, 266 .enable_reg = DCU0_EN, 267 .div_mask = 0x7, 268 .div_shift = 16, /* DCU0_DIV */ 269 .div_val = 0, /* divide by 1 */ 270 .sel_reg = 0, 271 .sel_mask = 0, 272 .sel_shift = 0, 273 .sel_val = 0, 274 }; 275 276 static struct clk enet_clk = { 277 .reg = CCM_CSCDR1, 278 .enable_reg = (ENET_TS_EN | RMII_CLK_EN), 279 .div_mask = 0, 280 .div_shift = 0, 281 .div_val = 0, 282 .sel_reg = 0, 283 .sel_mask = 0, 284 .sel_shift = 0, 285 .sel_val = 0, 286 }; 287 288 static struct clk nand_clk = { 289 .reg = CCM_CSCDR2, 290 .enable_reg = NFC_EN, 291 .div_mask = 0, 292 .div_shift = 0, 293 .div_val = 0, 294 .sel_reg = 0, 295 .sel_mask = 0, 296 .sel_shift = 0, 297 .sel_val = 0, 298 }; 299 300 /* 301 Divider to generate ESAI clock 302 0000 Divide by 1 303 0001 Divide by 2 304 ... ... 305 1111 Divide by 16 306 */ 307 308 static struct clk esai_clk = { 309 .reg = CCM_CSCDR2, 310 .enable_reg = ESAI_EN, 311 .div_mask = ESAI_DIV_MASK, 312 .div_shift = ESAI_DIV_SHIFT, 313 .div_val = 3, /* Divide by 4 */ 314 .sel_reg = CCM_CSCMR1, 315 .sel_mask = ESAI_CLK_SEL_MASK, 316 .sel_shift = ESAI_CLK_SEL_SHIFT, 317 .sel_val = 0x3, /* Divided PLL4 main clock */ 318 }; 319 320 struct clock_entry { 321 char *name; 322 struct clk *clk; 323 }; 324 325 static struct clock_entry clock_map[] = { 326 {"ipg", &ipg_clk}, 327 {"pll4", &pll4_clk}, 328 {"sai3", &sai3_clk}, 329 {"cko1", &cko1_clk}, 330 {"esdhc0", &esdhc0_clk}, 331 {"esdhc1", &esdhc1_clk}, 332 {"qspi0", &qspi0_clk}, 333 {"dcu0", &dcu0_clk}, 334 {"enet", &enet_clk}, 335 {"nand", &nand_clk}, 336 {"esai", &esai_clk}, 337 {NULL, NULL} 338 }; 339 340 struct ccm_softc { 341 struct resource *res[1]; 342 bus_space_tag_t bst; 343 bus_space_handle_t bsh; 344 device_t dev; 345 }; 346 347 static struct resource_spec ccm_spec[] = { 348 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 349 { -1, 0 } 350 }; 351 352 static int 353 ccm_probe(device_t dev) 354 { 355 356 if (!ofw_bus_status_okay(dev)) 357 return (ENXIO); 358 359 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-ccm")) 360 return (ENXIO); 361 362 device_set_desc(dev, "Vybrid Family CCM Unit"); 363 return (BUS_PROBE_DEFAULT); 364 } 365 366 static int 367 set_clock(struct ccm_softc *sc, char *name) 368 { 369 struct clk *clk; 370 int reg; 371 int i; 372 373 for (i = 0; clock_map[i].name != NULL; i++) { 374 if (strcmp(clock_map[i].name, name) == 0) { 375 #if 0 376 device_printf(sc->dev, "Configuring %s clk\n", name); 377 #endif 378 clk = clock_map[i].clk; 379 if (clk->sel_reg != 0) { 380 reg = READ4(sc, clk->sel_reg); 381 reg &= ~(clk->sel_mask << clk->sel_shift); 382 reg |= (clk->sel_val << clk->sel_shift); 383 WRITE4(sc, clk->sel_reg, reg); 384 } 385 386 reg = READ4(sc, clk->reg); 387 reg |= clk->enable_reg; 388 reg &= ~(clk->div_mask << clk->div_shift); 389 reg |= (clk->div_val << clk->div_shift); 390 WRITE4(sc, clk->reg, reg); 391 } 392 } 393 394 return (0); 395 } 396 397 static int 398 ccm_fdt_set(struct ccm_softc *sc) 399 { 400 phandle_t child, parent, root; 401 int len; 402 char *fdt_config, *name; 403 404 root = OF_finddevice("/"); 405 len = 0; 406 parent = root; 407 408 /* Find 'clock_names' prop in the tree */ 409 for (child = OF_child(parent); child != 0; child = OF_peer(child)) { 410 411 /* Find a 'leaf'. Start the search from this node. */ 412 while (OF_child(child)) { 413 parent = child; 414 child = OF_child(child); 415 } 416 417 if (!ofw_bus_node_status_okay(child)) 418 continue; 419 420 if ((len = OF_getproplen(child, "clock_names")) > 0) { 421 len = OF_getproplen(child, "clock_names"); 422 OF_getprop_alloc(child, "clock_names", 423 (void **)&fdt_config); 424 425 while (len > 0) { 426 name = fdt_config; 427 fdt_config += strlen(name) + 1; 428 len -= strlen(name) + 1; 429 set_clock(sc, name); 430 } 431 } 432 433 if (OF_peer(child) == 0) { 434 /* No more siblings. */ 435 child = parent; 436 parent = OF_parent(child); 437 } 438 } 439 440 return (0); 441 } 442 443 static int 444 ccm_attach(device_t dev) 445 { 446 struct ccm_softc *sc; 447 int reg; 448 int i; 449 450 sc = device_get_softc(dev); 451 sc->dev = dev; 452 453 if (bus_alloc_resources(dev, ccm_spec, sc->res)) { 454 device_printf(dev, "could not allocate resources\n"); 455 return (ENXIO); 456 } 457 458 /* Memory interface */ 459 sc->bst = rman_get_bustag(sc->res[0]); 460 sc->bsh = rman_get_bushandle(sc->res[0]); 461 462 /* Enable oscillator */ 463 reg = READ4(sc, CCM_CCR); 464 reg |= (FIRC_EN | FXOSC_EN); 465 WRITE4(sc, CCM_CCR, reg); 466 467 /* Wait 10 times */ 468 for (i = 0; i < 10; i++) { 469 if (READ4(sc, CCM_CSR) & FXOSC_RDY) { 470 device_printf(sc->dev, "On board oscillator is ready.\n"); 471 break; 472 } 473 474 cpufunc_nullop(); 475 } 476 477 /* Clock is on during all modes, except stop mode. */ 478 for (i = 0; i < CCM_CCGRN; i++) { 479 WRITE4(sc, CCM_CCGR(i), 0xffffffff); 480 } 481 482 /* Take and apply FDT clocks */ 483 ccm_fdt_set(sc); 484 485 return (0); 486 } 487 488 static device_method_t ccm_methods[] = { 489 DEVMETHOD(device_probe, ccm_probe), 490 DEVMETHOD(device_attach, ccm_attach), 491 { 0, 0 } 492 }; 493 494 static driver_t ccm_driver = { 495 "ccm", 496 ccm_methods, 497 sizeof(struct ccm_softc), 498 }; 499 500 static devclass_t ccm_devclass; 501 502 DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0); 503