xref: /freebsd/sys/arm/freescale/vybrid/vf_anadig.c (revision 4ec234c813eed05c166859bba82c882e40826eb9)
1 /*-
2  * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 /*
28  * Vybrid Family Analog components control digital interface (ANADIG)
29  * Chapter 11, Vybrid Reference Manual, Rev. 5, 07/2013
30  */
31 
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/rman.h>
42 #include <sys/timeet.h>
43 #include <sys/timetc.h>
44 #include <sys/watchdog.h>
45 
46 #include <dev/fdt/fdt_common.h>
47 #include <dev/ofw/openfirm.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 
51 #include <machine/bus.h>
52 #include <machine/fdt.h>
53 #include <machine/cpu.h>
54 #include <machine/intr.h>
55 
56 #include <arm/freescale/vybrid/vf_common.h>
57 
58 #define	ANADIG_PLL3_CTRL	0x010	/* PLL3 Control */
59 #define	ANADIG_PLL7_CTRL	0x020	/* PLL7 Control */
60 #define	ANADIG_PLL2_CTRL	0x030	/* PLL2 Control */
61 #define	ANADIG_PLL2_SS		0x040	/* PLL2 Spread Spectrum */
62 #define	ANADIG_PLL2_NUM		0x050	/* PLL2 Numerator */
63 #define	ANADIG_PLL2_DENOM	0x060	/* PLL2 Denominator */
64 #define	ANADIG_PLL4_CTRL	0x070	/* PLL4 Control */
65 #define	ANADIG_PLL4_NUM		0x080	/* PLL4 Numerator */
66 #define	ANADIG_PLL4_DENOM	0x090	/* PLL4 Denominator */
67 #define	ANADIG_PLL6_CTRL	0x0A0	/* PLL6 Control */
68 #define	ANADIG_PLL6_NUM		0x0B0	/* PLL6 Numerator */
69 #define	ANADIG_PLL6_DENOM	0x0C0	/* PLL6 Denominator */
70 #define	ANADIG_PLL5_CTRL	0x0E0	/* PLL5 Control */
71 #define	ANADIG_PLL3_PFD		0x0F0	/* PLL3 PFD */
72 #define	ANADIG_PLL2_PFD		0x100	/* PLL2 PFD */
73 #define	ANADIG_REG_1P1		0x110	/* Regulator 1P1 */
74 #define	ANADIG_REG_3P0		0x120	/* Regulator 3P0 */
75 #define	ANADIG_REG_2P5		0x130	/* Regulator 2P5 */
76 #define	ANADIG_ANA_MISC0	0x150	/* Analog Miscellaneous */
77 #define	ANADIG_ANA_MISC1	0x160	/* Analog Miscellaneous */
78 #define	ANADIG_ANADIG_DIGPROG	0x260	/* Digital Program */
79 #define	ANADIG_PLL1_CTRL	0x270	/* PLL1 Control */
80 #define	ANADIG_PLL1_SS		0x280	/* PLL1 Spread Spectrum */
81 #define	ANADIG_PLL1_NUM		0x290	/* PLL1 Numerator */
82 #define	ANADIG_PLL1_DENOM	0x2A0	/* PLL1 Denominator */
83 #define	ANADIG_PLL1_PFD		0x2B0	/* PLL1_PFD */
84 #define	ANADIG_PLL_LOCK		0x2C0	/* PLL Lock */
85 
86 #define	USB_VBUS_DETECT(n)		(0x1A0 + 0x60 * n)
87 #define	USB_CHRG_DETECT(n)		(0x1B0 + 0x60 * n)
88 #define	USB_VBUS_DETECT_STATUS(n)	(0x1C0 + 0x60 * n)
89 #define	USB_CHRG_DETECT_STATUS(n)	(0x1D0 + 0x60 * n)
90 #define	USB_LOOPBACK(n)			(0x1E0 + 0x60 * n)
91 #define	USB_MISC(n)			(0x1F0 + 0x60 * n)
92 
93 #define	ANADIG_PLL_LOCKED	(1U << 31)
94 #define	ENABLE_LINREG		(1 << 0)
95 #define	EN_CLK_TO_UTMI		(1 << 30)
96 
97 #define	CTRL_BYPASS		(1 << 16)
98 #define	CTRL_PWR		(1 << 12)
99 #define	CTRL_PLL_EN		(1 << 13)
100 #define	EN_USB_CLKS		(1 << 6)
101 
102 struct anadig_softc {
103 	struct resource		*res[1];
104 	bus_space_tag_t		bst;
105 	bus_space_handle_t	bsh;
106 };
107 
108 static struct resource_spec anadig_spec[] = {
109 	{ SYS_RES_MEMORY,       0,      RF_ACTIVE },
110 	{ -1, 0 }
111 };
112 
113 static int
114 anadig_probe(device_t dev)
115 {
116 
117 	if (!ofw_bus_is_compatible(dev, "fsl,mvf600-anadig"))
118 		return (ENXIO);
119 
120 	device_set_desc(dev, "Vybrid Family ANADIG Unit");
121 	return (BUS_PROBE_DEFAULT);
122 }
123 
124 static int
125 enable_pll(struct anadig_softc *sc, int pll_ctrl)
126 {
127 	int reg;
128 
129 	reg = READ4(sc, pll_ctrl);
130 	reg &= ~(CTRL_BYPASS | CTRL_PWR);
131 	if (pll_ctrl == ANADIG_PLL3_CTRL || pll_ctrl == ANADIG_PLL7_CTRL) {
132 		/* It is USB PLL. Power bit logic is reversed */
133 		reg |= (CTRL_PWR | EN_USB_CLKS);
134 	}
135 	WRITE4(sc, pll_ctrl, reg);
136 
137 	/* Wait for PLL lock */
138 	while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED))
139 		;
140 
141 	reg = READ4(sc, pll_ctrl);
142 	reg |= (CTRL_PLL_EN);
143 	WRITE4(sc, pll_ctrl, reg);
144 
145 	return (0);
146 }
147 
148 static int
149 anadig_attach(device_t dev)
150 {
151 	struct anadig_softc *sc;
152 	int reg;
153 
154 	sc = device_get_softc(dev);
155 
156 	if (bus_alloc_resources(dev, anadig_spec, sc->res)) {
157 		device_printf(dev, "could not allocate resources\n");
158 		return (ENXIO);
159 	}
160 
161 	/* Memory interface */
162 	sc->bst = rman_get_bustag(sc->res[0]);
163 	sc->bsh = rman_get_bushandle(sc->res[0]);
164 
165 	/* Enable USB PLLs */
166 	enable_pll(sc, ANADIG_PLL3_CTRL);
167 	enable_pll(sc, ANADIG_PLL7_CTRL);
168 
169 	/* Enable other */
170 	enable_pll(sc, ANADIG_PLL1_CTRL);
171 	enable_pll(sc, ANADIG_PLL2_CTRL);
172 	enable_pll(sc, ANADIG_PLL4_CTRL);
173 	enable_pll(sc, ANADIG_PLL5_CTRL);
174 	enable_pll(sc, ANADIG_PLL6_CTRL);
175 
176 	/* Enable USB voltage regulator */
177 	reg = READ4(sc, ANADIG_REG_3P0);
178 	reg |= (ENABLE_LINREG);
179 	WRITE4(sc, ANADIG_REG_3P0, reg);
180 
181 	/* Give clocks to USB */
182 	reg = READ4(sc, USB_MISC(0));
183 	reg |= (EN_CLK_TO_UTMI);
184 	WRITE4(sc, USB_MISC(0), reg);
185 
186 	reg = READ4(sc, USB_MISC(1));
187 	reg |= (EN_CLK_TO_UTMI);
188 	WRITE4(sc, USB_MISC(1), reg);
189 
190 #if 0
191 	printf("USB_ANALOG_USB_MISC(0) == 0x%08x\n",
192 	    READ4(sc, USB_ANALOG_USB_MISC(0)));
193 	printf("USB_ANALOG_USB_MISC(1) == 0x%08x\n",
194 	    READ4(sc, USB_ANALOG_USB_MISC(1)));
195 #endif
196 
197 	return (0);
198 }
199 
200 static device_method_t anadig_methods[] = {
201 	DEVMETHOD(device_probe,		anadig_probe),
202 	DEVMETHOD(device_attach,	anadig_attach),
203 	{ 0, 0 }
204 };
205 
206 static driver_t anadig_driver = {
207 	"anadig",
208 	anadig_methods,
209 	sizeof(struct anadig_softc),
210 };
211 
212 static devclass_t anadig_devclass;
213 
214 DRIVER_MODULE(anadig, simplebus, anadig_driver, anadig_devclass, 0, 0);
215