1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Analog components control digital interface (ANADIG) 31 * Chapter 11, Vybrid Reference Manual, Rev. 5, 07/2013 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 #include <sys/watchdog.h> 44 45 #include <dev/ofw/openfirm.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <machine/bus.h> 50 #include <machine/cpu.h> 51 #include <machine/intr.h> 52 53 #include <arm/freescale/vybrid/vf_common.h> 54 55 #define ANADIG_PLL3_CTRL 0x010 /* PLL3 Control */ 56 #define ANADIG_PLL7_CTRL 0x020 /* PLL7 Control */ 57 #define ANADIG_PLL2_CTRL 0x030 /* PLL2 Control */ 58 #define ANADIG_PLL2_SS 0x040 /* PLL2 Spread Spectrum */ 59 #define ANADIG_PLL2_NUM 0x050 /* PLL2 Numerator */ 60 #define ANADIG_PLL2_DENOM 0x060 /* PLL2 Denominator */ 61 #define ANADIG_PLL4_CTRL 0x070 /* PLL4 Control */ 62 #define ANADIG_PLL4_NUM 0x080 /* PLL4 Numerator */ 63 #define ANADIG_PLL4_DENOM 0x090 /* PLL4 Denominator */ 64 #define ANADIG_PLL6_CTRL 0x0A0 /* PLL6 Control */ 65 #define ANADIG_PLL6_NUM 0x0B0 /* PLL6 Numerator */ 66 #define ANADIG_PLL6_DENOM 0x0C0 /* PLL6 Denominator */ 67 #define ANADIG_PLL5_CTRL 0x0E0 /* PLL5 Control */ 68 #define ANADIG_PLL3_PFD 0x0F0 /* PLL3 PFD */ 69 #define ANADIG_PLL2_PFD 0x100 /* PLL2 PFD */ 70 #define ANADIG_REG_1P1 0x110 /* Regulator 1P1 */ 71 #define ANADIG_REG_3P0 0x120 /* Regulator 3P0 */ 72 #define ANADIG_REG_2P5 0x130 /* Regulator 2P5 */ 73 #define ANADIG_ANA_MISC0 0x150 /* Analog Miscellaneous */ 74 #define ANADIG_ANA_MISC1 0x160 /* Analog Miscellaneous */ 75 #define ANADIG_ANADIG_DIGPROG 0x260 /* Digital Program */ 76 #define ANADIG_PLL1_CTRL 0x270 /* PLL1 Control */ 77 #define ANADIG_PLL1_SS 0x280 /* PLL1 Spread Spectrum */ 78 #define ANADIG_PLL1_NUM 0x290 /* PLL1 Numerator */ 79 #define ANADIG_PLL1_DENOM 0x2A0 /* PLL1 Denominator */ 80 #define ANADIG_PLL1_PFD 0x2B0 /* PLL1_PFD */ 81 #define ANADIG_PLL_LOCK 0x2C0 /* PLL Lock */ 82 83 #define USB_VBUS_DETECT(n) (0x1A0 + 0x60 * n) 84 #define USB_CHRG_DETECT(n) (0x1B0 + 0x60 * n) 85 #define USB_VBUS_DETECT_STATUS(n) (0x1C0 + 0x60 * n) 86 #define USB_CHRG_DETECT_STATUS(n) (0x1D0 + 0x60 * n) 87 #define USB_LOOPBACK(n) (0x1E0 + 0x60 * n) 88 #define USB_MISC(n) (0x1F0 + 0x60 * n) 89 90 #define ANADIG_PLL_LOCKED (1U << 31) 91 #define ENABLE_LINREG (1 << 0) 92 #define EN_CLK_TO_UTMI (1 << 30) 93 94 #define CTRL_BYPASS (1 << 16) 95 #define CTRL_PWR (1 << 12) 96 #define CTRL_PLL_EN (1 << 13) 97 #define EN_USB_CLKS (1 << 6) 98 99 #define PLL4_CTRL_DIV_SEL_S 0 100 #define PLL4_CTRL_DIV_SEL_M 0x7f 101 102 struct anadig_softc { 103 struct resource *res[1]; 104 bus_space_tag_t bst; 105 bus_space_handle_t bsh; 106 }; 107 108 struct anadig_softc *anadig_sc; 109 110 static struct resource_spec anadig_spec[] = { 111 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 112 { -1, 0 } 113 }; 114 115 static int 116 anadig_probe(device_t dev) 117 { 118 119 if (!ofw_bus_status_okay(dev)) 120 return (ENXIO); 121 122 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-anadig")) 123 return (ENXIO); 124 125 device_set_desc(dev, "Vybrid Family ANADIG Unit"); 126 return (BUS_PROBE_DEFAULT); 127 } 128 129 static int 130 enable_pll(struct anadig_softc *sc, int pll_ctrl) 131 { 132 int reg; 133 134 reg = READ4(sc, pll_ctrl); 135 reg &= ~(CTRL_BYPASS | CTRL_PWR); 136 if (pll_ctrl == ANADIG_PLL3_CTRL || pll_ctrl == ANADIG_PLL7_CTRL) { 137 /* It is USB PLL. Power bit logic is reversed */ 138 reg |= (CTRL_PWR | EN_USB_CLKS); 139 } 140 WRITE4(sc, pll_ctrl, reg); 141 142 /* Wait for PLL lock */ 143 while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED)) 144 ; 145 146 reg = READ4(sc, pll_ctrl); 147 reg |= (CTRL_PLL_EN); 148 WRITE4(sc, pll_ctrl, reg); 149 150 return (0); 151 } 152 153 uint32_t 154 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 155 { 156 struct anadig_softc *sc; 157 int reg; 158 159 sc = anadig_sc; 160 161 /* 162 * PLLout = Fsys * (MFI+(MFN/MFD)) 163 */ 164 165 reg = READ4(sc, ANADIG_PLL4_CTRL); 166 reg &= ~(PLL4_CTRL_DIV_SEL_M << PLL4_CTRL_DIV_SEL_S); 167 reg |= (mfi << PLL4_CTRL_DIV_SEL_S); 168 WRITE4(sc, ANADIG_PLL4_CTRL, reg); 169 WRITE4(sc, ANADIG_PLL4_NUM, mfn); 170 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); 171 172 return (0); 173 } 174 175 static int 176 anadig_attach(device_t dev) 177 { 178 struct anadig_softc *sc; 179 int reg; 180 181 sc = device_get_softc(dev); 182 183 if (bus_alloc_resources(dev, anadig_spec, sc->res)) { 184 device_printf(dev, "could not allocate resources\n"); 185 return (ENXIO); 186 } 187 188 /* Memory interface */ 189 sc->bst = rman_get_bustag(sc->res[0]); 190 sc->bsh = rman_get_bushandle(sc->res[0]); 191 192 anadig_sc = sc; 193 194 /* Enable USB PLLs */ 195 enable_pll(sc, ANADIG_PLL3_CTRL); 196 enable_pll(sc, ANADIG_PLL7_CTRL); 197 198 /* Enable other PLLs */ 199 enable_pll(sc, ANADIG_PLL1_CTRL); 200 enable_pll(sc, ANADIG_PLL2_CTRL); 201 enable_pll(sc, ANADIG_PLL4_CTRL); 202 enable_pll(sc, ANADIG_PLL5_CTRL); 203 enable_pll(sc, ANADIG_PLL6_CTRL); 204 205 /* Enable USB voltage regulator */ 206 reg = READ4(sc, ANADIG_REG_3P0); 207 reg |= (ENABLE_LINREG); 208 WRITE4(sc, ANADIG_REG_3P0, reg); 209 210 /* Give clocks to USB */ 211 reg = READ4(sc, USB_MISC(0)); 212 reg |= (EN_CLK_TO_UTMI); 213 WRITE4(sc, USB_MISC(0), reg); 214 215 reg = READ4(sc, USB_MISC(1)); 216 reg |= (EN_CLK_TO_UTMI); 217 WRITE4(sc, USB_MISC(1), reg); 218 219 #if 0 220 printf("USB_ANALOG_USB_MISC(0) == 0x%08x\n", 221 READ4(sc, USB_ANALOG_USB_MISC(0))); 222 printf("USB_ANALOG_USB_MISC(1) == 0x%08x\n", 223 READ4(sc, USB_ANALOG_USB_MISC(1))); 224 #endif 225 226 return (0); 227 } 228 229 static device_method_t anadig_methods[] = { 230 DEVMETHOD(device_probe, anadig_probe), 231 DEVMETHOD(device_attach, anadig_attach), 232 { 0, 0 } 233 }; 234 235 static driver_t anadig_driver = { 236 "anadig", 237 anadig_methods, 238 sizeof(struct anadig_softc), 239 }; 240 241 DRIVER_MODULE(anadig, simplebus, anadig_driver, 0, 0); 242