1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family 12-bit Analog to Digital Converter (ADC) 29 * Chapter 37, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <machine/bus.h> 51 #include <machine/fdt.h> 52 #include <machine/cpu.h> 53 #include <machine/intr.h> 54 55 #include <arm/freescale/vybrid/vf_common.h> 56 #include <arm/freescale/vybrid/vf_adc.h> 57 58 #define ADC_HC0 0x00 /* Ctrl reg for hardware triggers */ 59 #define ADC_HC1 0x04 /* Ctrl reg for hardware triggers */ 60 #define HC_AIEN (1 << 7) /* Conversion Complete Int Control */ 61 #define HC_ADCH_M 0x1f /* Input Channel Select Mask */ 62 #define HC_ADCH_S 0 /* Input Channel Select Shift */ 63 #define ADC_HS 0x08 /* Status register for HW triggers */ 64 #define HS_COCO0 (1 << 0) /* Conversion Complete Flag */ 65 #define HS_COCO1 (1 << 1) /* Conversion Complete Flag */ 66 #define ADC_R0 0x0C /* Data result reg for HW triggers */ 67 #define ADC_R1 0x10 /* Data result reg for HW triggers */ 68 #define ADC_CFG 0x14 /* Configuration register */ 69 #define CFG_OVWREN (1 << 16) /* Data Overwrite Enable */ 70 #define CFG_AVGS_M 0x3 /* Hardware Average select Mask */ 71 #define CFG_AVGS_S 14 /* Hardware Average select Shift */ 72 #define CFG_ADTRG (1 << 13) /* Conversion Trigger Select */ 73 #define CFG_REFSEL_M 0x3 /* Voltage Reference Select Mask */ 74 #define CFG_REFSEL_S 11 /* Voltage Reference Select Shift */ 75 #define CFG_ADHSC (1 << 10) /* High Speed Configuration */ 76 #define CFG_ADSTS_M 0x3 /* Defines the sample time duration */ 77 #define CFG_ADSTS_S 8 /* Defines the sample time duration */ 78 #define CFG_ADLPC (1 << 7) /* Low-Power Configuration */ 79 #define CFG_ADIV_M 0x3 /* Clock Divide Select */ 80 #define CFG_ADIV_S 5 /* Clock Divide Select */ 81 #define CFG_ADLSMP (1 << 4) /* Long Sample Time Configuration */ 82 #define CFG_MODE_M 0x3 /* Conversion Mode Selection Mask */ 83 #define CFG_MODE_S 2 /* Conversion Mode Selection Shift */ 84 #define CFG_MODE_12 0x2 /* 12-bit mode */ 85 #define CFG_ADICLK_M 0x3 /* Input Clock Select Mask */ 86 #define CFG_ADICLK_S 0 /* Input Clock Select Shift */ 87 #define ADC_GC 0x18 /* General control register */ 88 #define GC_CAL (1 << 7) /* Calibration */ 89 #define GC_ADCO (1 << 6) /* Continuous Conversion Enable */ 90 #define GC_AVGE (1 << 5) /* Hardware average enable */ 91 #define GC_ACFE (1 << 4) /* Compare Function Enable */ 92 #define GC_ACFGT (1 << 3) /* Compare Function Greater Than En */ 93 #define GC_ACREN (1 << 2) /* Compare Function Range En */ 94 #define GC_DMAEN (1 << 1) /* DMA Enable */ 95 #define GC_ADACKEN (1 << 0) /* Asynchronous clock output enable */ 96 #define ADC_GS 0x1C /* General status register */ 97 #define GS_AWKST (1 << 2) /* Asynchronous wakeup int status */ 98 #define GS_CALF (1 << 1) /* Calibration Failed Flag */ 99 #define GS_ADACT (1 << 0) /* Conversion Active */ 100 #define ADC_CV 0x20 /* Compare value register */ 101 #define CV_CV2_M 0xfff /* Compare Value 2 Mask */ 102 #define CV_CV2_S 16 /* Compare Value 2 Shift */ 103 #define CV_CV1_M 0xfff /* Compare Value 1 Mask */ 104 #define CV_CV1_S 0 /* Compare Value 1 Shift */ 105 #define ADC_OFS 0x24 /* Offset correction value register */ 106 #define OFS_SIGN 12 /* Sign bit */ 107 #define OFS_M 0xfff /* Offset value Mask */ 108 #define OFS_S 0 /* Offset value Shift */ 109 #define ADC_CAL 0x28 /* Calibration value register */ 110 #define CAL_CODE_M 0xf /* Calibration Result Value Mask */ 111 #define CAL_CODE_S 0 /* Calibration Result Value Shift */ 112 #define ADC_PCTL 0x30 /* Pin control register */ 113 114 struct adc_softc { 115 struct resource *res[2]; 116 bus_space_tag_t bst; 117 bus_space_handle_t bsh; 118 void *ih; 119 }; 120 121 struct adc_softc *adc_sc; 122 123 static struct resource_spec adc_spec[] = { 124 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 125 { SYS_RES_IRQ, 0, RF_ACTIVE }, 126 { -1, 0 } 127 }; 128 129 static int 130 adc_probe(device_t dev) 131 { 132 133 if (!ofw_bus_status_okay(dev)) 134 return (ENXIO); 135 136 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-adc")) 137 return (ENXIO); 138 139 device_set_desc(dev, "Vybrid Family " 140 "12-bit Analog to Digital Converter"); 141 return (BUS_PROBE_DEFAULT); 142 } 143 144 static void 145 adc_intr(void *arg) 146 { 147 struct adc_softc *sc; 148 149 sc = arg; 150 151 /* Conversation complete */ 152 } 153 154 uint32_t 155 adc_read(void) 156 { 157 struct adc_softc *sc; 158 159 sc = adc_sc; 160 if (sc == NULL) 161 return (0); 162 163 return (READ4(sc, ADC_R0)); 164 } 165 166 uint32_t 167 adc_enable(int channel) 168 { 169 struct adc_softc *sc; 170 int reg; 171 172 sc = adc_sc; 173 if (sc == NULL) 174 return (1); 175 176 reg = READ4(sc, ADC_HC0); 177 reg &= ~(HC_ADCH_M << HC_ADCH_S); 178 reg |= (channel << HC_ADCH_S); 179 WRITE4(sc, ADC_HC0, reg); 180 181 return (0); 182 } 183 184 static int 185 adc_attach(device_t dev) 186 { 187 struct adc_softc *sc; 188 int err; 189 int reg; 190 191 sc = device_get_softc(dev); 192 193 if (bus_alloc_resources(dev, adc_spec, sc->res)) { 194 device_printf(dev, "could not allocate resources\n"); 195 return (ENXIO); 196 } 197 198 /* Memory interface */ 199 sc->bst = rman_get_bustag(sc->res[0]); 200 sc->bsh = rman_get_bushandle(sc->res[0]); 201 202 adc_sc = sc; 203 204 /* Setup interrupt handler */ 205 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 206 NULL, adc_intr, sc, &sc->ih); 207 if (err) { 208 device_printf(dev, "Unable to alloc interrupt resource.\n"); 209 return (ENXIO); 210 } 211 212 /* Configure 12-bit mode */ 213 reg = READ4(sc, ADC_CFG); 214 reg &= ~(CFG_MODE_M << CFG_MODE_S); 215 reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */ 216 WRITE4(sc, ADC_CFG, reg); 217 218 /* Configure for continuous conversion */ 219 reg = READ4(sc, ADC_GC); 220 reg |= (GC_ADCO | GC_AVGE); 221 WRITE4(sc, ADC_GC, reg); 222 223 /* Disable interrupts */ 224 reg = READ4(sc, ADC_HC0); 225 reg &= HC_AIEN; 226 WRITE4(sc, ADC_HC0, reg); 227 228 return (0); 229 } 230 231 static device_method_t adc_methods[] = { 232 DEVMETHOD(device_probe, adc_probe), 233 DEVMETHOD(device_attach, adc_attach), 234 { 0, 0 } 235 }; 236 237 static driver_t adc_driver = { 238 "adc", 239 adc_methods, 240 sizeof(struct adc_softc), 241 }; 242 243 static devclass_t adc_devclass; 244 245 DRIVER_MODULE(adc, simplebus, adc_driver, adc_devclass, 0, 0); 246