1a2c472e7SAleksandr Rybalko /*- 2af3dc4a7SPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3af3dc4a7SPedro F. Giffuni * 494f8d6fdSAleksandr Rybalko * Copyright (c) 2012, 2013 The FreeBSD Foundation 5a2c472e7SAleksandr Rybalko * All rights reserved. 6a2c472e7SAleksandr Rybalko * 7a2c472e7SAleksandr Rybalko * This software was developed by Oleksandr Rybalko under sponsorship 8a2c472e7SAleksandr Rybalko * from the FreeBSD Foundation. 9a2c472e7SAleksandr Rybalko * 10a2c472e7SAleksandr Rybalko * Redistribution and use in source and binary forms, with or without 11a2c472e7SAleksandr Rybalko * modification, are permitted provided that the following conditions 12a2c472e7SAleksandr Rybalko * are met: 13a2c472e7SAleksandr Rybalko * 1. Redistributions of source code must retain the above copyright 14a2c472e7SAleksandr Rybalko * notice, this list of conditions and the following disclaimer. 15a2c472e7SAleksandr Rybalko * 2. Redistributions in binary form must reproduce the above copyright 16a2c472e7SAleksandr Rybalko * notice, this list of conditions and the following disclaimer in the 17a2c472e7SAleksandr Rybalko * documentation and/or other materials provided with the distribution. 18a2c472e7SAleksandr Rybalko * 19a2c472e7SAleksandr Rybalko * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20a2c472e7SAleksandr Rybalko * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21a2c472e7SAleksandr Rybalko * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22a2c472e7SAleksandr Rybalko * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23a2c472e7SAleksandr Rybalko * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24a2c472e7SAleksandr Rybalko * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25a2c472e7SAleksandr Rybalko * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26a2c472e7SAleksandr Rybalko * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27a2c472e7SAleksandr Rybalko * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28a2c472e7SAleksandr Rybalko * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29a2c472e7SAleksandr Rybalko * SUCH DAMAGE. 30a2c472e7SAleksandr Rybalko */ 31a2c472e7SAleksandr Rybalko 32a2c472e7SAleksandr Rybalko #include <sys/cdefs.h> 33a2c472e7SAleksandr Rybalko __FBSDID("$FreeBSD$"); 34a2c472e7SAleksandr Rybalko 35a2c472e7SAleksandr Rybalko #include <sys/param.h> 36a2c472e7SAleksandr Rybalko #include <sys/systm.h> 37a2c472e7SAleksandr Rybalko #include <sys/kernel.h> 38a2c472e7SAleksandr Rybalko #include <sys/module.h> 39a2c472e7SAleksandr Rybalko #include <sys/time.h> 40a2c472e7SAleksandr Rybalko #include <sys/bus.h> 41a2c472e7SAleksandr Rybalko #include <sys/resource.h> 42a2c472e7SAleksandr Rybalko #include <sys/rman.h> 43a2c472e7SAleksandr Rybalko #include <sys/watchdog.h> 44a2c472e7SAleksandr Rybalko 45a2c472e7SAleksandr Rybalko #include <machine/bus.h> 46a2c472e7SAleksandr Rybalko #include <machine/intr.h> 47a2c472e7SAleksandr Rybalko 48a2c472e7SAleksandr Rybalko #include <dev/ofw/openfirm.h> 49a2c472e7SAleksandr Rybalko #include <dev/ofw/ofw_bus.h> 50a2c472e7SAleksandr Rybalko #include <dev/ofw/ofw_bus_subr.h> 51a2c472e7SAleksandr Rybalko 52*4dbbaf20SIan Lepore #include <arm/freescale/imx/imx_machdep.h> 53a2c472e7SAleksandr Rybalko #include <arm/freescale/imx/imx_wdogreg.h> 54a2c472e7SAleksandr Rybalko 55a2c472e7SAleksandr Rybalko struct imx_wdog_softc { 56a2c472e7SAleksandr Rybalko struct mtx sc_mtx; 57a2c472e7SAleksandr Rybalko device_t sc_dev; 58a2c472e7SAleksandr Rybalko struct resource *sc_res[2]; 59*4dbbaf20SIan Lepore void *sc_ih; 60a2c472e7SAleksandr Rybalko uint32_t sc_timeout; 61*4dbbaf20SIan Lepore bool sc_pde_enabled; 62a2c472e7SAleksandr Rybalko }; 63a2c472e7SAleksandr Rybalko 64a2c472e7SAleksandr Rybalko static struct resource_spec imx_wdog_spec[] = { 65a2c472e7SAleksandr Rybalko { SYS_RES_MEMORY, 0, RF_ACTIVE }, 66a2c472e7SAleksandr Rybalko { SYS_RES_IRQ, 0, RF_ACTIVE }, 6776ecefceSIan Lepore RESOURCE_SPEC_END 68a2c472e7SAleksandr Rybalko }; 69a2c472e7SAleksandr Rybalko 7076ecefceSIan Lepore #define MEMRES 0 7176ecefceSIan Lepore #define IRQRES 1 7276ecefceSIan Lepore 73398c1838SIan Lepore static struct ofw_compat_data compat_data[] = { 74398c1838SIan Lepore {"fsl,imx6sx-wdt", 1}, 75398c1838SIan Lepore {"fsl,imx6sl-wdt", 1}, 76398c1838SIan Lepore {"fsl,imx6q-wdt", 1}, 77398c1838SIan Lepore {"fsl,imx53-wdt", 1}, 78398c1838SIan Lepore {"fsl,imx51-wdt", 1}, 79398c1838SIan Lepore {"fsl,imx50-wdt", 1}, 80398c1838SIan Lepore {"fsl,imx35-wdt", 1}, 81398c1838SIan Lepore {"fsl,imx27-wdt", 1}, 82398c1838SIan Lepore {"fsl,imx25-wdt", 1}, 83398c1838SIan Lepore {"fsl,imx21-wdt", 1}, 84398c1838SIan Lepore {NULL, 0} 85398c1838SIan Lepore }; 86398c1838SIan Lepore 8776ecefceSIan Lepore static inline uint16_t 8876ecefceSIan Lepore RD2(struct imx_wdog_softc *sc, bus_size_t offs) 8976ecefceSIan Lepore { 90a2c472e7SAleksandr Rybalko 915b810fe4SIan Lepore return (bus_read_2(sc->sc_res[MEMRES], offs)); 9276ecefceSIan Lepore } 93a2c472e7SAleksandr Rybalko 9476ecefceSIan Lepore static inline void 9576ecefceSIan Lepore WR2(struct imx_wdog_softc *sc, bus_size_t offs, uint16_t val) 9676ecefceSIan Lepore { 97a2c472e7SAleksandr Rybalko 985b810fe4SIan Lepore bus_write_2(sc->sc_res[MEMRES], offs, val); 9976ecefceSIan Lepore } 100a2c472e7SAleksandr Rybalko 101a2c472e7SAleksandr Rybalko static void 102a2c472e7SAleksandr Rybalko imx_watchdog(void *arg, u_int cmd, int *error) 103a2c472e7SAleksandr Rybalko { 104a2c472e7SAleksandr Rybalko struct imx_wdog_softc *sc; 105a2c472e7SAleksandr Rybalko uint16_t reg; 1066da71028SIan Lepore u_int timeout; 107a2c472e7SAleksandr Rybalko 108a2c472e7SAleksandr Rybalko sc = arg; 109a2c472e7SAleksandr Rybalko mtx_lock(&sc->sc_mtx); 1106da71028SIan Lepore if (cmd == 0) { 1116da71028SIan Lepore if (bootverbose) 1126da71028SIan Lepore device_printf(sc->sc_dev, "Can not be disabled.\n"); 1136da71028SIan Lepore *error = EOPNOTSUPP; 1146da71028SIan Lepore } else { 1156da71028SIan Lepore timeout = (u_int)((1ULL << (cmd & WD_INTERVAL)) / 1000000000U); 116a2c472e7SAleksandr Rybalko if (timeout > 1 && timeout < 128) { 117a2c472e7SAleksandr Rybalko if (timeout != sc->sc_timeout) { 118a2c472e7SAleksandr Rybalko sc->sc_timeout = timeout; 119398c1838SIan Lepore reg = RD2(sc, WDOG_CR_REG); 120a2c472e7SAleksandr Rybalko reg &= ~WDOG_CR_WT_MASK; 121a2c472e7SAleksandr Rybalko reg |= (timeout << (WDOG_CR_WT_SHIFT + 1)) & 122a2c472e7SAleksandr Rybalko WDOG_CR_WT_MASK; 1236da71028SIan Lepore WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE); 1246da71028SIan Lepore } 125a2c472e7SAleksandr Rybalko /* Refresh counter */ 126398c1838SIan Lepore WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1); 127398c1838SIan Lepore WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2); 128*4dbbaf20SIan Lepore /* Watchdog active, can disable rom-boot watchdog. */ 129*4dbbaf20SIan Lepore if (sc->sc_pde_enabled) { 130*4dbbaf20SIan Lepore sc->sc_pde_enabled = false; 131*4dbbaf20SIan Lepore reg = RD2(sc, WDOG_MCR_REG); 132*4dbbaf20SIan Lepore WR2(sc, WDOG_MCR_REG, reg & ~WDOG_MCR_PDE); 133*4dbbaf20SIan Lepore } 134a2c472e7SAleksandr Rybalko *error = 0; 135a2c472e7SAleksandr Rybalko } 136a2c472e7SAleksandr Rybalko } 137a2c472e7SAleksandr Rybalko mtx_unlock(&sc->sc_mtx); 138a2c472e7SAleksandr Rybalko } 139a2c472e7SAleksandr Rybalko 140a2c472e7SAleksandr Rybalko static int 141*4dbbaf20SIan Lepore imx_wdog_intr(void *arg) 142*4dbbaf20SIan Lepore { 143*4dbbaf20SIan Lepore struct imx_wdog_softc *sc = arg; 144*4dbbaf20SIan Lepore 145*4dbbaf20SIan Lepore /* 146*4dbbaf20SIan Lepore * When configured for external reset, the actual reset is supposed to 147*4dbbaf20SIan Lepore * happen when some external device responds to the assertion of the 148*4dbbaf20SIan Lepore * WDOG_B signal by asserting the POR signal to the chip. This 149*4dbbaf20SIan Lepore * interrupt handler is a backstop mechanism; it is set up to fire 150*4dbbaf20SIan Lepore * simultaneously with WDOG_B, and if the external reset happens we'll 151*4dbbaf20SIan Lepore * never actually make it to here. If we do make it here, just trigger 152*4dbbaf20SIan Lepore * a software reset. That code will see that external reset is 153*4dbbaf20SIan Lepore * configured, and it will wait for 1 second for it to take effect, then 154*4dbbaf20SIan Lepore * it will do a software reset as a fallback. 155*4dbbaf20SIan Lepore */ 156*4dbbaf20SIan Lepore imx_wdog_cpu_reset(BUS_SPACE_PHYSADDR(sc->sc_res[MEMRES], WDOG_CR_REG)); 157*4dbbaf20SIan Lepore 158*4dbbaf20SIan Lepore return (FILTER_HANDLED); /* unreached */ 159*4dbbaf20SIan Lepore } 160*4dbbaf20SIan Lepore 161*4dbbaf20SIan Lepore static int 162a2c472e7SAleksandr Rybalko imx_wdog_probe(device_t dev) 163a2c472e7SAleksandr Rybalko { 164a2c472e7SAleksandr Rybalko 165add35ed5SIan Lepore if (!ofw_bus_status_okay(dev)) 166add35ed5SIan Lepore return (ENXIO); 167add35ed5SIan Lepore 168398c1838SIan Lepore if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 169a2c472e7SAleksandr Rybalko return (ENXIO); 170a2c472e7SAleksandr Rybalko 171398c1838SIan Lepore device_set_desc(dev, "Freescale i.MX Watchdog"); 172a2c472e7SAleksandr Rybalko return (0); 173a2c472e7SAleksandr Rybalko } 174a2c472e7SAleksandr Rybalko 175a2c472e7SAleksandr Rybalko static int 176a2c472e7SAleksandr Rybalko imx_wdog_attach(device_t dev) 177a2c472e7SAleksandr Rybalko { 178a2c472e7SAleksandr Rybalko struct imx_wdog_softc *sc; 179a2c472e7SAleksandr Rybalko 180a2c472e7SAleksandr Rybalko sc = device_get_softc(dev); 181a2c472e7SAleksandr Rybalko sc->sc_dev = dev; 182a2c472e7SAleksandr Rybalko 183a2c472e7SAleksandr Rybalko if (bus_alloc_resources(dev, imx_wdog_spec, sc->sc_res)) { 184a2c472e7SAleksandr Rybalko device_printf(dev, "could not allocate resources\n"); 185a2c472e7SAleksandr Rybalko return (ENXIO); 186a2c472e7SAleksandr Rybalko } 187a2c472e7SAleksandr Rybalko 188a2c472e7SAleksandr Rybalko mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "imx_wdt", MTX_DEF); 189a2c472e7SAleksandr Rybalko 190*4dbbaf20SIan Lepore /* 191*4dbbaf20SIan Lepore * If we're configured to assert an external reset signal, set up the 192*4dbbaf20SIan Lepore * hardware to do so, and install an interrupt handler whose only 193*4dbbaf20SIan Lepore * purpose is to backstop the external reset. Don't worry if the 194*4dbbaf20SIan Lepore * interrupt setup fails, since it's only a backstop measure. 195*4dbbaf20SIan Lepore */ 196*4dbbaf20SIan Lepore if (ofw_bus_has_prop(sc->sc_dev, "fsl,ext-reset-output")) { 197*4dbbaf20SIan Lepore WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG)); 198*4dbbaf20SIan Lepore bus_setup_intr(sc->sc_dev, sc->sc_res[IRQRES], 199*4dbbaf20SIan Lepore INTR_TYPE_MISC | INTR_MPSAFE, imx_wdog_intr, NULL, sc, 200*4dbbaf20SIan Lepore &sc->sc_ih); 201*4dbbaf20SIan Lepore WR2(sc, WDOG_ICR_REG, WDOG_ICR_WIE); /* Enable, count is 0. */ 202*4dbbaf20SIan Lepore } 203*4dbbaf20SIan Lepore 204*4dbbaf20SIan Lepore /* 205*4dbbaf20SIan Lepore * Note whether the rom-boot so-called "power-down" watchdog is active, 206*4dbbaf20SIan Lepore * so we can disable it when the regular watchdog is first enabled. 207*4dbbaf20SIan Lepore */ 208*4dbbaf20SIan Lepore if (RD2(sc, WDOG_MCR_REG) & WDOG_MCR_PDE) 209*4dbbaf20SIan Lepore sc->sc_pde_enabled = true; 210a2c472e7SAleksandr Rybalko 211a2c472e7SAleksandr Rybalko EVENTHANDLER_REGISTER(watchdog_list, imx_watchdog, sc, 0); 212a2c472e7SAleksandr Rybalko return (0); 213a2c472e7SAleksandr Rybalko } 21476ecefceSIan Lepore 21576ecefceSIan Lepore static device_method_t imx_wdog_methods[] = { 21676ecefceSIan Lepore DEVMETHOD(device_probe, imx_wdog_probe), 21776ecefceSIan Lepore DEVMETHOD(device_attach, imx_wdog_attach), 21876ecefceSIan Lepore DEVMETHOD_END 21976ecefceSIan Lepore }; 22076ecefceSIan Lepore 22176ecefceSIan Lepore static driver_t imx_wdog_driver = { 22276ecefceSIan Lepore "imx_wdog", 22376ecefceSIan Lepore imx_wdog_methods, 22476ecefceSIan Lepore sizeof(struct imx_wdog_softc), 22576ecefceSIan Lepore }; 22676ecefceSIan Lepore 22776ecefceSIan Lepore static devclass_t imx_wdog_devclass; 22876ecefceSIan Lepore 22976ecefceSIan Lepore DRIVER_MODULE(imx_wdog, simplebus, imx_wdog_driver, imx_wdog_devclass, 0, 0); 230