1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* 31 * Driver for imx Enhanced Configurable SPI; master-mode only. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/gpio.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 #include <machine/intr.h> 47 48 #include <arm/freescale/imx/imx_ccmvar.h> 49 50 #include <dev/gpio/gpiobusvar.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 #include <dev/ofw/openfirm.h> 54 #include <dev/spibus/spi.h> 55 #include <dev/spibus/spibusvar.h> 56 57 #include "spibus_if.h" 58 59 #define ECSPI_RXDATA 0x00 60 #define ECSPI_TXDATA 0x04 61 #define ECSPI_CTLREG 0x08 62 #define CTLREG_BLEN_SHIFT 20 63 #define CTLREG_BLEN_MASK 0x0fff 64 #define CTLREG_CSEL_SHIFT 18 65 #define CTLREG_CSEL_MASK 0x03 66 #define CTLREG_DRCTL_SHIFT 16 67 #define CTLREG_DRCTL_MASK 0x03 68 #define CTLREG_PREDIV_SHIFT 12 69 #define CTLREG_PREDIV_MASK 0x0f 70 #define CTLREG_POSTDIV_SHIFT 8 71 #define CTLREG_POSTDIV_MASK 0x0f 72 #define CTLREG_CMODE_SHIFT 4 73 #define CTLREG_CMODE_MASK 0x0f 74 #define CTLREG_CMODES_MASTER (CTLREG_CMODE_MASK << CTLREG_CMODE_SHIFT) 75 #define CTLREG_SMC (1u << 3) 76 #define CTLREG_XCH (1u << 2) 77 #define CTLREG_HT (1u << 1) 78 #define CTLREG_EN (1u << 0) 79 #define ECSPI_CFGREG 0x0c 80 #define CFGREG_HTLEN_SHIFT 24 81 #define CFGREG_SCLKCTL_SHIFT 20 82 #define CFGREG_DATACTL_SHIFT 16 83 #define CFGREG_SSPOL_SHIFT 12 84 #define CFGREG_SSCTL_SHIFT 8 85 #define CFGREG_SCLKPOL_SHIFT 4 86 #define CFGREG_SCLKPHA_SHIFT 0 87 #define CFGREG_MASK 0x0f /* all CFGREG fields are 4 bits */ 88 #define ECSPI_INTREG 0x10 89 #define INTREG_TCEN (1u << 7) 90 #define INTREG_ROEN (1u << 6) 91 #define INTREG_RFEN (1u << 5) 92 #define INTREG_RDREN (1u << 4) 93 #define INTREG_RREN (1u << 3) 94 #define INTREG_TFEN (1u << 2) 95 #define INTREG_TDREN (1u << 1) 96 #define INTREG_TEEN (1u << 0) 97 #define ECSPI_DMAREG 0x14 98 #define DMA_RX_THRESH_SHIFT 16 99 #define DMA_RX_THRESH_MASK 0x3f 100 #define DMA_TX_THRESH_SHIFT 0 101 #define DMA_TX_THRESH_MASK 0x3f 102 #define ECSPI_STATREG 0x18 103 #define SREG_TC (1u << 7) 104 #define SREG_RO (1u << 6) 105 #define SREG_RF (1u << 5) 106 #define SREG_RDR (1u << 4) 107 #define SREG_RR (1u << 3) 108 #define SREG_TF (1u << 2) 109 #define SREG_TDR (1u << 1) 110 #define SREG_TE (1u << 0) 111 #define ECSPI_PERIODREG 0x1c 112 #define ECSPI_TESTREG 0x20 113 114 #define CS_MAX 4 /* Max number of chip selects. */ 115 #define CS_MASK 0x03 /* Mask flag bits out of chipsel. */ 116 117 #define FIFO_SIZE 64 118 #define FIFO_RXTHRESH 32 119 #define FIFO_TXTHRESH 32 120 121 struct spi_softc { 122 device_t dev; 123 device_t spibus; 124 struct mtx mtx; 125 struct resource *memres; 126 struct resource *intres; 127 void *inthandle; 128 gpio_pin_t cspins[CS_MAX]; 129 u_int debug; 130 u_int basefreq; 131 uint32_t ctlreg; 132 uint32_t intreg; 133 uint32_t fifocnt; 134 uint8_t *rxbuf; 135 uint32_t rxidx; 136 uint32_t rxlen; 137 uint8_t *txbuf; 138 uint32_t txidx; 139 uint32_t txlen; 140 }; 141 142 static struct ofw_compat_data compat_data[] = { 143 {"fsl,imx51-ecspi", true}, 144 {"fsl,imx53-ecspi", true}, 145 {"fsl,imx6dl-ecspi", true}, 146 {"fsl,imx6q-ecspi", true}, 147 {"fsl,imx6sx-ecspi", true}, 148 {"fsl,imx6ul-ecspi", true}, 149 {NULL, false} 150 }; 151 152 static inline uint32_t 153 RD4(struct spi_softc *sc, bus_size_t offset) 154 { 155 156 return (bus_read_4(sc->memres, offset)); 157 } 158 159 static inline void 160 WR4(struct spi_softc *sc, bus_size_t offset, uint32_t value) 161 { 162 163 bus_write_4(sc->memres, offset, value); 164 } 165 166 static u_int 167 spi_calc_clockdiv(struct spi_softc *sc, u_int busfreq) 168 { 169 u_int post, pre; 170 171 /* Returning 0 effectively sets both dividers to 1. */ 172 if (sc->basefreq <= busfreq) 173 return (0); 174 175 /* 176 * Brute-force this; all real-world bus speeds are going to be found on 177 * the 1st or 2nd time through this loop. 178 */ 179 for (post = 0; post < 16; ++post) { 180 pre = ((sc->basefreq >> post) / busfreq) - 1; 181 if (pre < 16) 182 break; 183 } 184 if (post == 16) { 185 /* The lowest we can go is ~115 Hz. */ 186 pre = 15; 187 post = 15; 188 } 189 190 if (sc->debug >= 2) { 191 device_printf(sc->dev, 192 "base %u bus %u; pre %u, post %u; actual busfreq %u\n", 193 sc->basefreq, busfreq, pre, post, 194 (sc->basefreq / (pre + 1)) / (1 << post)); 195 } 196 197 return (pre << CTLREG_PREDIV_SHIFT) | (post << CTLREG_POSTDIV_SHIFT); 198 } 199 200 static void 201 spi_set_chipsel(struct spi_softc *sc, u_int cs, bool active) 202 { 203 bool pinactive; 204 205 /* 206 * This is kinda crazy... the gpio pins for chipsel are defined as 207 * active-high in the dts, but are supposed to be treated as active-low 208 * by this driver. So to turn on chipsel we have to invert the value 209 * passed to gpio_pin_set_active(). Then, to make it more fun, any 210 * slave can say its chipsel is active-high, so if that option is 211 * on, we have to invert the value again. 212 */ 213 pinactive = !active ^ (bool)(cs & SPIBUS_CS_HIGH); 214 215 if (sc->debug >= 2) { 216 device_printf(sc->dev, "chipsel %u changed to %u\n", 217 (cs & ~SPIBUS_CS_HIGH), pinactive); 218 } 219 220 /* 221 * Change the pin, then do a dummy read of its current state to ensure 222 * that the state change reaches the hardware before proceeding. 223 */ 224 gpio_pin_set_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], pinactive); 225 gpio_pin_is_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], &pinactive); 226 } 227 228 static void 229 spi_hw_setup(struct spi_softc *sc, u_int cs, u_int mode, u_int freq) 230 { 231 uint32_t reg; 232 233 /* 234 * Set up control register, and write it first to bring the device out 235 * of reset. 236 */ 237 sc->ctlreg = CTLREG_EN | CTLREG_CMODES_MASTER | CTLREG_SMC; 238 sc->ctlreg |= spi_calc_clockdiv(sc, freq); 239 sc->ctlreg |= 7 << CTLREG_BLEN_SHIFT; /* XXX byte at a time */ 240 WR4(sc, ECSPI_CTLREG, sc->ctlreg); 241 242 /* 243 * Set up the config register. Note that we do all transfers with the 244 * SPI hardware's chip-select set to zero. The actual chip select is 245 * handled with a gpio pin. 246 */ 247 reg = 0; 248 if (cs & SPIBUS_CS_HIGH) 249 reg |= 1u << CFGREG_SSPOL_SHIFT; 250 if (mode & SPIBUS_MODE_CPHA) 251 reg |= 1u << CFGREG_SCLKPHA_SHIFT; 252 if (mode & SPIBUS_MODE_CPOL) { 253 reg |= 1u << CFGREG_SCLKPOL_SHIFT; 254 reg |= 1u << CFGREG_SCLKCTL_SHIFT; 255 } 256 WR4(sc, ECSPI_CFGREG, reg); 257 258 /* 259 * Set up the rx/tx FIFO interrupt thresholds. 260 */ 261 reg = (FIFO_RXTHRESH << DMA_RX_THRESH_SHIFT); 262 reg |= (FIFO_TXTHRESH << DMA_TX_THRESH_SHIFT); 263 WR4(sc, ECSPI_DMAREG, reg); 264 265 /* 266 * Do a dummy read, to make sure the preceding writes reach the spi 267 * hardware before we assert any gpio chip select. 268 */ 269 (void)RD4(sc, ECSPI_CFGREG); 270 } 271 272 static void 273 spi_empty_rxfifo(struct spi_softc *sc) 274 { 275 276 while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) { 277 sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA); 278 --sc->fifocnt; 279 } 280 } 281 282 static void 283 spi_fill_txfifo(struct spi_softc *sc) 284 { 285 286 while (sc->txidx < sc->txlen && sc->fifocnt < FIFO_SIZE) { 287 WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]); 288 ++sc->fifocnt; 289 } 290 291 /* 292 * If we're out of data, disable tx data ready (threshold) interrupts, 293 * and enable tx fifo empty interrupts. 294 */ 295 if (sc->txidx == sc->txlen) 296 sc->intreg = (sc->intreg & ~INTREG_TDREN) | INTREG_TEEN; 297 } 298 299 static void 300 spi_intr(void *arg) 301 { 302 struct spi_softc *sc = arg; 303 uint32_t intreg, status; 304 305 mtx_lock(&sc->mtx); 306 307 sc = arg; 308 intreg = sc->intreg; 309 status = RD4(sc, ECSPI_STATREG); 310 WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */ 311 312 /* 313 * If we get an overflow error, just signal that the transfer is done 314 * and wakeup the waiting thread, which will see that txidx != txlen and 315 * return an IO error to the caller. 316 */ 317 if (__predict_false(status & SREG_RO)) { 318 if (sc->debug || bootverbose) { 319 device_printf(sc->dev, "rxoverflow rxidx %u txidx %u\n", 320 sc->rxidx, sc->txidx); 321 } 322 sc->intreg = 0; 323 wakeup(sc); 324 mtx_unlock(&sc->mtx); 325 return; 326 } 327 328 if (status & SREG_RR) 329 spi_empty_rxfifo(sc); 330 331 if (status & SREG_TDR) 332 spi_fill_txfifo(sc); 333 334 /* 335 * If we're out of bytes to send... 336 * - If Transfer Complete is set (shift register is empty) and we've 337 * received everything we expect, we're all done. 338 * - Else if Tx Fifo Empty is set, we need to stop waiting for that and 339 * switch to waiting for Transfer Complete (wait for shift register 340 * to empty out), and also for Receive Ready (last of incoming data). 341 */ 342 if (sc->txidx == sc->txlen) { 343 if ((status & SREG_TC) && sc->fifocnt == 0) { 344 sc->intreg = 0; 345 wakeup(sc); 346 } else if (status & SREG_TE) { 347 sc->intreg &= ~(sc->intreg & ~INTREG_TEEN); 348 sc->intreg |= INTREG_TCEN | INTREG_RREN; 349 } 350 } 351 352 /* 353 * If interrupt flags changed, write the new flags to the hardware and 354 * do a dummy readback to ensure the changes reach the hardware before 355 * we exit the isr. 356 */ 357 if (sc->intreg != intreg) { 358 WR4(sc, ECSPI_INTREG, sc->intreg); 359 (void)RD4(sc, ECSPI_INTREG); 360 } 361 362 if (sc->debug >= 3) { 363 device_printf(sc->dev, 364 "spi_intr, sreg 0x%08x intreg was 0x%08x now 0x%08x\n", 365 status, intreg, sc->intreg); 366 } 367 368 mtx_unlock(&sc->mtx); 369 } 370 371 static int 372 spi_xfer_buf(struct spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len) 373 { 374 int err; 375 376 if (sc->debug >= 1) { 377 device_printf(sc->dev, 378 "spi_xfer_buf, rxbuf %p txbuf %p len %u\n", 379 rxbuf, txbuf, len); 380 } 381 382 if (len == 0) 383 return (0); 384 385 sc->rxbuf = rxbuf; 386 sc->rxlen = len; 387 sc->rxidx = 0; 388 sc->txbuf = txbuf; 389 sc->txlen = len; 390 sc->txidx = 0; 391 sc->intreg = INTREG_RDREN | INTREG_TDREN; 392 spi_fill_txfifo(sc); 393 394 /* Enable interrupts last; spi_fill_txfifo() can change sc->intreg */ 395 WR4(sc, ECSPI_INTREG, sc->intreg); 396 397 err = 0; 398 while (err == 0 && sc->intreg != 0) 399 err = msleep(sc, &sc->mtx, 0, "imxspi", 10 * hz); 400 401 if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen) 402 err = EIO; 403 404 return (err); 405 } 406 407 static int 408 spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 409 { 410 struct spi_softc *sc = device_get_softc(dev); 411 uint32_t cs, mode, clock; 412 int err; 413 414 spibus_get_cs(child, &cs); 415 spibus_get_clock(child, &clock); 416 spibus_get_mode(child, &mode); 417 418 if (cs > CS_MAX || sc->cspins[cs] == NULL) { 419 if (sc->debug || bootverbose) 420 device_printf(sc->dev, "Invalid chip select %u\n", cs); 421 return (EINVAL); 422 } 423 424 mtx_lock(&sc->mtx); 425 device_busy(sc->dev); 426 427 if (sc->debug >= 1) { 428 device_printf(sc->dev, 429 "spi_transfer, cs 0x%x clock %u mode %u\n", 430 cs, clock, mode); 431 } 432 433 /* Set up the hardware and select the device. */ 434 spi_hw_setup(sc, cs, mode, clock); 435 spi_set_chipsel(sc, cs, true); 436 437 /* Transfer command then data bytes. */ 438 err = 0; 439 if (cmd->tx_cmd_sz > 0) 440 err = spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd, 441 cmd->tx_cmd_sz); 442 if (cmd->tx_data_sz > 0 && err == 0) 443 err = spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data, 444 cmd->tx_data_sz); 445 446 /* Deselect the device, turn off (and reset) hardware. */ 447 spi_set_chipsel(sc, cs, false); 448 WR4(sc, ECSPI_CTLREG, 0); 449 450 device_unbusy(sc->dev); 451 mtx_unlock(&sc->mtx); 452 453 return (err); 454 } 455 456 static phandle_t 457 spi_get_node(device_t bus, device_t dev) 458 { 459 460 /* 461 * Share our controller node with our spibus child; it instantiates 462 * devices by walking the children contained within our node. 463 */ 464 return ofw_bus_get_node(bus); 465 } 466 467 static int 468 spi_detach(device_t dev) 469 { 470 struct spi_softc *sc = device_get_softc(dev); 471 int error, idx; 472 473 if ((error = bus_generic_detach(sc->dev)) != 0) 474 return (error); 475 476 if (sc->spibus != NULL) 477 device_delete_child(dev, sc->spibus); 478 479 for (idx = 0; idx < nitems(sc->cspins); ++idx) { 480 if (sc->cspins[idx] != NULL) 481 gpio_pin_release(sc->cspins[idx]); 482 } 483 484 if (sc->inthandle != NULL) 485 bus_teardown_intr(sc->dev, sc->intres, sc->inthandle); 486 if (sc->intres != NULL) 487 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->intres); 488 if (sc->memres != NULL) 489 bus_release_resource(sc->dev, SYS_RES_MEMORY, 0, sc->memres); 490 491 mtx_destroy(&sc->mtx); 492 493 return (0); 494 } 495 496 static int 497 spi_attach(device_t dev) 498 { 499 struct spi_softc *sc = device_get_softc(dev); 500 phandle_t node; 501 int err, idx, rid; 502 503 sc->dev = dev; 504 sc->basefreq = imx_ccm_ecspi_hz(); 505 506 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 507 508 /* Set up debug-enable sysctl. */ 509 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 510 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 511 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 512 "Enable debug, higher values = more info"); 513 514 /* Allocate mmio register access resources. */ 515 rid = 0; 516 sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, 517 RF_ACTIVE); 518 if (sc->memres == NULL) { 519 device_printf(sc->dev, "could not allocate registers\n"); 520 spi_detach(sc->dev); 521 return (ENXIO); 522 } 523 524 /* Allocate interrupt resources and set up handler. */ 525 rid = 0; 526 sc->intres = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, 527 RF_ACTIVE); 528 if (sc->intres == NULL) { 529 device_printf(sc->dev, "could not allocate interrupt\n"); 530 device_detach(sc->dev); 531 return (ENXIO); 532 } 533 err = bus_setup_intr(sc->dev, sc->intres, INTR_TYPE_MISC | INTR_MPSAFE, 534 NULL, spi_intr, sc, &sc->inthandle); 535 if (err != 0) { 536 device_printf(sc->dev, "could not setup interrupt handler"); 537 device_detach(sc->dev); 538 return (ENXIO); 539 } 540 541 /* Allocate gpio pins for configured chip selects. */ 542 node = ofw_bus_get_node(sc->dev); 543 for (idx = 0; idx < nitems(sc->cspins); ++idx) { 544 err = gpio_pin_get_by_ofw_propidx(sc->dev, node, "cs-gpios", 545 idx, &sc->cspins[idx]); 546 if (err == 0) { 547 gpio_pin_setflags(sc->cspins[idx], GPIO_PIN_OUTPUT); 548 } else if (sc->debug >= 2) { 549 device_printf(sc->dev, 550 "cannot configure gpio for chip select %u\n", idx); 551 } 552 } 553 554 /* 555 * Hardware init: put all channels into Master mode, turn off the enable 556 * bit (gates off clocks); we only enable the hardware while xfers run. 557 */ 558 WR4(sc, ECSPI_CTLREG, CTLREG_CMODES_MASTER); 559 560 /* 561 * Add the spibus driver as a child, and setup a one-shot intrhook to 562 * attach it after interrupts are working. It will attach actual SPI 563 * devices as its children, and those devices may need to do IO during 564 * their attach. We can't do IO until timers and interrupts are working. 565 */ 566 sc->spibus = device_add_child(dev, "spibus", DEVICE_UNIT_ANY); 567 return (bus_delayed_attach_children(dev)); 568 } 569 570 static int 571 spi_probe(device_t dev) 572 { 573 574 if (!ofw_bus_status_okay(dev)) 575 return (ENXIO); 576 577 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 578 return (ENXIO); 579 580 device_set_desc(dev, "i.MX ECSPI Master"); 581 return (BUS_PROBE_DEFAULT); 582 } 583 584 static device_method_t spi_methods[] = { 585 DEVMETHOD(device_probe, spi_probe), 586 DEVMETHOD(device_attach, spi_attach), 587 DEVMETHOD(device_detach, spi_detach), 588 589 /* spibus_if */ 590 DEVMETHOD(spibus_transfer, spi_transfer), 591 592 /* ofw_bus_if */ 593 DEVMETHOD(ofw_bus_get_node, spi_get_node), 594 595 DEVMETHOD_END 596 }; 597 598 static driver_t spi_driver = { 599 "imx_spi", 600 spi_methods, 601 sizeof(struct spi_softc), 602 }; 603 604 DRIVER_MODULE(imx_spi, simplebus, spi_driver, 0, 0); 605 DRIVER_MODULE(ofw_spibus, imx_spi, ofw_spibus_driver, 0, 0); 606 MODULE_DEPEND(imx_spi, ofw_spibus, 1, 1, 1); 607 SIMPLEBUS_PNP_INFO(compat_data); 608