1a0fd2339SIan Lepore /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3a0fd2339SIan Lepore *
4a0fd2339SIan Lepore * Copyright (c) 2018 Ian Lepore <ian@freebsd.org>
5a0fd2339SIan Lepore * All rights reserved.
6a0fd2339SIan Lepore *
7a0fd2339SIan Lepore * Redistribution and use in source and binary forms, with or without
8a0fd2339SIan Lepore * modification, are permitted provided that the following conditions
9a0fd2339SIan Lepore * are met:
10a0fd2339SIan Lepore * 1. Redistributions of source code must retain the above copyright
11a0fd2339SIan Lepore * notice, this list of conditions and the following disclaimer.
12a0fd2339SIan Lepore * 2. Redistributions in binary form must reproduce the above copyright
13a0fd2339SIan Lepore * notice, this list of conditions and the following disclaimer in the
14a0fd2339SIan Lepore * documentation and/or other materials provided with the distribution.
15a0fd2339SIan Lepore *
16a0fd2339SIan Lepore * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17a0fd2339SIan Lepore * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18a0fd2339SIan Lepore * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19a0fd2339SIan Lepore * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20a0fd2339SIan Lepore * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21a0fd2339SIan Lepore * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22a0fd2339SIan Lepore * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23a0fd2339SIan Lepore * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24a0fd2339SIan Lepore * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25a0fd2339SIan Lepore * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26a0fd2339SIan Lepore * SUCH DAMAGE.
27a0fd2339SIan Lepore */
28a0fd2339SIan Lepore
29a0fd2339SIan Lepore #include <sys/cdefs.h>
30a0fd2339SIan Lepore /*
31a0fd2339SIan Lepore * Driver for imx Enhanced Configurable SPI; master-mode only.
32a0fd2339SIan Lepore */
33a0fd2339SIan Lepore
34a0fd2339SIan Lepore #include <sys/param.h>
35a0fd2339SIan Lepore #include <sys/systm.h>
36a0fd2339SIan Lepore #include <sys/bus.h>
37a0fd2339SIan Lepore #include <sys/gpio.h>
38a0fd2339SIan Lepore #include <sys/kernel.h>
39a0fd2339SIan Lepore #include <sys/lock.h>
40a0fd2339SIan Lepore #include <sys/module.h>
41a0fd2339SIan Lepore #include <sys/mutex.h>
42a0fd2339SIan Lepore #include <sys/rman.h>
43a0fd2339SIan Lepore #include <sys/sysctl.h>
44a0fd2339SIan Lepore #include <machine/bus.h>
45a0fd2339SIan Lepore #include <machine/cpu.h>
46a0fd2339SIan Lepore #include <machine/intr.h>
47a0fd2339SIan Lepore
48a0fd2339SIan Lepore #include <arm/freescale/imx/imx_ccmvar.h>
49a0fd2339SIan Lepore
50a0fd2339SIan Lepore #include <dev/gpio/gpiobusvar.h>
51a0fd2339SIan Lepore #include <dev/ofw/ofw_bus.h>
52a0fd2339SIan Lepore #include <dev/ofw/ofw_bus_subr.h>
53a0fd2339SIan Lepore #include <dev/ofw/openfirm.h>
54a0fd2339SIan Lepore #include <dev/spibus/spi.h>
55a0fd2339SIan Lepore #include <dev/spibus/spibusvar.h>
56a0fd2339SIan Lepore
57a0fd2339SIan Lepore #include "spibus_if.h"
58a0fd2339SIan Lepore
59a0fd2339SIan Lepore #define ECSPI_RXDATA 0x00
60a0fd2339SIan Lepore #define ECSPI_TXDATA 0x04
61a0fd2339SIan Lepore #define ECSPI_CTLREG 0x08
62a0fd2339SIan Lepore #define CTLREG_BLEN_SHIFT 20
63a0fd2339SIan Lepore #define CTLREG_BLEN_MASK 0x0fff
64a0fd2339SIan Lepore #define CTLREG_CSEL_SHIFT 18
65a0fd2339SIan Lepore #define CTLREG_CSEL_MASK 0x03
66a0fd2339SIan Lepore #define CTLREG_DRCTL_SHIFT 16
67a0fd2339SIan Lepore #define CTLREG_DRCTL_MASK 0x03
68a0fd2339SIan Lepore #define CTLREG_PREDIV_SHIFT 12
69a0fd2339SIan Lepore #define CTLREG_PREDIV_MASK 0x0f
70a0fd2339SIan Lepore #define CTLREG_POSTDIV_SHIFT 8
71a0fd2339SIan Lepore #define CTLREG_POSTDIV_MASK 0x0f
72a0fd2339SIan Lepore #define CTLREG_CMODE_SHIFT 4
73a0fd2339SIan Lepore #define CTLREG_CMODE_MASK 0x0f
74a0fd2339SIan Lepore #define CTLREG_CMODES_MASTER (CTLREG_CMODE_MASK << CTLREG_CMODE_SHIFT)
75a0fd2339SIan Lepore #define CTLREG_SMC (1u << 3)
76a0fd2339SIan Lepore #define CTLREG_XCH (1u << 2)
77a0fd2339SIan Lepore #define CTLREG_HT (1u << 1)
78a0fd2339SIan Lepore #define CTLREG_EN (1u << 0)
79a0fd2339SIan Lepore #define ECSPI_CFGREG 0x0c
80a0fd2339SIan Lepore #define CFGREG_HTLEN_SHIFT 24
81a0fd2339SIan Lepore #define CFGREG_SCLKCTL_SHIFT 20
82a0fd2339SIan Lepore #define CFGREG_DATACTL_SHIFT 16
83a0fd2339SIan Lepore #define CFGREG_SSPOL_SHIFT 12
84a0fd2339SIan Lepore #define CFGREG_SSCTL_SHIFT 8
85a0fd2339SIan Lepore #define CFGREG_SCLKPOL_SHIFT 4
86a0fd2339SIan Lepore #define CFGREG_SCLKPHA_SHIFT 0
87a0fd2339SIan Lepore #define CFGREG_MASK 0x0f /* all CFGREG fields are 4 bits */
88a0fd2339SIan Lepore #define ECSPI_INTREG 0x10
89a0fd2339SIan Lepore #define INTREG_TCEN (1u << 7)
90a0fd2339SIan Lepore #define INTREG_ROEN (1u << 6)
91a0fd2339SIan Lepore #define INTREG_RFEN (1u << 5)
92a0fd2339SIan Lepore #define INTREG_RDREN (1u << 4)
93a0fd2339SIan Lepore #define INTREG_RREN (1u << 3)
94a0fd2339SIan Lepore #define INTREG_TFEN (1u << 2)
95a0fd2339SIan Lepore #define INTREG_TDREN (1u << 1)
96a0fd2339SIan Lepore #define INTREG_TEEN (1u << 0)
97a0fd2339SIan Lepore #define ECSPI_DMAREG 0x14
98a0fd2339SIan Lepore #define DMA_RX_THRESH_SHIFT 16
99a0fd2339SIan Lepore #define DMA_RX_THRESH_MASK 0x3f
100a0fd2339SIan Lepore #define DMA_TX_THRESH_SHIFT 0
101a0fd2339SIan Lepore #define DMA_TX_THRESH_MASK 0x3f
102a0fd2339SIan Lepore #define ECSPI_STATREG 0x18
103a0fd2339SIan Lepore #define SREG_TC (1u << 7)
104a0fd2339SIan Lepore #define SREG_RO (1u << 6)
105a0fd2339SIan Lepore #define SREG_RF (1u << 5)
106a0fd2339SIan Lepore #define SREG_RDR (1u << 4)
107a0fd2339SIan Lepore #define SREG_RR (1u << 3)
108a0fd2339SIan Lepore #define SREG_TF (1u << 2)
109a0fd2339SIan Lepore #define SREG_TDR (1u << 1)
110a0fd2339SIan Lepore #define SREG_TE (1u << 0)
111a0fd2339SIan Lepore #define ECSPI_PERIODREG 0x1c
112a0fd2339SIan Lepore #define ECSPI_TESTREG 0x20
113a0fd2339SIan Lepore
114a0fd2339SIan Lepore #define CS_MAX 4 /* Max number of chip selects. */
115a0fd2339SIan Lepore #define CS_MASK 0x03 /* Mask flag bits out of chipsel. */
116a0fd2339SIan Lepore
117a0fd2339SIan Lepore #define FIFO_SIZE 64
118a0fd2339SIan Lepore #define FIFO_RXTHRESH 32
119a0fd2339SIan Lepore #define FIFO_TXTHRESH 32
120a0fd2339SIan Lepore
121a0fd2339SIan Lepore struct spi_softc {
122a0fd2339SIan Lepore device_t dev;
123a0fd2339SIan Lepore device_t spibus;
124a0fd2339SIan Lepore struct mtx mtx;
125a0fd2339SIan Lepore struct resource *memres;
126a0fd2339SIan Lepore struct resource *intres;
127a0fd2339SIan Lepore void *inthandle;
128a0fd2339SIan Lepore gpio_pin_t cspins[CS_MAX];
129a0fd2339SIan Lepore u_int debug;
130a0fd2339SIan Lepore u_int basefreq;
131a0fd2339SIan Lepore uint32_t ctlreg;
132a0fd2339SIan Lepore uint32_t intreg;
133a0fd2339SIan Lepore uint32_t fifocnt;
134a0fd2339SIan Lepore uint8_t *rxbuf;
135a0fd2339SIan Lepore uint32_t rxidx;
136a0fd2339SIan Lepore uint32_t rxlen;
137a0fd2339SIan Lepore uint8_t *txbuf;
138a0fd2339SIan Lepore uint32_t txidx;
139a0fd2339SIan Lepore uint32_t txlen;
140a0fd2339SIan Lepore };
141a0fd2339SIan Lepore
142a0fd2339SIan Lepore static struct ofw_compat_data compat_data[] = {
143a0fd2339SIan Lepore {"fsl,imx51-ecspi", true},
144a0fd2339SIan Lepore {"fsl,imx53-ecspi", true},
145a0fd2339SIan Lepore {"fsl,imx6dl-ecspi", true},
146a0fd2339SIan Lepore {"fsl,imx6q-ecspi", true},
147a0fd2339SIan Lepore {"fsl,imx6sx-ecspi", true},
148a0fd2339SIan Lepore {"fsl,imx6ul-ecspi", true},
149a0fd2339SIan Lepore {NULL, false}
150a0fd2339SIan Lepore };
151a0fd2339SIan Lepore
152a0fd2339SIan Lepore static inline uint32_t
RD4(struct spi_softc * sc,bus_size_t offset)153a0fd2339SIan Lepore RD4(struct spi_softc *sc, bus_size_t offset)
154a0fd2339SIan Lepore {
155a0fd2339SIan Lepore
156a0fd2339SIan Lepore return (bus_read_4(sc->memres, offset));
157a0fd2339SIan Lepore }
158a0fd2339SIan Lepore
159a0fd2339SIan Lepore static inline void
WR4(struct spi_softc * sc,bus_size_t offset,uint32_t value)160a0fd2339SIan Lepore WR4(struct spi_softc *sc, bus_size_t offset, uint32_t value)
161a0fd2339SIan Lepore {
162a0fd2339SIan Lepore
163a0fd2339SIan Lepore bus_write_4(sc->memres, offset, value);
164a0fd2339SIan Lepore }
165a0fd2339SIan Lepore
166a0fd2339SIan Lepore static u_int
spi_calc_clockdiv(struct spi_softc * sc,u_int busfreq)167a0fd2339SIan Lepore spi_calc_clockdiv(struct spi_softc *sc, u_int busfreq)
168a0fd2339SIan Lepore {
169a0fd2339SIan Lepore u_int post, pre;
170a0fd2339SIan Lepore
171a0fd2339SIan Lepore /* Returning 0 effectively sets both dividers to 1. */
172a0fd2339SIan Lepore if (sc->basefreq <= busfreq)
173a0fd2339SIan Lepore return (0);
174a0fd2339SIan Lepore
175a0fd2339SIan Lepore /*
176a0fd2339SIan Lepore * Brute-force this; all real-world bus speeds are going to be found on
177a0fd2339SIan Lepore * the 1st or 2nd time through this loop.
178a0fd2339SIan Lepore */
179a0fd2339SIan Lepore for (post = 0; post < 16; ++post) {
180a0fd2339SIan Lepore pre = ((sc->basefreq >> post) / busfreq) - 1;
181a0fd2339SIan Lepore if (pre < 16)
182a0fd2339SIan Lepore break;
183a0fd2339SIan Lepore }
184a0fd2339SIan Lepore if (post == 16) {
185a0fd2339SIan Lepore /* The lowest we can go is ~115 Hz. */
186a0fd2339SIan Lepore pre = 15;
187a0fd2339SIan Lepore post = 15;
188a0fd2339SIan Lepore }
189a0fd2339SIan Lepore
190a0fd2339SIan Lepore if (sc->debug >= 2) {
191a0fd2339SIan Lepore device_printf(sc->dev,
192a0fd2339SIan Lepore "base %u bus %u; pre %u, post %u; actual busfreq %u\n",
193a0fd2339SIan Lepore sc->basefreq, busfreq, pre, post,
194a0fd2339SIan Lepore (sc->basefreq / (pre + 1)) / (1 << post));
195a0fd2339SIan Lepore }
196a0fd2339SIan Lepore
197a0fd2339SIan Lepore return (pre << CTLREG_PREDIV_SHIFT) | (post << CTLREG_POSTDIV_SHIFT);
198a0fd2339SIan Lepore }
199a0fd2339SIan Lepore
200a0fd2339SIan Lepore static void
spi_set_chipsel(struct spi_softc * sc,u_int cs,bool active)201a0fd2339SIan Lepore spi_set_chipsel(struct spi_softc *sc, u_int cs, bool active)
202a0fd2339SIan Lepore {
203a0fd2339SIan Lepore bool pinactive;
204a0fd2339SIan Lepore
205a0fd2339SIan Lepore /*
206a0fd2339SIan Lepore * This is kinda crazy... the gpio pins for chipsel are defined as
207a0fd2339SIan Lepore * active-high in the dts, but are supposed to be treated as active-low
208a0fd2339SIan Lepore * by this driver. So to turn on chipsel we have to invert the value
209a0fd2339SIan Lepore * passed to gpio_pin_set_active(). Then, to make it more fun, any
210a0fd2339SIan Lepore * slave can say its chipsel is active-high, so if that option is
211a0fd2339SIan Lepore * on, we have to invert the value again.
212a0fd2339SIan Lepore */
213a0fd2339SIan Lepore pinactive = !active ^ (bool)(cs & SPIBUS_CS_HIGH);
214a0fd2339SIan Lepore
215a0fd2339SIan Lepore if (sc->debug >= 2) {
216a0fd2339SIan Lepore device_printf(sc->dev, "chipsel %u changed to %u\n",
217a0fd2339SIan Lepore (cs & ~SPIBUS_CS_HIGH), pinactive);
218a0fd2339SIan Lepore }
219a0fd2339SIan Lepore
220a0fd2339SIan Lepore /*
221a0fd2339SIan Lepore * Change the pin, then do a dummy read of its current state to ensure
222a0fd2339SIan Lepore * that the state change reaches the hardware before proceeding.
223a0fd2339SIan Lepore */
224a0fd2339SIan Lepore gpio_pin_set_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], pinactive);
225a0fd2339SIan Lepore gpio_pin_is_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], &pinactive);
226a0fd2339SIan Lepore }
227a0fd2339SIan Lepore
228a0fd2339SIan Lepore static void
spi_hw_setup(struct spi_softc * sc,u_int cs,u_int mode,u_int freq)229a0fd2339SIan Lepore spi_hw_setup(struct spi_softc *sc, u_int cs, u_int mode, u_int freq)
230a0fd2339SIan Lepore {
231a0fd2339SIan Lepore uint32_t reg;
232a0fd2339SIan Lepore
233a0fd2339SIan Lepore /*
234a0fd2339SIan Lepore * Set up control register, and write it first to bring the device out
235a0fd2339SIan Lepore * of reset.
236a0fd2339SIan Lepore */
237a0fd2339SIan Lepore sc->ctlreg = CTLREG_EN | CTLREG_CMODES_MASTER | CTLREG_SMC;
238a0fd2339SIan Lepore sc->ctlreg |= spi_calc_clockdiv(sc, freq);
239a0fd2339SIan Lepore sc->ctlreg |= 7 << CTLREG_BLEN_SHIFT; /* XXX byte at a time */
240a0fd2339SIan Lepore WR4(sc, ECSPI_CTLREG, sc->ctlreg);
241a0fd2339SIan Lepore
242a0fd2339SIan Lepore /*
243a0fd2339SIan Lepore * Set up the config register. Note that we do all transfers with the
244a0fd2339SIan Lepore * SPI hardware's chip-select set to zero. The actual chip select is
245a0fd2339SIan Lepore * handled with a gpio pin.
246a0fd2339SIan Lepore */
247a0fd2339SIan Lepore reg = 0;
248a0fd2339SIan Lepore if (cs & SPIBUS_CS_HIGH)
249a0fd2339SIan Lepore reg |= 1u << CFGREG_SSPOL_SHIFT;
250a0fd2339SIan Lepore if (mode & SPIBUS_MODE_CPHA)
251a0fd2339SIan Lepore reg |= 1u << CFGREG_SCLKPHA_SHIFT;
252a0fd2339SIan Lepore if (mode & SPIBUS_MODE_CPOL) {
253a0fd2339SIan Lepore reg |= 1u << CFGREG_SCLKPOL_SHIFT;
254a0fd2339SIan Lepore reg |= 1u << CFGREG_SCLKCTL_SHIFT;
255a0fd2339SIan Lepore }
256a0fd2339SIan Lepore WR4(sc, ECSPI_CFGREG, reg);
257a0fd2339SIan Lepore
258a0fd2339SIan Lepore /*
259a0fd2339SIan Lepore * Set up the rx/tx FIFO interrupt thresholds.
260a0fd2339SIan Lepore */
261a0fd2339SIan Lepore reg = (FIFO_RXTHRESH << DMA_RX_THRESH_SHIFT);
262a0fd2339SIan Lepore reg |= (FIFO_TXTHRESH << DMA_TX_THRESH_SHIFT);
263a0fd2339SIan Lepore WR4(sc, ECSPI_DMAREG, reg);
264a0fd2339SIan Lepore
265a0fd2339SIan Lepore /*
266a0fd2339SIan Lepore * Do a dummy read, to make sure the preceding writes reach the spi
267a0fd2339SIan Lepore * hardware before we assert any gpio chip select.
268a0fd2339SIan Lepore */
269a0fd2339SIan Lepore (void)RD4(sc, ECSPI_CFGREG);
270a0fd2339SIan Lepore }
271a0fd2339SIan Lepore
272a0fd2339SIan Lepore static void
spi_empty_rxfifo(struct spi_softc * sc)273a0fd2339SIan Lepore spi_empty_rxfifo(struct spi_softc *sc)
274a0fd2339SIan Lepore {
275a0fd2339SIan Lepore
276a0fd2339SIan Lepore while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) {
277a0fd2339SIan Lepore sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA);
278a0fd2339SIan Lepore --sc->fifocnt;
279a0fd2339SIan Lepore }
280a0fd2339SIan Lepore }
281a0fd2339SIan Lepore
282a0fd2339SIan Lepore static void
spi_fill_txfifo(struct spi_softc * sc)283a0fd2339SIan Lepore spi_fill_txfifo(struct spi_softc *sc)
284a0fd2339SIan Lepore {
285a0fd2339SIan Lepore
286a0fd2339SIan Lepore while (sc->txidx < sc->txlen && sc->fifocnt < FIFO_SIZE) {
287a0fd2339SIan Lepore WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]);
288a0fd2339SIan Lepore ++sc->fifocnt;
289a0fd2339SIan Lepore }
290a0fd2339SIan Lepore
291a0fd2339SIan Lepore /*
292a0fd2339SIan Lepore * If we're out of data, disable tx data ready (threshold) interrupts,
293a0fd2339SIan Lepore * and enable tx fifo empty interrupts.
294a0fd2339SIan Lepore */
295a0fd2339SIan Lepore if (sc->txidx == sc->txlen)
296a0fd2339SIan Lepore sc->intreg = (sc->intreg & ~INTREG_TDREN) | INTREG_TEEN;
297a0fd2339SIan Lepore }
298a0fd2339SIan Lepore
299a0fd2339SIan Lepore static void
spi_intr(void * arg)300a0fd2339SIan Lepore spi_intr(void *arg)
301a0fd2339SIan Lepore {
302a0fd2339SIan Lepore struct spi_softc *sc = arg;
303a0fd2339SIan Lepore uint32_t intreg, status;
304a0fd2339SIan Lepore
305a0fd2339SIan Lepore mtx_lock(&sc->mtx);
306a0fd2339SIan Lepore
307a0fd2339SIan Lepore sc = arg;
308a0fd2339SIan Lepore intreg = sc->intreg;
309a0fd2339SIan Lepore status = RD4(sc, ECSPI_STATREG);
310a0fd2339SIan Lepore WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */
311a0fd2339SIan Lepore
312a0fd2339SIan Lepore /*
313a0fd2339SIan Lepore * If we get an overflow error, just signal that the transfer is done
314a0fd2339SIan Lepore * and wakeup the waiting thread, which will see that txidx != txlen and
315a0fd2339SIan Lepore * return an IO error to the caller.
316a0fd2339SIan Lepore */
317a0fd2339SIan Lepore if (__predict_false(status & SREG_RO)) {
318a0fd2339SIan Lepore if (sc->debug || bootverbose) {
319a0fd2339SIan Lepore device_printf(sc->dev, "rxoverflow rxidx %u txidx %u\n",
320a0fd2339SIan Lepore sc->rxidx, sc->txidx);
321a0fd2339SIan Lepore }
322a0fd2339SIan Lepore sc->intreg = 0;
323a0fd2339SIan Lepore wakeup(sc);
324a0fd2339SIan Lepore mtx_unlock(&sc->mtx);
325a0fd2339SIan Lepore return;
326a0fd2339SIan Lepore }
327a0fd2339SIan Lepore
328a0fd2339SIan Lepore if (status & SREG_RR)
329a0fd2339SIan Lepore spi_empty_rxfifo(sc);
330a0fd2339SIan Lepore
331a0fd2339SIan Lepore if (status & SREG_TDR)
332a0fd2339SIan Lepore spi_fill_txfifo(sc);
333a0fd2339SIan Lepore
334a0fd2339SIan Lepore /*
335a0fd2339SIan Lepore * If we're out of bytes to send...
336a0fd2339SIan Lepore * - If Transfer Complete is set (shift register is empty) and we've
337a0fd2339SIan Lepore * received everything we expect, we're all done.
338a0fd2339SIan Lepore * - Else if Tx Fifo Empty is set, we need to stop waiting for that and
339a0fd2339SIan Lepore * switch to waiting for Transfer Complete (wait for shift register
340a0fd2339SIan Lepore * to empty out), and also for Receive Ready (last of incoming data).
341a0fd2339SIan Lepore */
342a0fd2339SIan Lepore if (sc->txidx == sc->txlen) {
343a0fd2339SIan Lepore if ((status & SREG_TC) && sc->fifocnt == 0) {
344a0fd2339SIan Lepore sc->intreg = 0;
345a0fd2339SIan Lepore wakeup(sc);
346a0fd2339SIan Lepore } else if (status & SREG_TE) {
347a0fd2339SIan Lepore sc->intreg &= ~(sc->intreg & ~INTREG_TEEN);
348a0fd2339SIan Lepore sc->intreg |= INTREG_TCEN | INTREG_RREN;
349a0fd2339SIan Lepore }
350a0fd2339SIan Lepore }
351a0fd2339SIan Lepore
352a0fd2339SIan Lepore /*
353a0fd2339SIan Lepore * If interrupt flags changed, write the new flags to the hardware and
354a0fd2339SIan Lepore * do a dummy readback to ensure the changes reach the hardware before
355a0fd2339SIan Lepore * we exit the isr.
356a0fd2339SIan Lepore */
357a0fd2339SIan Lepore if (sc->intreg != intreg) {
358a0fd2339SIan Lepore WR4(sc, ECSPI_INTREG, sc->intreg);
359a0fd2339SIan Lepore (void)RD4(sc, ECSPI_INTREG);
360a0fd2339SIan Lepore }
361a0fd2339SIan Lepore
362a0fd2339SIan Lepore if (sc->debug >= 3) {
363a0fd2339SIan Lepore device_printf(sc->dev,
364a0fd2339SIan Lepore "spi_intr, sreg 0x%08x intreg was 0x%08x now 0x%08x\n",
365a0fd2339SIan Lepore status, intreg, sc->intreg);
366a0fd2339SIan Lepore }
367a0fd2339SIan Lepore
368a0fd2339SIan Lepore mtx_unlock(&sc->mtx);
369a0fd2339SIan Lepore }
370a0fd2339SIan Lepore
371a0fd2339SIan Lepore static int
spi_xfer_buf(struct spi_softc * sc,void * rxbuf,void * txbuf,uint32_t len)372a0fd2339SIan Lepore spi_xfer_buf(struct spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len)
373a0fd2339SIan Lepore {
374a0fd2339SIan Lepore int err;
375a0fd2339SIan Lepore
376a0fd2339SIan Lepore if (sc->debug >= 1) {
377a0fd2339SIan Lepore device_printf(sc->dev,
378a0fd2339SIan Lepore "spi_xfer_buf, rxbuf %p txbuf %p len %u\n",
379a0fd2339SIan Lepore rxbuf, txbuf, len);
380a0fd2339SIan Lepore }
381a0fd2339SIan Lepore
382a0fd2339SIan Lepore if (len == 0)
383a0fd2339SIan Lepore return (0);
384a0fd2339SIan Lepore
385a0fd2339SIan Lepore sc->rxbuf = rxbuf;
386a0fd2339SIan Lepore sc->rxlen = len;
387a0fd2339SIan Lepore sc->rxidx = 0;
388a0fd2339SIan Lepore sc->txbuf = txbuf;
389a0fd2339SIan Lepore sc->txlen = len;
390a0fd2339SIan Lepore sc->txidx = 0;
391a0fd2339SIan Lepore sc->intreg = INTREG_RDREN | INTREG_TDREN;
392a0fd2339SIan Lepore spi_fill_txfifo(sc);
393a0fd2339SIan Lepore
394a0fd2339SIan Lepore /* Enable interrupts last; spi_fill_txfifo() can change sc->intreg */
395a0fd2339SIan Lepore WR4(sc, ECSPI_INTREG, sc->intreg);
396a0fd2339SIan Lepore
397a0fd2339SIan Lepore err = 0;
398a0fd2339SIan Lepore while (err == 0 && sc->intreg != 0)
399a0fd2339SIan Lepore err = msleep(sc, &sc->mtx, 0, "imxspi", 10 * hz);
400a0fd2339SIan Lepore
401a0fd2339SIan Lepore if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen)
402a0fd2339SIan Lepore err = EIO;
403a0fd2339SIan Lepore
404a0fd2339SIan Lepore return (err);
405a0fd2339SIan Lepore }
406a0fd2339SIan Lepore
407a0fd2339SIan Lepore static int
spi_transfer(device_t dev,device_t child,struct spi_command * cmd)408a0fd2339SIan Lepore spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
409a0fd2339SIan Lepore {
410a0fd2339SIan Lepore struct spi_softc *sc = device_get_softc(dev);
411a0fd2339SIan Lepore uint32_t cs, mode, clock;
412a0fd2339SIan Lepore int err;
413a0fd2339SIan Lepore
414a0fd2339SIan Lepore spibus_get_cs(child, &cs);
415a0fd2339SIan Lepore spibus_get_clock(child, &clock);
416a0fd2339SIan Lepore spibus_get_mode(child, &mode);
417a0fd2339SIan Lepore
418a0fd2339SIan Lepore if (cs > CS_MAX || sc->cspins[cs] == NULL) {
419a0fd2339SIan Lepore if (sc->debug || bootverbose)
420a0fd2339SIan Lepore device_printf(sc->dev, "Invalid chip select %u\n", cs);
421a0fd2339SIan Lepore return (EINVAL);
422a0fd2339SIan Lepore }
423a0fd2339SIan Lepore
424a0fd2339SIan Lepore mtx_lock(&sc->mtx);
4256daa4a40SIan Lepore device_busy(sc->dev);
426a0fd2339SIan Lepore
427a0fd2339SIan Lepore if (sc->debug >= 1) {
428a0fd2339SIan Lepore device_printf(sc->dev,
429a0fd2339SIan Lepore "spi_transfer, cs 0x%x clock %u mode %u\n",
430a0fd2339SIan Lepore cs, clock, mode);
431a0fd2339SIan Lepore }
432a0fd2339SIan Lepore
433a0fd2339SIan Lepore /* Set up the hardware and select the device. */
434a0fd2339SIan Lepore spi_hw_setup(sc, cs, mode, clock);
435a0fd2339SIan Lepore spi_set_chipsel(sc, cs, true);
436a0fd2339SIan Lepore
437a0fd2339SIan Lepore /* Transfer command then data bytes. */
438a0fd2339SIan Lepore err = 0;
439a0fd2339SIan Lepore if (cmd->tx_cmd_sz > 0)
440a0fd2339SIan Lepore err = spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
441a0fd2339SIan Lepore cmd->tx_cmd_sz);
442a0fd2339SIan Lepore if (cmd->tx_data_sz > 0 && err == 0)
443a0fd2339SIan Lepore err = spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
444a0fd2339SIan Lepore cmd->tx_data_sz);
445a0fd2339SIan Lepore
446a0fd2339SIan Lepore /* Deselect the device, turn off (and reset) hardware. */
447a0fd2339SIan Lepore spi_set_chipsel(sc, cs, false);
448a0fd2339SIan Lepore WR4(sc, ECSPI_CTLREG, 0);
449a0fd2339SIan Lepore
4506daa4a40SIan Lepore device_unbusy(sc->dev);
451a0fd2339SIan Lepore mtx_unlock(&sc->mtx);
452a0fd2339SIan Lepore
453a0fd2339SIan Lepore return (err);
454a0fd2339SIan Lepore }
455a0fd2339SIan Lepore
456a0fd2339SIan Lepore static phandle_t
spi_get_node(device_t bus,device_t dev)457a0fd2339SIan Lepore spi_get_node(device_t bus, device_t dev)
458a0fd2339SIan Lepore {
459a0fd2339SIan Lepore
460a0fd2339SIan Lepore /*
461a0fd2339SIan Lepore * Share our controller node with our spibus child; it instantiates
462a0fd2339SIan Lepore * devices by walking the children contained within our node.
463a0fd2339SIan Lepore */
464a0fd2339SIan Lepore return ofw_bus_get_node(bus);
465a0fd2339SIan Lepore }
466a0fd2339SIan Lepore
467a0fd2339SIan Lepore static int
spi_detach(device_t dev)468a0fd2339SIan Lepore spi_detach(device_t dev)
469a0fd2339SIan Lepore {
470a0fd2339SIan Lepore struct spi_softc *sc = device_get_softc(dev);
4716daa4a40SIan Lepore int error, idx;
472a0fd2339SIan Lepore
4736daa4a40SIan Lepore if ((error = bus_generic_detach(sc->dev)) != 0)
4746daa4a40SIan Lepore return (error);
475a0fd2339SIan Lepore
476a0fd2339SIan Lepore if (sc->spibus != NULL)
477a0fd2339SIan Lepore device_delete_child(dev, sc->spibus);
478a0fd2339SIan Lepore
479a0fd2339SIan Lepore for (idx = 0; idx < nitems(sc->cspins); ++idx) {
480a0fd2339SIan Lepore if (sc->cspins[idx] != NULL)
481a0fd2339SIan Lepore gpio_pin_release(sc->cspins[idx]);
482a0fd2339SIan Lepore }
483a0fd2339SIan Lepore
484a0fd2339SIan Lepore if (sc->inthandle != NULL)
485a0fd2339SIan Lepore bus_teardown_intr(sc->dev, sc->intres, sc->inthandle);
486a0fd2339SIan Lepore if (sc->intres != NULL)
487a0fd2339SIan Lepore bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->intres);
488a0fd2339SIan Lepore if (sc->memres != NULL)
489a0fd2339SIan Lepore bus_release_resource(sc->dev, SYS_RES_MEMORY, 0, sc->memres);
490a0fd2339SIan Lepore
491a0fd2339SIan Lepore mtx_destroy(&sc->mtx);
492a0fd2339SIan Lepore
493a0fd2339SIan Lepore return (0);
494a0fd2339SIan Lepore }
495a0fd2339SIan Lepore
496a0fd2339SIan Lepore static int
spi_attach(device_t dev)497a0fd2339SIan Lepore spi_attach(device_t dev)
498a0fd2339SIan Lepore {
499a0fd2339SIan Lepore struct spi_softc *sc = device_get_softc(dev);
500a0fd2339SIan Lepore phandle_t node;
501a0fd2339SIan Lepore int err, idx, rid;
502a0fd2339SIan Lepore
503a0fd2339SIan Lepore sc->dev = dev;
504a0fd2339SIan Lepore sc->basefreq = imx_ccm_ecspi_hz();
505a0fd2339SIan Lepore
506a0fd2339SIan Lepore mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
507a0fd2339SIan Lepore
508a0fd2339SIan Lepore /* Set up debug-enable sysctl. */
509a0fd2339SIan Lepore SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
510a0fd2339SIan Lepore SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
511a0fd2339SIan Lepore OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0,
512a0fd2339SIan Lepore "Enable debug, higher values = more info");
513a0fd2339SIan Lepore
514a0fd2339SIan Lepore /* Allocate mmio register access resources. */
515a0fd2339SIan Lepore rid = 0;
516a0fd2339SIan Lepore sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
517a0fd2339SIan Lepore RF_ACTIVE);
518a0fd2339SIan Lepore if (sc->memres == NULL) {
519a0fd2339SIan Lepore device_printf(sc->dev, "could not allocate registers\n");
520a0fd2339SIan Lepore spi_detach(sc->dev);
521a0fd2339SIan Lepore return (ENXIO);
522a0fd2339SIan Lepore }
523a0fd2339SIan Lepore
524a0fd2339SIan Lepore /* Allocate interrupt resources and set up handler. */
525a0fd2339SIan Lepore rid = 0;
526a0fd2339SIan Lepore sc->intres = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
527a0fd2339SIan Lepore RF_ACTIVE);
528a0fd2339SIan Lepore if (sc->intres == NULL) {
529a0fd2339SIan Lepore device_printf(sc->dev, "could not allocate interrupt\n");
530a0fd2339SIan Lepore device_detach(sc->dev);
531a0fd2339SIan Lepore return (ENXIO);
532a0fd2339SIan Lepore }
533a0fd2339SIan Lepore err = bus_setup_intr(sc->dev, sc->intres, INTR_TYPE_MISC | INTR_MPSAFE,
534a0fd2339SIan Lepore NULL, spi_intr, sc, &sc->inthandle);
535a0fd2339SIan Lepore if (err != 0) {
536a0fd2339SIan Lepore device_printf(sc->dev, "could not setup interrupt handler");
537a0fd2339SIan Lepore device_detach(sc->dev);
538a0fd2339SIan Lepore return (ENXIO);
539a0fd2339SIan Lepore }
540a0fd2339SIan Lepore
541a0fd2339SIan Lepore /* Allocate gpio pins for configured chip selects. */
542a0fd2339SIan Lepore node = ofw_bus_get_node(sc->dev);
543a3389cb7SIan Lepore for (idx = 0; idx < nitems(sc->cspins); ++idx) {
544a0fd2339SIan Lepore err = gpio_pin_get_by_ofw_propidx(sc->dev, node, "cs-gpios",
545a0fd2339SIan Lepore idx, &sc->cspins[idx]);
546a0fd2339SIan Lepore if (err == 0) {
547a0fd2339SIan Lepore gpio_pin_setflags(sc->cspins[idx], GPIO_PIN_OUTPUT);
548a0fd2339SIan Lepore } else if (sc->debug >= 2) {
549a0fd2339SIan Lepore device_printf(sc->dev,
550a0fd2339SIan Lepore "cannot configure gpio for chip select %u\n", idx);
551a0fd2339SIan Lepore }
552a0fd2339SIan Lepore }
553a0fd2339SIan Lepore
554a0fd2339SIan Lepore /*
555a0fd2339SIan Lepore * Hardware init: put all channels into Master mode, turn off the enable
556a0fd2339SIan Lepore * bit (gates off clocks); we only enable the hardware while xfers run.
557a0fd2339SIan Lepore */
558a0fd2339SIan Lepore WR4(sc, ECSPI_CTLREG, CTLREG_CMODES_MASTER);
559a0fd2339SIan Lepore
560b1dbbe4dSIan Lepore /*
561b1dbbe4dSIan Lepore * Add the spibus driver as a child, and setup a one-shot intrhook to
562b1dbbe4dSIan Lepore * attach it after interrupts are working. It will attach actual SPI
563b1dbbe4dSIan Lepore * devices as its children, and those devices may need to do IO during
564b1dbbe4dSIan Lepore * their attach. We can't do IO until timers and interrupts are working.
565b1dbbe4dSIan Lepore */
5665b56413dSWarner Losh sc->spibus = device_add_child(dev, "spibus", DEVICE_UNIT_ANY);
567*34f5de82SJohn Baldwin bus_delayed_attach_children(dev);
568*34f5de82SJohn Baldwin return (0);
569a0fd2339SIan Lepore }
570a0fd2339SIan Lepore
571a0fd2339SIan Lepore static int
spi_probe(device_t dev)572a0fd2339SIan Lepore spi_probe(device_t dev)
573a0fd2339SIan Lepore {
574a0fd2339SIan Lepore
575a0fd2339SIan Lepore if (!ofw_bus_status_okay(dev))
576a0fd2339SIan Lepore return (ENXIO);
577a0fd2339SIan Lepore
578a0fd2339SIan Lepore if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
579a0fd2339SIan Lepore return (ENXIO);
580a0fd2339SIan Lepore
581a0fd2339SIan Lepore device_set_desc(dev, "i.MX ECSPI Master");
582a0fd2339SIan Lepore return (BUS_PROBE_DEFAULT);
583a0fd2339SIan Lepore }
584a0fd2339SIan Lepore
585a0fd2339SIan Lepore static device_method_t spi_methods[] = {
586a0fd2339SIan Lepore DEVMETHOD(device_probe, spi_probe),
587a0fd2339SIan Lepore DEVMETHOD(device_attach, spi_attach),
588a0fd2339SIan Lepore DEVMETHOD(device_detach, spi_detach),
589a0fd2339SIan Lepore
590a0fd2339SIan Lepore /* spibus_if */
591a0fd2339SIan Lepore DEVMETHOD(spibus_transfer, spi_transfer),
592a0fd2339SIan Lepore
593a0fd2339SIan Lepore /* ofw_bus_if */
594a0fd2339SIan Lepore DEVMETHOD(ofw_bus_get_node, spi_get_node),
595a0fd2339SIan Lepore
596a0fd2339SIan Lepore DEVMETHOD_END
597a0fd2339SIan Lepore };
598a0fd2339SIan Lepore
599a0fd2339SIan Lepore static driver_t spi_driver = {
600a0fd2339SIan Lepore "imx_spi",
601a0fd2339SIan Lepore spi_methods,
602a0fd2339SIan Lepore sizeof(struct spi_softc),
603a0fd2339SIan Lepore };
604a0fd2339SIan Lepore
605ea538dabSJohn Baldwin DRIVER_MODULE(imx_spi, simplebus, spi_driver, 0, 0);
6065f31d14aSJohn Baldwin DRIVER_MODULE(ofw_spibus, imx_spi, ofw_spibus_driver, 0, 0);
607a0fd2339SIan Lepore MODULE_DEPEND(imx_spi, ofw_spibus, 1, 1, 1);
6084c2b4396SIan Lepore SIMPLEBUS_PNP_INFO(compat_data);
609