1 /*- 2 * Copyright (c) 2014 Ian Lepore 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Pin mux and pad control driver for imx5 and imx6. 31 * 32 * This driver implements the fdt_pinctrl interface for configuring the gpio and 33 * peripheral pins based on fdt configuration data. 34 * 35 * When the driver attaches, it walks the entire fdt tree and automatically 36 * configures the pins for each device which has a pinctrl-0 property and whose 37 * status is "okay". In addition it implements the fdt_pinctrl_configure() 38 * method which any other driver can call at any time to reconfigure its pins. 39 * 40 * The nature of the fsl,pins property in fdt data makes this driver's job very 41 * easy. Instead of representing each pin and pad configuration using symbolic 42 * properties such as pullup-enable="true" and so on, the data simply contains 43 * the addresses of the registers that control the pins, and the raw values to 44 * store in those registers. 45 * 46 * The imx5 and imx6 SoCs also have a small number of "general purpose 47 * registers" in the iomuxc device which are used to control an assortment 48 * of completely unrelated aspects of SoC behavior. This driver provides other 49 * drivers with direct access to those registers via simple accessor functions. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/module.h> 57 #include <sys/malloc.h> 58 #include <sys/rman.h> 59 60 #include <machine/bus.h> 61 #include <machine/fdt.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/fdt/fdt_pinctrl.h> 65 #include <dev/ofw/openfirm.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include <arm/freescale/imx/imx_iomuxvar.h> 70 #include <arm/freescale/imx/imx_machdep.h> 71 72 struct iomux_softc { 73 device_t dev; 74 struct resource *mem_res; 75 u_int last_gpreg; 76 }; 77 78 static struct iomux_softc *iomux_sc; 79 80 static struct ofw_compat_data compat_data[] = { 81 {"fsl,imx6dl-iomuxc", true}, 82 {"fsl,imx6q-iomuxc", true}, 83 {"fsl,imx6sl-iomuxc", true}, 84 {"fsl,imx6sx-iomuxc", true}, 85 {"fsl,imx53-iomuxc", true}, 86 {"fsl,imx51-iomuxc", true}, 87 {NULL, false}, 88 }; 89 90 /* 91 * Each tuple in an fsl,pins property contains these fields. 92 */ 93 struct pincfg { 94 uint32_t mux_reg; 95 uint32_t padconf_reg; 96 uint32_t input_reg; 97 uint32_t mux_val; 98 uint32_t input_val; 99 uint32_t padconf_val; 100 }; 101 102 static inline uint32_t 103 RD4(struct iomux_softc *sc, bus_size_t off) 104 { 105 106 return (bus_read_4(sc->mem_res, off)); 107 } 108 109 static inline void 110 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) 111 { 112 113 bus_write_4(sc->mem_res, off, val); 114 } 115 116 static int 117 iomux_configure_pins(device_t dev, phandle_t cfgxref) 118 { 119 struct iomux_softc * sc; 120 struct pincfg *cfgtuples, *cfg; 121 phandle_t cfgnode; 122 int i, ntuples; 123 124 sc = device_get_softc(dev); 125 cfgnode = OF_node_from_xref(cfgxref); 126 ntuples = OF_getencprop_alloc(cfgnode, "fsl,pins", sizeof(*cfgtuples), 127 (void **)&cfgtuples); 128 if (ntuples < 0) 129 return (ENOENT); 130 if (ntuples == 0) 131 return (0); /* Empty property is not an error. */ 132 for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) { 133 WR4(sc, cfg->mux_reg, cfg->mux_val); 134 WR4(sc, cfg->input_reg, cfg->input_val); 135 WR4(sc, cfg->padconf_reg, cfg->padconf_val); 136 } 137 free(cfgtuples, M_OFWPROP); 138 return (0); 139 } 140 141 static int 142 iomux_probe(device_t dev) 143 { 144 145 if (!ofw_bus_status_okay(dev)) 146 return (ENXIO); 147 148 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 149 return (ENXIO); 150 151 device_set_desc(dev, "Freescale i.MX pin configuration"); 152 return (BUS_PROBE_DEFAULT); 153 } 154 155 static int 156 iomux_detach(device_t dev) 157 { 158 159 /* This device is always present. */ 160 return (EBUSY); 161 } 162 163 static int 164 iomux_attach(device_t dev) 165 { 166 struct iomux_softc * sc; 167 int rid; 168 169 sc = device_get_softc(dev); 170 sc->dev = dev; 171 172 switch (imx_soc_type()) { 173 case IMXSOC_51: 174 sc->last_gpreg = 1; 175 break; 176 case IMXSOC_53: 177 sc->last_gpreg = 2; 178 break; 179 case IMXSOC_6DL: 180 case IMXSOC_6S: 181 case IMXSOC_6SL: 182 case IMXSOC_6Q: 183 sc->last_gpreg = 13; 184 break; 185 default: 186 device_printf(dev, "Unknown SoC type\n"); 187 return (ENXIO); 188 } 189 190 rid = 0; 191 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 192 RF_ACTIVE); 193 if (sc->mem_res == NULL) { 194 device_printf(dev, "Cannot allocate memory resources\n"); 195 return (ENXIO); 196 } 197 198 iomux_sc = sc; 199 200 /* 201 * Register as a pinctrl device, and call the convenience function that 202 * walks the entire device tree invoking FDT_PINCTRL_CONFIGURE() on any 203 * pinctrl-0 property cells whose xref phandle refers to a configuration 204 * that is a child node of our node in the tree. 205 * 206 * The pinctrl bindings documentation specifically mentions that the 207 * pinctrl device itself may have a pinctrl-0 property which contains 208 * static configuration to be applied at device init time. The tree 209 * walk will automatically handle this for us when it passes through our 210 * node in the tree. 211 */ 212 fdt_pinctrl_register(dev, "fsl,pins"); 213 fdt_pinctrl_configure_tree(dev); 214 215 return (0); 216 } 217 218 uint32_t 219 imx_iomux_gpr_get(u_int regnum) 220 { 221 struct iomux_softc * sc; 222 223 sc = iomux_sc; 224 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); 225 KASSERT(regnum >= 0 && regnum <= sc->last_gpreg, 226 ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg)); 227 228 return (RD4(iomux_sc, regnum * 4)); 229 } 230 231 void 232 imx_iomux_gpr_set(u_int regnum, uint32_t val) 233 { 234 struct iomux_softc * sc; 235 236 sc = iomux_sc; 237 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); 238 KASSERT(regnum >= 0 && regnum <= sc->last_gpreg, 239 ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg)); 240 241 WR4(iomux_sc, regnum * 4, val); 242 } 243 244 void 245 imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits) 246 { 247 struct iomux_softc * sc; 248 uint32_t val; 249 250 sc = iomux_sc; 251 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); 252 KASSERT(regnum >= 0 && regnum <= sc->last_gpreg, 253 ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg)); 254 255 val = RD4(iomux_sc, regnum * 4); 256 val = (val & ~clrbits) | setbits; 257 WR4(iomux_sc, regnum * 4, val); 258 } 259 260 static device_method_t imx_iomux_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, iomux_probe), 263 DEVMETHOD(device_attach, iomux_attach), 264 DEVMETHOD(device_detach, iomux_detach), 265 266 /* fdt_pinctrl interface */ 267 DEVMETHOD(fdt_pinctrl_configure,iomux_configure_pins), 268 269 DEVMETHOD_END 270 }; 271 272 static driver_t imx_iomux_driver = { 273 "imx_iomux", 274 imx_iomux_methods, 275 sizeof(struct iomux_softc), 276 }; 277 278 static devclass_t imx_iomux_devclass; 279 280 EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver, 281 imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE); 282 283