1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/gpio.h> 52 #include <sys/kernel.h> 53 #include <sys/limits.h> 54 #include <sys/module.h> 55 #include <sys/resource.h> 56 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/rman.h> 60 61 #include <arm/freescale/imx/imx_ccmvar.h> 62 63 #include <dev/iicbus/iiconf.h> 64 #include <dev/iicbus/iicbus.h> 65 #include <dev/iicbus/iic_recover_bus.h> 66 #include "iicbus_if.h" 67 68 #include <dev/ofw/openfirm.h> 69 #include <dev/ofw/ofw_bus.h> 70 #include <dev/ofw/ofw_bus_subr.h> 71 72 #include <dev/fdt/fdt_pinctrl.h> 73 #include <dev/gpio/gpiobusvar.h> 74 75 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 76 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 77 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 78 #define I2C_STATUS_REG 0x0C /* I2C status register */ 79 #define I2C_DATA_REG 0x10 /* I2C data register */ 80 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 81 82 #define I2CCR_MEN (1 << 7) /* Module enable */ 83 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 84 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 85 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 86 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 87 88 #define I2CSR_MCF (1 << 7) /* Data transfer */ 89 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 90 #define I2CSR_MBB (1 << 5) /* Bus busy */ 91 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 92 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 93 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 94 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 95 96 #define I2C_BAUD_RATE_FAST 0x31 97 #define I2C_BAUD_RATE_DEF 0x3F 98 #define I2C_DFSSR_DIV 0x10 99 100 /* 101 * A table of available divisors and the associated coded values to put in the 102 * FDR register to achieve that divisor.. There is no algorithmic relationship I 103 * can see between divisors and the codes that go into the register. The table 104 * begins and ends with entries that handle insane configuration values. 105 */ 106 struct clkdiv { 107 u_int divisor; 108 u_int regcode; 109 }; 110 static struct clkdiv clkdiv_table[] = { 111 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 112 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 113 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 114 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 115 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 116 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 117 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 118 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 119 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 120 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 121 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 122 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 123 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 124 }; 125 126 static struct ofw_compat_data compat_data[] = { 127 {"fsl,imx6q-i2c", 1}, 128 {"fsl,imx-i2c", 1}, 129 {NULL, 0} 130 }; 131 132 struct i2c_softc { 133 device_t dev; 134 device_t iicbus; 135 struct resource *res; 136 int rid; 137 sbintime_t byte_time_sbt; 138 int rb_pinctl_idx; 139 gpio_pin_t rb_sclpin; 140 gpio_pin_t rb_sdapin; 141 }; 142 143 static phandle_t i2c_get_node(device_t, device_t); 144 static int i2c_probe(device_t); 145 static int i2c_attach(device_t); 146 147 static int i2c_repeated_start(device_t, u_char, int); 148 static int i2c_start(device_t, u_char, int); 149 static int i2c_stop(device_t); 150 static int i2c_reset(device_t, u_char, u_char, u_char *); 151 static int i2c_read(device_t, char *, int, int *, int, int); 152 static int i2c_write(device_t, const char *, int, int *, int); 153 154 static device_method_t i2c_methods[] = { 155 DEVMETHOD(device_probe, i2c_probe), 156 DEVMETHOD(device_attach, i2c_attach), 157 158 /* OFW methods */ 159 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 160 161 DEVMETHOD(iicbus_callback, iicbus_null_callback), 162 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 163 DEVMETHOD(iicbus_start, i2c_start), 164 DEVMETHOD(iicbus_stop, i2c_stop), 165 DEVMETHOD(iicbus_reset, i2c_reset), 166 DEVMETHOD(iicbus_read, i2c_read), 167 DEVMETHOD(iicbus_write, i2c_write), 168 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 169 170 DEVMETHOD_END 171 }; 172 173 static driver_t i2c_driver = { 174 "iichb", 175 i2c_methods, 176 sizeof(struct i2c_softc), 177 }; 178 static devclass_t i2c_devclass; 179 180 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 181 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 182 183 static phandle_t 184 i2c_get_node(device_t bus, device_t dev) 185 { 186 /* 187 * Share controller node with iicbus device 188 */ 189 return ofw_bus_get_node(bus); 190 } 191 192 static __inline void 193 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 194 { 195 196 bus_write_1(sc->res, off, val); 197 } 198 199 static __inline uint8_t 200 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 201 { 202 203 return (bus_read_1(sc->res, off)); 204 } 205 206 static __inline void 207 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 208 { 209 uint8_t status; 210 211 status = i2c_read_reg(sc, off); 212 status |= mask; 213 i2c_write_reg(sc, off, status); 214 } 215 216 /* Wait for bus to become busy or not-busy. */ 217 static int 218 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 219 { 220 int retry, srb; 221 222 retry = 1000; 223 while (retry --) { 224 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 225 if ((srb && wantbusy) || (!srb && !wantbusy)) 226 return (IIC_NOERR); 227 DELAY(1); 228 } 229 return (IIC_ETIMEOUT); 230 } 231 232 /* Wait for transfer to complete, optionally check RXAK. */ 233 static int 234 wait_for_xfer(struct i2c_softc *sc, int checkack) 235 { 236 int retry, sr; 237 238 /* 239 * Sleep for about the time it takes to transfer a byte (with precision 240 * set to tolerate 5% oversleep). We calculate the approximate byte 241 * transfer time when we set the bus speed divisor. Slaves are allowed 242 * to do clock-stretching so the actual transfer time can be larger, but 243 * this gets the bulk of the waiting out of the way without tying up the 244 * processor the whole time. 245 */ 246 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 247 248 retry = 10000; 249 while (retry --) { 250 sr = i2c_read_reg(sc, I2C_STATUS_REG); 251 if (sr & I2CSR_MIF) { 252 if (sr & I2CSR_MAL) 253 return (IIC_EBUSERR); 254 else if (checkack && (sr & I2CSR_RXAK)) 255 return (IIC_ENOACK); 256 else 257 return (IIC_NOERR); 258 } 259 DELAY(1); 260 } 261 return (IIC_ETIMEOUT); 262 } 263 264 /* 265 * Implement the error handling shown in the state diagram of the imx6 reference 266 * manual. If there was an error, then: 267 * - Clear master mode (MSTA and MTX). 268 * - Wait for the bus to become free or for a timeout to happen. 269 * - Disable the controller. 270 */ 271 static int 272 i2c_error_handler(struct i2c_softc *sc, int error) 273 { 274 275 if (error != 0) { 276 i2c_write_reg(sc, I2C_STATUS_REG, 0); 277 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 278 wait_for_busbusy(sc, false); 279 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 280 } 281 return (error); 282 } 283 284 static int 285 i2c_recover_getsda(void *ctx) 286 { 287 bool active; 288 289 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 290 return (active); 291 } 292 293 static void 294 i2c_recover_setsda(void *ctx, int value) 295 { 296 297 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 298 } 299 300 static int 301 i2c_recover_getscl(void *ctx) 302 { 303 bool active; 304 305 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 306 return (active); 307 308 } 309 310 static void 311 i2c_recover_setscl(void *ctx, int value) 312 { 313 314 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 315 } 316 317 static int 318 i2c_recover_bus(struct i2c_softc *sc) 319 { 320 struct iicrb_pin_access pins; 321 int err; 322 323 /* 324 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 325 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 326 * recovery sequence if necessary, then configure the pins back to i2c 327 * mode (idx 0). 328 */ 329 if (sc->rb_pinctl_idx == 0) 330 return (0); 331 332 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 333 334 pins.ctx = sc; 335 pins.getsda = i2c_recover_getsda; 336 pins.setsda = i2c_recover_setsda; 337 pins.getscl = i2c_recover_getscl; 338 pins.setscl = i2c_recover_setscl; 339 err = iic_recover_bus(&pins); 340 341 fdt_pinctrl_configure(sc->dev, 0); 342 343 return (err); 344 } 345 346 static int 347 i2c_probe(device_t dev) 348 { 349 350 if (!ofw_bus_status_okay(dev)) 351 return (ENXIO); 352 353 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 354 return (ENXIO); 355 356 device_set_desc(dev, "Freescale i.MX I2C"); 357 358 return (BUS_PROBE_DEFAULT); 359 } 360 361 static int 362 i2c_attach(device_t dev) 363 { 364 char wrkstr[16]; 365 struct i2c_softc *sc; 366 phandle_t node; 367 int err, cfgidx; 368 369 sc = device_get_softc(dev); 370 sc->dev = dev; 371 sc->rid = 0; 372 373 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 374 RF_ACTIVE); 375 if (sc->res == NULL) { 376 device_printf(dev, "could not allocate resources"); 377 return (ENXIO); 378 } 379 380 sc->iicbus = device_add_child(dev, "iicbus", -1); 381 if (sc->iicbus == NULL) { 382 device_printf(dev, "could not add iicbus child"); 383 return (ENXIO); 384 } 385 386 /* 387 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 388 * properties are present. This is optional. If all the config data is 389 * not in place, we just don't do gpio bitbang bus recovery. 390 */ 391 node = ofw_bus_get_node(sc->dev); 392 393 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 394 &sc->rb_sclpin); 395 if (err != 0) 396 goto no_recovery; 397 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 398 &sc->rb_sdapin); 399 if (err != 0) 400 goto no_recovery; 401 402 /* 403 * Preset the gpio pins to output high (idle bus state). The signal 404 * won't actually appear on the pins until the bus recovery code changes 405 * the pinmux config from i2c to gpio. 406 */ 407 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 408 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 409 gpio_pin_set_active(sc->rb_sclpin, true); 410 gpio_pin_set_active(sc->rb_sdapin, true); 411 412 /* 413 * Obtain the index of pinctrl node for bus recovery using gpio pins, 414 * then confirm that pinctrl properties exist for that index and for the 415 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 416 * will also do a bus recovery, so setting this value must be last. 417 */ 418 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 419 if (err == 0) { 420 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 421 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 422 sc->rb_pinctl_idx = cfgidx; 423 } 424 425 no_recovery: 426 427 /* We don't do a hardware reset here because iicbus_attach() does it. */ 428 429 bus_generic_attach(dev); 430 return (0); 431 } 432 433 static int 434 i2c_repeated_start(device_t dev, u_char slave, int timeout) 435 { 436 struct i2c_softc *sc; 437 int error; 438 439 sc = device_get_softc(dev); 440 441 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 442 return (IIC_EBUSERR); 443 } 444 445 /* 446 * Set repeated start condition, delay (per reference manual, min 156nS) 447 * before writing slave address, wait for ack after write. 448 */ 449 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 450 DELAY(1); 451 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 452 i2c_write_reg(sc, I2C_DATA_REG, slave); 453 error = wait_for_xfer(sc, true); 454 return (i2c_error_handler(sc, error)); 455 } 456 457 static int 458 i2c_start_ll(device_t dev, u_char slave, int timeout) 459 { 460 struct i2c_softc *sc; 461 int error; 462 463 sc = device_get_softc(dev); 464 465 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 466 DELAY(10); /* Delay for controller to sample bus state. */ 467 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 468 return (i2c_error_handler(sc, IIC_EBUSERR)); 469 } 470 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 471 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 472 return (i2c_error_handler(sc, error)); 473 i2c_write_reg(sc, I2C_STATUS_REG, 0); 474 i2c_write_reg(sc, I2C_DATA_REG, slave); 475 error = wait_for_xfer(sc, true); 476 return (i2c_error_handler(sc, error)); 477 } 478 479 static int 480 i2c_start(device_t dev, u_char slave, int timeout) 481 { 482 struct i2c_softc *sc; 483 int error; 484 485 sc = device_get_softc(dev); 486 487 /* 488 * Invoke the low-level code to put the bus into master mode and address 489 * the given slave. If that fails, idle the controller and attempt a 490 * bus recovery, and then try again one time. Signaling a start and 491 * addressing the slave is the only operation that a low-level driver 492 * can safely retry without any help from the upper layers that know 493 * more about the slave device. 494 */ 495 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 496 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 497 if ((error = i2c_recover_bus(sc)) != 0) 498 return (error); 499 error = i2c_start_ll(dev, slave, timeout); 500 } 501 return (error); 502 } 503 504 static int 505 i2c_stop(device_t dev) 506 { 507 struct i2c_softc *sc; 508 509 sc = device_get_softc(dev); 510 511 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 512 wait_for_busbusy(sc, false); 513 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 514 return (IIC_NOERR); 515 } 516 517 static int 518 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 519 { 520 struct i2c_softc *sc; 521 u_int busfreq, div, i, ipgfreq; 522 523 sc = device_get_softc(dev); 524 525 /* 526 * Look up the divisor that gives the nearest speed that doesn't exceed 527 * the configured value for the bus. 528 */ 529 ipgfreq = imx_ccm_ipg_hz(); 530 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 531 div = howmany(ipgfreq, busfreq); 532 for (i = 0; i < nitems(clkdiv_table); i++) { 533 if (clkdiv_table[i].divisor >= div) 534 break; 535 } 536 537 /* 538 * Calculate roughly how long it will take to transfer a byte (which 539 * requires 9 clock cycles) at the new bus speed. This value is used to 540 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 541 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 542 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 543 */ 544 busfreq = ipgfreq / clkdiv_table[i].divisor; 545 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 546 547 /* 548 * Disable the controller (do the reset), and set the new clock divisor. 549 */ 550 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 551 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 552 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 553 554 /* 555 * Now that the controller is idle, perform bus recovery. If the bus 556 * isn't hung, this a fairly fast no-op. 557 */ 558 return (i2c_recover_bus(sc)); 559 } 560 561 static int 562 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 563 { 564 struct i2c_softc *sc; 565 int error, reg; 566 567 sc = device_get_softc(dev); 568 *read = 0; 569 570 if (len) { 571 if (len == 1) 572 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 573 I2CCR_MSTA | I2CCR_TXAK); 574 else 575 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 576 I2CCR_MSTA); 577 /* Dummy read to prime the receiver. */ 578 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 579 i2c_read_reg(sc, I2C_DATA_REG); 580 } 581 582 error = 0; 583 *read = 0; 584 while (*read < len) { 585 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 586 break; 587 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 588 if (last) { 589 if (*read == len - 2) { 590 /* NO ACK on last byte */ 591 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 592 I2CCR_MSTA | I2CCR_TXAK); 593 } else if (*read == len - 1) { 594 /* Transfer done, signal stop. */ 595 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 596 I2CCR_TXAK); 597 wait_for_busbusy(sc, false); 598 } 599 } 600 reg = i2c_read_reg(sc, I2C_DATA_REG); 601 *buf++ = reg; 602 (*read)++; 603 } 604 605 return (i2c_error_handler(sc, error)); 606 } 607 608 static int 609 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 610 { 611 struct i2c_softc *sc; 612 int error; 613 614 sc = device_get_softc(dev); 615 616 error = 0; 617 *sent = 0; 618 while (*sent < len) { 619 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 620 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 621 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 622 break; 623 (*sent)++; 624 } 625 626 return (i2c_error_handler(sc, error)); 627 } 628