1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/gpio.h> 52 #include <sys/kernel.h> 53 #include <sys/limits.h> 54 #include <sys/module.h> 55 #include <sys/resource.h> 56 #include <sys/sysctl.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/rman.h> 61 62 #include <arm/freescale/imx/imx_ccmvar.h> 63 64 #include <dev/iicbus/iiconf.h> 65 #include <dev/iicbus/iicbus.h> 66 #include <dev/iicbus/iic_recover_bus.h> 67 #include "iicbus_if.h" 68 69 #include <dev/ofw/openfirm.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include <dev/fdt/fdt_pinctrl.h> 74 #include <dev/gpio/gpiobusvar.h> 75 76 #if defined(EXT_RESOURCES) && defined(__aarch64__) 77 #define IMX_ENABLE_CLOCKS 78 #endif 79 80 #ifdef IMX_ENABLE_CLOCKS 81 #include <dev/extres/clk/clk.h> 82 #endif 83 84 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 85 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 86 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 87 #define I2C_STATUS_REG 0x0C /* I2C status register */ 88 #define I2C_DATA_REG 0x10 /* I2C data register */ 89 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 90 91 #define I2CCR_MEN (1 << 7) /* Module enable */ 92 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 93 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 94 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 95 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 96 97 #define I2CSR_MCF (1 << 7) /* Data transfer */ 98 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 99 #define I2CSR_MBB (1 << 5) /* Bus busy */ 100 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 101 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 102 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 103 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 104 105 #define I2C_BAUD_RATE_FAST 0x31 106 #define I2C_BAUD_RATE_DEF 0x3F 107 #define I2C_DFSSR_DIV 0x10 108 109 /* 110 * A table of available divisors and the associated coded values to put in the 111 * FDR register to achieve that divisor.. There is no algorithmic relationship I 112 * can see between divisors and the codes that go into the register. The table 113 * begins and ends with entries that handle insane configuration values. 114 */ 115 struct clkdiv { 116 u_int divisor; 117 u_int regcode; 118 }; 119 static struct clkdiv clkdiv_table[] = { 120 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 121 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 122 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 123 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 124 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 125 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 126 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 127 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 128 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 129 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 130 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 131 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 132 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 133 }; 134 135 static struct ofw_compat_data compat_data[] = { 136 {"fsl,imx21-i2c", 1}, 137 {"fsl,imx6q-i2c", 1}, 138 {"fsl,imx-i2c", 1}, 139 {NULL, 0} 140 }; 141 142 struct i2c_softc { 143 device_t dev; 144 device_t iicbus; 145 struct resource *res; 146 int rid; 147 sbintime_t byte_time_sbt; 148 int rb_pinctl_idx; 149 gpio_pin_t rb_sclpin; 150 gpio_pin_t rb_sdapin; 151 u_int debug; 152 u_int slave; 153 #ifdef IMX_ENABLE_CLOCKS 154 clk_t ipgclk; 155 #endif 156 }; 157 158 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 159 if ((lvl) <= (sc)->debug) \ 160 device_printf((sc)->dev, fmt, ##args) 161 162 #define DEBUGF(sc, lvl, fmt, args...) \ 163 if ((lvl) <= (sc)->debug) \ 164 printf(fmt, ##args) 165 166 static phandle_t i2c_get_node(device_t, device_t); 167 static int i2c_probe(device_t); 168 static int i2c_attach(device_t); 169 static int i2c_detach(device_t); 170 171 static int i2c_repeated_start(device_t, u_char, int); 172 static int i2c_start(device_t, u_char, int); 173 static int i2c_stop(device_t); 174 static int i2c_reset(device_t, u_char, u_char, u_char *); 175 static int i2c_read(device_t, char *, int, int *, int, int); 176 static int i2c_write(device_t, const char *, int, int *, int); 177 178 static device_method_t i2c_methods[] = { 179 DEVMETHOD(device_probe, i2c_probe), 180 DEVMETHOD(device_attach, i2c_attach), 181 DEVMETHOD(device_detach, i2c_detach), 182 183 /* OFW methods */ 184 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 185 186 DEVMETHOD(iicbus_callback, iicbus_null_callback), 187 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 188 DEVMETHOD(iicbus_start, i2c_start), 189 DEVMETHOD(iicbus_stop, i2c_stop), 190 DEVMETHOD(iicbus_reset, i2c_reset), 191 DEVMETHOD(iicbus_read, i2c_read), 192 DEVMETHOD(iicbus_write, i2c_write), 193 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 194 195 DEVMETHOD_END 196 }; 197 198 static driver_t i2c_driver = { 199 "imx_i2c", 200 i2c_methods, 201 sizeof(struct i2c_softc), 202 }; 203 static devclass_t i2c_devclass; 204 205 DRIVER_MODULE(imx_i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 206 DRIVER_MODULE(ofw_iicbus, imx_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 0, 0); 207 MODULE_DEPEND(imx_i2c, iicbus, 1, 1, 1); 208 SIMPLEBUS_PNP_INFO(compat_data); 209 210 static phandle_t 211 i2c_get_node(device_t bus, device_t dev) 212 { 213 /* 214 * Share controller node with iicbus device 215 */ 216 return ofw_bus_get_node(bus); 217 } 218 219 static __inline void 220 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 221 { 222 223 bus_write_1(sc->res, off, val); 224 } 225 226 static __inline uint8_t 227 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 228 { 229 230 return (bus_read_1(sc->res, off)); 231 } 232 233 static __inline void 234 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 235 { 236 uint8_t status; 237 238 status = i2c_read_reg(sc, off); 239 status |= mask; 240 i2c_write_reg(sc, off, status); 241 } 242 243 /* Wait for bus to become busy or not-busy. */ 244 static int 245 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 246 { 247 int retry, srb; 248 249 retry = 1000; 250 while (retry --) { 251 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 252 if ((srb && wantbusy) || (!srb && !wantbusy)) 253 return (IIC_NOERR); 254 DELAY(1); 255 } 256 return (IIC_ETIMEOUT); 257 } 258 259 /* Wait for transfer to complete, optionally check RXAK. */ 260 static int 261 wait_for_xfer(struct i2c_softc *sc, int checkack) 262 { 263 int retry, sr; 264 265 /* 266 * Sleep for about the time it takes to transfer a byte (with precision 267 * set to tolerate 5% oversleep). We calculate the approximate byte 268 * transfer time when we set the bus speed divisor. Slaves are allowed 269 * to do clock-stretching so the actual transfer time can be larger, but 270 * this gets the bulk of the waiting out of the way without tying up the 271 * processor the whole time. 272 */ 273 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 274 275 retry = 10000; 276 while (retry --) { 277 sr = i2c_read_reg(sc, I2C_STATUS_REG); 278 if (sr & I2CSR_MIF) { 279 if (sr & I2CSR_MAL) 280 return (IIC_EBUSERR); 281 else if (checkack && (sr & I2CSR_RXAK)) 282 return (IIC_ENOACK); 283 else 284 return (IIC_NOERR); 285 } 286 DELAY(1); 287 } 288 return (IIC_ETIMEOUT); 289 } 290 291 /* 292 * Implement the error handling shown in the state diagram of the imx6 reference 293 * manual. If there was an error, then: 294 * - Clear master mode (MSTA and MTX). 295 * - Wait for the bus to become free or for a timeout to happen. 296 * - Disable the controller. 297 */ 298 static int 299 i2c_error_handler(struct i2c_softc *sc, int error) 300 { 301 302 if (error != 0) { 303 i2c_write_reg(sc, I2C_STATUS_REG, 0); 304 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 305 wait_for_busbusy(sc, false); 306 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 307 } 308 return (error); 309 } 310 311 static int 312 i2c_recover_getsda(void *ctx) 313 { 314 bool active; 315 316 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 317 return (active); 318 } 319 320 static void 321 i2c_recover_setsda(void *ctx, int value) 322 { 323 324 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 325 } 326 327 static int 328 i2c_recover_getscl(void *ctx) 329 { 330 bool active; 331 332 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 333 return (active); 334 335 } 336 337 static void 338 i2c_recover_setscl(void *ctx, int value) 339 { 340 341 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 342 } 343 344 static int 345 i2c_recover_bus(struct i2c_softc *sc) 346 { 347 struct iicrb_pin_access pins; 348 int err; 349 350 /* 351 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 352 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 353 * recovery sequence if necessary, then configure the pins back to i2c 354 * mode (idx 0). 355 */ 356 if (sc->rb_pinctl_idx == 0) 357 return (0); 358 359 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 360 361 pins.ctx = sc; 362 pins.getsda = i2c_recover_getsda; 363 pins.setsda = i2c_recover_setsda; 364 pins.getscl = i2c_recover_getscl; 365 pins.setscl = i2c_recover_setscl; 366 err = iic_recover_bus(&pins); 367 368 fdt_pinctrl_configure(sc->dev, 0); 369 370 return (err); 371 } 372 373 static int 374 i2c_probe(device_t dev) 375 { 376 377 if (!ofw_bus_status_okay(dev)) 378 return (ENXIO); 379 380 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 381 return (ENXIO); 382 383 device_set_desc(dev, "Freescale i.MX I2C"); 384 385 return (BUS_PROBE_DEFAULT); 386 } 387 388 static int 389 i2c_attach(device_t dev) 390 { 391 char wrkstr[16]; 392 struct i2c_softc *sc; 393 phandle_t node; 394 int err, cfgidx; 395 396 sc = device_get_softc(dev); 397 sc->dev = dev; 398 sc->rid = 0; 399 400 #ifdef IMX_ENABLE_CLOCKS 401 if (clk_get_by_ofw_index(sc->dev, 0, 0, &sc->ipgclk) != 0) { 402 device_printf(dev, "could not get ipg clock"); 403 return (ENOENT); 404 } 405 406 err = clk_enable(sc->ipgclk); 407 if (err != 0) { 408 device_printf(sc->dev, "could not enable ipg clock\n"); 409 return (err); 410 } 411 #endif 412 413 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 414 RF_ACTIVE); 415 if (sc->res == NULL) { 416 device_printf(dev, "could not allocate resources"); 417 return (ENXIO); 418 } 419 420 sc->iicbus = device_add_child(dev, "iicbus", -1); 421 if (sc->iicbus == NULL) { 422 device_printf(dev, "could not add iicbus child"); 423 return (ENXIO); 424 } 425 426 /* Set up debug-enable sysctl. */ 427 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 428 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 429 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 430 "Enable debug; 1=reads/writes, 2=add starts/stops"); 431 432 /* 433 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 434 * properties are present. This is optional. If all the config data is 435 * not in place, we just don't do gpio bitbang bus recovery. 436 */ 437 node = ofw_bus_get_node(sc->dev); 438 439 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 440 &sc->rb_sclpin); 441 if (err != 0) 442 goto no_recovery; 443 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 444 &sc->rb_sdapin); 445 if (err != 0) 446 goto no_recovery; 447 448 /* 449 * Preset the gpio pins to output high (idle bus state). The signal 450 * won't actually appear on the pins until the bus recovery code changes 451 * the pinmux config from i2c to gpio. 452 */ 453 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 454 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 455 gpio_pin_set_active(sc->rb_sclpin, true); 456 gpio_pin_set_active(sc->rb_sdapin, true); 457 458 /* 459 * Obtain the index of pinctrl node for bus recovery using gpio pins, 460 * then confirm that pinctrl properties exist for that index and for the 461 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 462 * will also do a bus recovery, so setting this value must be last. 463 */ 464 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 465 if (err == 0) { 466 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 467 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 468 sc->rb_pinctl_idx = cfgidx; 469 } 470 471 no_recovery: 472 473 /* We don't do a hardware reset here because iicbus_attach() does it. */ 474 475 /* Probe and attach the iicbus when interrupts are available. */ 476 return (bus_delayed_attach_children(dev)); 477 } 478 479 static int 480 i2c_detach(device_t dev) 481 { 482 struct i2c_softc *sc; 483 int error; 484 485 sc = device_get_softc(dev); 486 487 #ifdef IMX_ENABLE_CLOCKS 488 error = clk_disable(sc->ipgclk); 489 if (error != 0) { 490 device_printf(sc->dev, "could not disable ipg clock\n"); 491 return (error); 492 } 493 #endif 494 495 if ((error = bus_generic_detach(sc->dev)) != 0) { 496 device_printf(sc->dev, "cannot detach child devices\n"); 497 return (error); 498 } 499 500 if (sc->iicbus != NULL) 501 device_delete_child(dev, sc->iicbus); 502 503 /* Release bus-recover pins; gpio_pin_release() handles NULL args. */ 504 gpio_pin_release(sc->rb_sclpin); 505 gpio_pin_release(sc->rb_sdapin); 506 507 if (sc->res != NULL) 508 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 509 510 return (0); 511 } 512 513 static int 514 i2c_repeated_start(device_t dev, u_char slave, int timeout) 515 { 516 struct i2c_softc *sc; 517 int error; 518 519 sc = device_get_softc(dev); 520 521 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 522 return (IIC_EBUSERR); 523 } 524 525 /* 526 * Set repeated start condition, delay (per reference manual, min 156nS) 527 * before writing slave address, wait for ack after write. 528 */ 529 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 530 DELAY(1); 531 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 532 i2c_write_reg(sc, I2C_DATA_REG, slave); 533 sc->slave = slave; 534 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); 535 error = wait_for_xfer(sc, true); 536 return (i2c_error_handler(sc, error)); 537 } 538 539 static int 540 i2c_start_ll(device_t dev, u_char slave, int timeout) 541 { 542 struct i2c_softc *sc; 543 int error; 544 545 sc = device_get_softc(dev); 546 547 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 548 DELAY(10); /* Delay for controller to sample bus state. */ 549 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 550 return (i2c_error_handler(sc, IIC_EBUSERR)); 551 } 552 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 553 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 554 return (i2c_error_handler(sc, error)); 555 i2c_write_reg(sc, I2C_STATUS_REG, 0); 556 i2c_write_reg(sc, I2C_DATA_REG, slave); 557 sc->slave = slave; 558 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); 559 error = wait_for_xfer(sc, true); 560 return (i2c_error_handler(sc, error)); 561 } 562 563 static int 564 i2c_start(device_t dev, u_char slave, int timeout) 565 { 566 struct i2c_softc *sc; 567 int error; 568 569 sc = device_get_softc(dev); 570 571 /* 572 * Invoke the low-level code to put the bus into master mode and address 573 * the given slave. If that fails, idle the controller and attempt a 574 * bus recovery, and then try again one time. Signaling a start and 575 * addressing the slave is the only operation that a low-level driver 576 * can safely retry without any help from the upper layers that know 577 * more about the slave device. 578 */ 579 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 580 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 581 if ((error = i2c_recover_bus(sc)) != 0) 582 return (error); 583 error = i2c_start_ll(dev, slave, timeout); 584 } 585 return (error); 586 } 587 588 static int 589 i2c_stop(device_t dev) 590 { 591 struct i2c_softc *sc; 592 593 sc = device_get_softc(dev); 594 595 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 596 wait_for_busbusy(sc, false); 597 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 598 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); 599 return (IIC_NOERR); 600 } 601 602 static int 603 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 604 { 605 struct i2c_softc *sc; 606 u_int busfreq, div, i, ipgfreq; 607 #ifdef IMX_ENABLE_CLOCKS 608 int err; 609 uint64_t freq; 610 #endif 611 612 sc = device_get_softc(dev); 613 614 DEVICE_DEBUGF(sc, 1, "reset\n"); 615 616 /* 617 * Look up the divisor that gives the nearest speed that doesn't exceed 618 * the configured value for the bus. 619 */ 620 #ifdef IMX_ENABLE_CLOCKS 621 err = clk_get_freq(sc->ipgclk, &freq); 622 if (err != 0) { 623 device_printf(sc->dev, "cannot get frequency\n"); 624 return (err); 625 } 626 ipgfreq = (int32_t)freq; 627 #else 628 ipgfreq = imx_ccm_ipg_hz(); 629 #endif 630 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 631 div = howmany(ipgfreq, busfreq); 632 for (i = 0; i < nitems(clkdiv_table); i++) { 633 if (clkdiv_table[i].divisor >= div) 634 break; 635 } 636 637 /* 638 * Calculate roughly how long it will take to transfer a byte (which 639 * requires 9 clock cycles) at the new bus speed. This value is used to 640 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 641 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 642 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 643 */ 644 busfreq = ipgfreq / clkdiv_table[i].divisor; 645 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 646 647 /* 648 * Disable the controller (do the reset), and set the new clock divisor. 649 */ 650 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 651 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 652 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 653 654 /* 655 * Now that the controller is idle, perform bus recovery. If the bus 656 * isn't hung, this a fairly fast no-op. 657 */ 658 return (i2c_recover_bus(sc)); 659 } 660 661 static int 662 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 663 { 664 struct i2c_softc *sc; 665 int error, reg; 666 667 sc = device_get_softc(dev); 668 *read = 0; 669 670 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); 671 if (len) { 672 if (len == 1) 673 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 674 I2CCR_MSTA | I2CCR_TXAK); 675 else 676 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 677 I2CCR_MSTA); 678 /* Dummy read to prime the receiver. */ 679 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 680 i2c_read_reg(sc, I2C_DATA_REG); 681 } 682 683 error = 0; 684 *read = 0; 685 while (*read < len) { 686 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 687 break; 688 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 689 if (last) { 690 if (*read == len - 2) { 691 /* NO ACK on last byte */ 692 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 693 I2CCR_MSTA | I2CCR_TXAK); 694 } else if (*read == len - 1) { 695 /* Transfer done, signal stop. */ 696 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 697 I2CCR_TXAK); 698 wait_for_busbusy(sc, false); 699 } 700 } 701 reg = i2c_read_reg(sc, I2C_DATA_REG); 702 DEBUGF(sc, 1, "0x%02x ", reg); 703 *buf++ = reg; 704 (*read)++; 705 } 706 DEBUGF(sc, 1, "\n"); 707 708 return (i2c_error_handler(sc, error)); 709 } 710 711 static int 712 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 713 { 714 struct i2c_softc *sc; 715 int error; 716 717 sc = device_get_softc(dev); 718 719 error = 0; 720 *sent = 0; 721 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); 722 while (*sent < len) { 723 DEBUGF(sc, 1, "0x%02x ", *buf); 724 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 725 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 726 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 727 break; 728 (*sent)++; 729 } 730 DEBUGF(sc, 1, "\n"); 731 return (i2c_error_handler(sc, error)); 732 } 733