1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/gpio.h> 52 #include <sys/kernel.h> 53 #include <sys/limits.h> 54 #include <sys/module.h> 55 #include <sys/resource.h> 56 #include <sys/sysctl.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/rman.h> 61 62 #include <arm/freescale/imx/imx_ccmvar.h> 63 64 #include <dev/iicbus/iiconf.h> 65 #include <dev/iicbus/iicbus.h> 66 #include <dev/iicbus/iic_recover_bus.h> 67 #include "iicbus_if.h" 68 69 #include <dev/ofw/openfirm.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include <dev/fdt/fdt_pinctrl.h> 74 #include <dev/gpio/gpiobusvar.h> 75 76 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 77 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 78 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 79 #define I2C_STATUS_REG 0x0C /* I2C status register */ 80 #define I2C_DATA_REG 0x10 /* I2C data register */ 81 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 82 83 #define I2CCR_MEN (1 << 7) /* Module enable */ 84 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 85 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 86 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 87 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 88 89 #define I2CSR_MCF (1 << 7) /* Data transfer */ 90 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 91 #define I2CSR_MBB (1 << 5) /* Bus busy */ 92 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 93 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 94 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 95 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 96 97 #define I2C_BAUD_RATE_FAST 0x31 98 #define I2C_BAUD_RATE_DEF 0x3F 99 #define I2C_DFSSR_DIV 0x10 100 101 /* 102 * A table of available divisors and the associated coded values to put in the 103 * FDR register to achieve that divisor.. There is no algorithmic relationship I 104 * can see between divisors and the codes that go into the register. The table 105 * begins and ends with entries that handle insane configuration values. 106 */ 107 struct clkdiv { 108 u_int divisor; 109 u_int regcode; 110 }; 111 static struct clkdiv clkdiv_table[] = { 112 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 113 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 114 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 115 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 116 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 117 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 118 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 119 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 120 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 121 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 122 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 123 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 124 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 125 }; 126 127 static struct ofw_compat_data compat_data[] = { 128 {"fsl,imx6q-i2c", 1}, 129 {"fsl,imx-i2c", 1}, 130 {NULL, 0} 131 }; 132 133 struct i2c_softc { 134 device_t dev; 135 device_t iicbus; 136 struct resource *res; 137 int rid; 138 sbintime_t byte_time_sbt; 139 int rb_pinctl_idx; 140 gpio_pin_t rb_sclpin; 141 gpio_pin_t rb_sdapin; 142 u_int debug; 143 u_int slave; 144 }; 145 146 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 147 if ((lvl) <= (sc)->debug) \ 148 device_printf((sc)->dev, fmt, ##args) 149 150 #define DEBUGF(sc, lvl, fmt, args...) \ 151 if ((lvl) <= (sc)->debug) \ 152 printf(fmt, ##args) 153 154 static phandle_t i2c_get_node(device_t, device_t); 155 static int i2c_probe(device_t); 156 static int i2c_attach(device_t); 157 static int i2c_detach(device_t); 158 159 static int i2c_repeated_start(device_t, u_char, int); 160 static int i2c_start(device_t, u_char, int); 161 static int i2c_stop(device_t); 162 static int i2c_reset(device_t, u_char, u_char, u_char *); 163 static int i2c_read(device_t, char *, int, int *, int, int); 164 static int i2c_write(device_t, const char *, int, int *, int); 165 166 static device_method_t i2c_methods[] = { 167 DEVMETHOD(device_probe, i2c_probe), 168 DEVMETHOD(device_attach, i2c_attach), 169 DEVMETHOD(device_detach, i2c_detach), 170 171 /* OFW methods */ 172 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 173 174 DEVMETHOD(iicbus_callback, iicbus_null_callback), 175 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 176 DEVMETHOD(iicbus_start, i2c_start), 177 DEVMETHOD(iicbus_stop, i2c_stop), 178 DEVMETHOD(iicbus_reset, i2c_reset), 179 DEVMETHOD(iicbus_read, i2c_read), 180 DEVMETHOD(iicbus_write, i2c_write), 181 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 182 183 DEVMETHOD_END 184 }; 185 186 static driver_t i2c_driver = { 187 "iichb", 188 i2c_methods, 189 sizeof(struct i2c_softc), 190 }; 191 static devclass_t i2c_devclass; 192 193 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 194 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 195 196 static phandle_t 197 i2c_get_node(device_t bus, device_t dev) 198 { 199 /* 200 * Share controller node with iicbus device 201 */ 202 return ofw_bus_get_node(bus); 203 } 204 205 static __inline void 206 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 207 { 208 209 bus_write_1(sc->res, off, val); 210 } 211 212 static __inline uint8_t 213 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 214 { 215 216 return (bus_read_1(sc->res, off)); 217 } 218 219 static __inline void 220 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 221 { 222 uint8_t status; 223 224 status = i2c_read_reg(sc, off); 225 status |= mask; 226 i2c_write_reg(sc, off, status); 227 } 228 229 /* Wait for bus to become busy or not-busy. */ 230 static int 231 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 232 { 233 int retry, srb; 234 235 retry = 1000; 236 while (retry --) { 237 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 238 if ((srb && wantbusy) || (!srb && !wantbusy)) 239 return (IIC_NOERR); 240 DELAY(1); 241 } 242 return (IIC_ETIMEOUT); 243 } 244 245 /* Wait for transfer to complete, optionally check RXAK. */ 246 static int 247 wait_for_xfer(struct i2c_softc *sc, int checkack) 248 { 249 int retry, sr; 250 251 /* 252 * Sleep for about the time it takes to transfer a byte (with precision 253 * set to tolerate 5% oversleep). We calculate the approximate byte 254 * transfer time when we set the bus speed divisor. Slaves are allowed 255 * to do clock-stretching so the actual transfer time can be larger, but 256 * this gets the bulk of the waiting out of the way without tying up the 257 * processor the whole time. 258 */ 259 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 260 261 retry = 10000; 262 while (retry --) { 263 sr = i2c_read_reg(sc, I2C_STATUS_REG); 264 if (sr & I2CSR_MIF) { 265 if (sr & I2CSR_MAL) 266 return (IIC_EBUSERR); 267 else if (checkack && (sr & I2CSR_RXAK)) 268 return (IIC_ENOACK); 269 else 270 return (IIC_NOERR); 271 } 272 DELAY(1); 273 } 274 return (IIC_ETIMEOUT); 275 } 276 277 /* 278 * Implement the error handling shown in the state diagram of the imx6 reference 279 * manual. If there was an error, then: 280 * - Clear master mode (MSTA and MTX). 281 * - Wait for the bus to become free or for a timeout to happen. 282 * - Disable the controller. 283 */ 284 static int 285 i2c_error_handler(struct i2c_softc *sc, int error) 286 { 287 288 if (error != 0) { 289 i2c_write_reg(sc, I2C_STATUS_REG, 0); 290 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 291 wait_for_busbusy(sc, false); 292 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 293 } 294 return (error); 295 } 296 297 static int 298 i2c_recover_getsda(void *ctx) 299 { 300 bool active; 301 302 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 303 return (active); 304 } 305 306 static void 307 i2c_recover_setsda(void *ctx, int value) 308 { 309 310 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 311 } 312 313 static int 314 i2c_recover_getscl(void *ctx) 315 { 316 bool active; 317 318 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 319 return (active); 320 321 } 322 323 static void 324 i2c_recover_setscl(void *ctx, int value) 325 { 326 327 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 328 } 329 330 static int 331 i2c_recover_bus(struct i2c_softc *sc) 332 { 333 struct iicrb_pin_access pins; 334 int err; 335 336 /* 337 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 338 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 339 * recovery sequence if necessary, then configure the pins back to i2c 340 * mode (idx 0). 341 */ 342 if (sc->rb_pinctl_idx == 0) 343 return (0); 344 345 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 346 347 pins.ctx = sc; 348 pins.getsda = i2c_recover_getsda; 349 pins.setsda = i2c_recover_setsda; 350 pins.getscl = i2c_recover_getscl; 351 pins.setscl = i2c_recover_setscl; 352 err = iic_recover_bus(&pins); 353 354 fdt_pinctrl_configure(sc->dev, 0); 355 356 return (err); 357 } 358 359 static int 360 i2c_probe(device_t dev) 361 { 362 363 if (!ofw_bus_status_okay(dev)) 364 return (ENXIO); 365 366 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 367 return (ENXIO); 368 369 device_set_desc(dev, "Freescale i.MX I2C"); 370 371 return (BUS_PROBE_DEFAULT); 372 } 373 374 static int 375 i2c_attach(device_t dev) 376 { 377 char wrkstr[16]; 378 struct i2c_softc *sc; 379 phandle_t node; 380 int err, cfgidx; 381 382 sc = device_get_softc(dev); 383 sc->dev = dev; 384 sc->rid = 0; 385 386 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 387 RF_ACTIVE); 388 if (sc->res == NULL) { 389 device_printf(dev, "could not allocate resources"); 390 return (ENXIO); 391 } 392 393 sc->iicbus = device_add_child(dev, "iicbus", -1); 394 if (sc->iicbus == NULL) { 395 device_printf(dev, "could not add iicbus child"); 396 return (ENXIO); 397 } 398 399 /* Set up debug-enable sysctl. */ 400 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 401 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 402 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 403 "Enable debug; 1=reads/writes, 2=add starts/stops"); 404 405 /* 406 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 407 * properties are present. This is optional. If all the config data is 408 * not in place, we just don't do gpio bitbang bus recovery. 409 */ 410 node = ofw_bus_get_node(sc->dev); 411 412 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 413 &sc->rb_sclpin); 414 if (err != 0) 415 goto no_recovery; 416 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 417 &sc->rb_sdapin); 418 if (err != 0) 419 goto no_recovery; 420 421 /* 422 * Preset the gpio pins to output high (idle bus state). The signal 423 * won't actually appear on the pins until the bus recovery code changes 424 * the pinmux config from i2c to gpio. 425 */ 426 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 427 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 428 gpio_pin_set_active(sc->rb_sclpin, true); 429 gpio_pin_set_active(sc->rb_sdapin, true); 430 431 /* 432 * Obtain the index of pinctrl node for bus recovery using gpio pins, 433 * then confirm that pinctrl properties exist for that index and for the 434 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 435 * will also do a bus recovery, so setting this value must be last. 436 */ 437 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 438 if (err == 0) { 439 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 440 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 441 sc->rb_pinctl_idx = cfgidx; 442 } 443 444 no_recovery: 445 446 /* We don't do a hardware reset here because iicbus_attach() does it. */ 447 448 /* Probe and attach the iicbus when interrupts are available. */ 449 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 450 return (0); 451 } 452 453 static int 454 i2c_detach(device_t dev) 455 { 456 struct i2c_softc *sc; 457 int error; 458 459 sc = device_get_softc(dev); 460 461 if ((error = bus_generic_detach(sc->dev)) != 0) { 462 device_printf(sc->dev, "cannot detach child devices\n"); 463 return (error); 464 } 465 466 if (sc->iicbus != NULL) 467 device_delete_child(dev, sc->iicbus); 468 469 if (sc->res != NULL) 470 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 471 472 return (0); 473 } 474 475 static int 476 i2c_repeated_start(device_t dev, u_char slave, int timeout) 477 { 478 struct i2c_softc *sc; 479 int error; 480 481 sc = device_get_softc(dev); 482 483 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 484 return (IIC_EBUSERR); 485 } 486 487 /* 488 * Set repeated start condition, delay (per reference manual, min 156nS) 489 * before writing slave address, wait for ack after write. 490 */ 491 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 492 DELAY(1); 493 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 494 i2c_write_reg(sc, I2C_DATA_REG, slave); 495 sc->slave = slave; 496 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); 497 error = wait_for_xfer(sc, true); 498 return (i2c_error_handler(sc, error)); 499 } 500 501 static int 502 i2c_start_ll(device_t dev, u_char slave, int timeout) 503 { 504 struct i2c_softc *sc; 505 int error; 506 507 sc = device_get_softc(dev); 508 509 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 510 DELAY(10); /* Delay for controller to sample bus state. */ 511 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 512 return (i2c_error_handler(sc, IIC_EBUSERR)); 513 } 514 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 515 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 516 return (i2c_error_handler(sc, error)); 517 i2c_write_reg(sc, I2C_STATUS_REG, 0); 518 i2c_write_reg(sc, I2C_DATA_REG, slave); 519 sc->slave = slave; 520 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); 521 error = wait_for_xfer(sc, true); 522 return (i2c_error_handler(sc, error)); 523 } 524 525 static int 526 i2c_start(device_t dev, u_char slave, int timeout) 527 { 528 struct i2c_softc *sc; 529 int error; 530 531 sc = device_get_softc(dev); 532 533 /* 534 * Invoke the low-level code to put the bus into master mode and address 535 * the given slave. If that fails, idle the controller and attempt a 536 * bus recovery, and then try again one time. Signaling a start and 537 * addressing the slave is the only operation that a low-level driver 538 * can safely retry without any help from the upper layers that know 539 * more about the slave device. 540 */ 541 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 542 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 543 if ((error = i2c_recover_bus(sc)) != 0) 544 return (error); 545 error = i2c_start_ll(dev, slave, timeout); 546 } 547 return (error); 548 } 549 550 static int 551 i2c_stop(device_t dev) 552 { 553 struct i2c_softc *sc; 554 555 sc = device_get_softc(dev); 556 557 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 558 wait_for_busbusy(sc, false); 559 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 560 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); 561 return (IIC_NOERR); 562 } 563 564 static int 565 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 566 { 567 struct i2c_softc *sc; 568 u_int busfreq, div, i, ipgfreq; 569 570 sc = device_get_softc(dev); 571 572 DEVICE_DEBUGF(sc, 1, "reset\n"); 573 574 /* 575 * Look up the divisor that gives the nearest speed that doesn't exceed 576 * the configured value for the bus. 577 */ 578 ipgfreq = imx_ccm_ipg_hz(); 579 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 580 div = howmany(ipgfreq, busfreq); 581 for (i = 0; i < nitems(clkdiv_table); i++) { 582 if (clkdiv_table[i].divisor >= div) 583 break; 584 } 585 586 /* 587 * Calculate roughly how long it will take to transfer a byte (which 588 * requires 9 clock cycles) at the new bus speed. This value is used to 589 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 590 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 591 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 592 */ 593 busfreq = ipgfreq / clkdiv_table[i].divisor; 594 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 595 596 /* 597 * Disable the controller (do the reset), and set the new clock divisor. 598 */ 599 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 600 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 601 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 602 603 /* 604 * Now that the controller is idle, perform bus recovery. If the bus 605 * isn't hung, this a fairly fast no-op. 606 */ 607 return (i2c_recover_bus(sc)); 608 } 609 610 static int 611 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 612 { 613 struct i2c_softc *sc; 614 int error, reg; 615 616 sc = device_get_softc(dev); 617 *read = 0; 618 619 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); 620 if (len) { 621 if (len == 1) 622 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 623 I2CCR_MSTA | I2CCR_TXAK); 624 else 625 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 626 I2CCR_MSTA); 627 /* Dummy read to prime the receiver. */ 628 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 629 i2c_read_reg(sc, I2C_DATA_REG); 630 } 631 632 error = 0; 633 *read = 0; 634 while (*read < len) { 635 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 636 break; 637 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 638 if (last) { 639 if (*read == len - 2) { 640 /* NO ACK on last byte */ 641 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 642 I2CCR_MSTA | I2CCR_TXAK); 643 } else if (*read == len - 1) { 644 /* Transfer done, signal stop. */ 645 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 646 I2CCR_TXAK); 647 wait_for_busbusy(sc, false); 648 } 649 } 650 reg = i2c_read_reg(sc, I2C_DATA_REG); 651 DEBUGF(sc, 1, "0x%02x ", reg); 652 *buf++ = reg; 653 (*read)++; 654 } 655 DEBUGF(sc, 1, "\n"); 656 657 return (i2c_error_handler(sc, error)); 658 } 659 660 static int 661 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 662 { 663 struct i2c_softc *sc; 664 int error; 665 666 sc = device_get_softc(dev); 667 668 error = 0; 669 *sent = 0; 670 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); 671 while (*sent < len) { 672 DEBUGF(sc, 1, "0x%02x ", *buf); 673 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 674 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 675 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 676 break; 677 (*sent)++; 678 } 679 DEBUGF(sc, 1, "\n"); 680 return (i2c_error_handler(sc, error)); 681 } 682