1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/gpio.h> 52 #include <sys/kernel.h> 53 #include <sys/limits.h> 54 #include <sys/module.h> 55 #include <sys/resource.h> 56 #include <sys/sysctl.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/rman.h> 61 62 #include <arm/freescale/imx/imx_ccmvar.h> 63 64 #include <dev/iicbus/iiconf.h> 65 #include <dev/iicbus/iicbus.h> 66 #include <dev/iicbus/iic_recover_bus.h> 67 #include "iicbus_if.h" 68 69 #include <dev/ofw/openfirm.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include <dev/fdt/fdt_pinctrl.h> 74 #include <dev/gpio/gpiobusvar.h> 75 76 #if defined(__aarch64__) 77 #define IMX_ENABLE_CLOCKS 78 #endif 79 80 #ifdef IMX_ENABLE_CLOCKS 81 #include <dev/extres/clk/clk.h> 82 #endif 83 84 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 85 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 86 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 87 #define I2C_STATUS_REG 0x0C /* I2C status register */ 88 #define I2C_DATA_REG 0x10 /* I2C data register */ 89 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 90 91 #define I2CCR_MEN (1 << 7) /* Module enable */ 92 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 93 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 94 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 95 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 96 97 #define I2CSR_MCF (1 << 7) /* Data transfer */ 98 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 99 #define I2CSR_MBB (1 << 5) /* Bus busy */ 100 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 101 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 102 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 103 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 104 105 #define I2C_BAUD_RATE_FAST 0x31 106 #define I2C_BAUD_RATE_DEF 0x3F 107 #define I2C_DFSSR_DIV 0x10 108 109 /* 110 * A table of available divisors and the associated coded values to put in the 111 * FDR register to achieve that divisor.. There is no algorithmic relationship I 112 * can see between divisors and the codes that go into the register. The table 113 * begins and ends with entries that handle insane configuration values. 114 */ 115 struct clkdiv { 116 u_int divisor; 117 u_int regcode; 118 }; 119 static struct clkdiv clkdiv_table[] = { 120 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 121 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 122 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 123 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 124 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 125 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 126 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 127 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 128 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 129 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 130 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 131 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 132 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 133 }; 134 135 static struct ofw_compat_data compat_data[] = { 136 {"fsl,imx21-i2c", 1}, 137 {"fsl,imx6q-i2c", 1}, 138 {"fsl,imx-i2c", 1}, 139 {NULL, 0} 140 }; 141 142 struct i2c_softc { 143 device_t dev; 144 device_t iicbus; 145 struct resource *res; 146 int rid; 147 sbintime_t byte_time_sbt; 148 int rb_pinctl_idx; 149 gpio_pin_t rb_sclpin; 150 gpio_pin_t rb_sdapin; 151 u_int debug; 152 u_int slave; 153 #ifdef IMX_ENABLE_CLOCKS 154 clk_t ipgclk; 155 #endif 156 }; 157 158 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 159 if ((lvl) <= (sc)->debug) \ 160 device_printf((sc)->dev, fmt, ##args) 161 162 #define DEBUGF(sc, lvl, fmt, args...) \ 163 if ((lvl) <= (sc)->debug) \ 164 printf(fmt, ##args) 165 166 static phandle_t i2c_get_node(device_t, device_t); 167 static int i2c_probe(device_t); 168 static int i2c_attach(device_t); 169 static int i2c_detach(device_t); 170 171 static int i2c_repeated_start(device_t, u_char, int); 172 static int i2c_start(device_t, u_char, int); 173 static int i2c_stop(device_t); 174 static int i2c_reset(device_t, u_char, u_char, u_char *); 175 static int i2c_read(device_t, char *, int, int *, int, int); 176 static int i2c_write(device_t, const char *, int, int *, int); 177 178 static device_method_t i2c_methods[] = { 179 DEVMETHOD(device_probe, i2c_probe), 180 DEVMETHOD(device_attach, i2c_attach), 181 DEVMETHOD(device_detach, i2c_detach), 182 183 /* OFW methods */ 184 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 185 186 DEVMETHOD(iicbus_callback, iicbus_null_callback), 187 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 188 DEVMETHOD(iicbus_start, i2c_start), 189 DEVMETHOD(iicbus_stop, i2c_stop), 190 DEVMETHOD(iicbus_reset, i2c_reset), 191 DEVMETHOD(iicbus_read, i2c_read), 192 DEVMETHOD(iicbus_write, i2c_write), 193 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 194 195 DEVMETHOD_END 196 }; 197 198 static driver_t i2c_driver = { 199 "imx_i2c", 200 i2c_methods, 201 sizeof(struct i2c_softc), 202 }; 203 204 DRIVER_MODULE(imx_i2c, simplebus, i2c_driver, 0, 0); 205 DRIVER_MODULE(ofw_iicbus, imx_i2c, ofw_iicbus_driver, 0, 0); 206 MODULE_DEPEND(imx_i2c, iicbus, 1, 1, 1); 207 SIMPLEBUS_PNP_INFO(compat_data); 208 209 static phandle_t 210 i2c_get_node(device_t bus, device_t dev) 211 { 212 /* 213 * Share controller node with iicbus device 214 */ 215 return ofw_bus_get_node(bus); 216 } 217 218 static __inline void 219 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 220 { 221 222 bus_write_1(sc->res, off, val); 223 } 224 225 static __inline uint8_t 226 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 227 { 228 229 return (bus_read_1(sc->res, off)); 230 } 231 232 static __inline void 233 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 234 { 235 uint8_t status; 236 237 status = i2c_read_reg(sc, off); 238 status |= mask; 239 i2c_write_reg(sc, off, status); 240 } 241 242 /* Wait for bus to become busy or not-busy. */ 243 static int 244 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 245 { 246 int retry, srb; 247 248 retry = 1000; 249 while (retry --) { 250 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 251 if ((srb && wantbusy) || (!srb && !wantbusy)) 252 return (IIC_NOERR); 253 DELAY(1); 254 } 255 return (IIC_ETIMEOUT); 256 } 257 258 /* Wait for transfer to complete, optionally check RXAK. */ 259 static int 260 wait_for_xfer(struct i2c_softc *sc, int checkack) 261 { 262 int retry, sr; 263 264 /* 265 * Sleep for about the time it takes to transfer a byte (with precision 266 * set to tolerate 5% oversleep). We calculate the approximate byte 267 * transfer time when we set the bus speed divisor. Slaves are allowed 268 * to do clock-stretching so the actual transfer time can be larger, but 269 * this gets the bulk of the waiting out of the way without tying up the 270 * processor the whole time. 271 */ 272 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 273 274 retry = 10000; 275 while (retry --) { 276 sr = i2c_read_reg(sc, I2C_STATUS_REG); 277 if (sr & I2CSR_MIF) { 278 if (sr & I2CSR_MAL) 279 return (IIC_EBUSERR); 280 else if (checkack && (sr & I2CSR_RXAK)) 281 return (IIC_ENOACK); 282 else 283 return (IIC_NOERR); 284 } 285 DELAY(1); 286 } 287 return (IIC_ETIMEOUT); 288 } 289 290 /* 291 * Implement the error handling shown in the state diagram of the imx6 reference 292 * manual. If there was an error, then: 293 * - Clear master mode (MSTA and MTX). 294 * - Wait for the bus to become free or for a timeout to happen. 295 * - Disable the controller. 296 */ 297 static int 298 i2c_error_handler(struct i2c_softc *sc, int error) 299 { 300 301 if (error != 0) { 302 i2c_write_reg(sc, I2C_STATUS_REG, 0); 303 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 304 wait_for_busbusy(sc, false); 305 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 306 } 307 return (error); 308 } 309 310 static int 311 i2c_recover_getsda(void *ctx) 312 { 313 bool active; 314 315 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 316 return (active); 317 } 318 319 static void 320 i2c_recover_setsda(void *ctx, int value) 321 { 322 323 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 324 } 325 326 static int 327 i2c_recover_getscl(void *ctx) 328 { 329 bool active; 330 331 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 332 return (active); 333 334 } 335 336 static void 337 i2c_recover_setscl(void *ctx, int value) 338 { 339 340 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 341 } 342 343 static int 344 i2c_recover_bus(struct i2c_softc *sc) 345 { 346 struct iicrb_pin_access pins; 347 int err; 348 349 /* 350 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 351 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 352 * recovery sequence if necessary, then configure the pins back to i2c 353 * mode (idx 0). 354 */ 355 if (sc->rb_pinctl_idx == 0) 356 return (0); 357 358 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 359 360 pins.ctx = sc; 361 pins.getsda = i2c_recover_getsda; 362 pins.setsda = i2c_recover_setsda; 363 pins.getscl = i2c_recover_getscl; 364 pins.setscl = i2c_recover_setscl; 365 err = iic_recover_bus(&pins); 366 367 fdt_pinctrl_configure(sc->dev, 0); 368 369 return (err); 370 } 371 372 static int 373 i2c_probe(device_t dev) 374 { 375 376 if (!ofw_bus_status_okay(dev)) 377 return (ENXIO); 378 379 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 380 return (ENXIO); 381 382 device_set_desc(dev, "Freescale i.MX I2C"); 383 384 return (BUS_PROBE_DEFAULT); 385 } 386 387 static int 388 i2c_attach(device_t dev) 389 { 390 char wrkstr[16]; 391 struct i2c_softc *sc; 392 phandle_t node; 393 int err, cfgidx; 394 395 sc = device_get_softc(dev); 396 sc->dev = dev; 397 sc->rid = 0; 398 399 #ifdef IMX_ENABLE_CLOCKS 400 if (clk_get_by_ofw_index(sc->dev, 0, 0, &sc->ipgclk) != 0) { 401 device_printf(dev, "could not get ipg clock"); 402 return (ENOENT); 403 } 404 405 err = clk_enable(sc->ipgclk); 406 if (err != 0) { 407 device_printf(sc->dev, "could not enable ipg clock\n"); 408 return (err); 409 } 410 #endif 411 412 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 413 RF_ACTIVE); 414 if (sc->res == NULL) { 415 device_printf(dev, "could not allocate resources"); 416 return (ENXIO); 417 } 418 419 sc->iicbus = device_add_child(dev, "iicbus", -1); 420 if (sc->iicbus == NULL) { 421 device_printf(dev, "could not add iicbus child"); 422 return (ENXIO); 423 } 424 425 /* Set up debug-enable sysctl. */ 426 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 427 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 428 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 429 "Enable debug; 1=reads/writes, 2=add starts/stops"); 430 431 /* 432 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 433 * properties are present. This is optional. If all the config data is 434 * not in place, we just don't do gpio bitbang bus recovery. 435 */ 436 node = ofw_bus_get_node(sc->dev); 437 438 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 439 &sc->rb_sclpin); 440 if (err != 0) 441 goto no_recovery; 442 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 443 &sc->rb_sdapin); 444 if (err != 0) 445 goto no_recovery; 446 447 /* 448 * Preset the gpio pins to output high (idle bus state). The signal 449 * won't actually appear on the pins until the bus recovery code changes 450 * the pinmux config from i2c to gpio. 451 */ 452 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 453 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 454 gpio_pin_set_active(sc->rb_sclpin, true); 455 gpio_pin_set_active(sc->rb_sdapin, true); 456 457 /* 458 * Obtain the index of pinctrl node for bus recovery using gpio pins, 459 * then confirm that pinctrl properties exist for that index and for the 460 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 461 * will also do a bus recovery, so setting this value must be last. 462 */ 463 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 464 if (err == 0) { 465 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 466 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 467 sc->rb_pinctl_idx = cfgidx; 468 } 469 470 no_recovery: 471 472 /* We don't do a hardware reset here because iicbus_attach() does it. */ 473 474 /* Probe and attach the iicbus when interrupts are available. */ 475 return (bus_delayed_attach_children(dev)); 476 } 477 478 static int 479 i2c_detach(device_t dev) 480 { 481 struct i2c_softc *sc; 482 int error; 483 484 sc = device_get_softc(dev); 485 486 #ifdef IMX_ENABLE_CLOCKS 487 error = clk_disable(sc->ipgclk); 488 if (error != 0) { 489 device_printf(sc->dev, "could not disable ipg clock\n"); 490 return (error); 491 } 492 #endif 493 494 if ((error = bus_generic_detach(sc->dev)) != 0) { 495 device_printf(sc->dev, "cannot detach child devices\n"); 496 return (error); 497 } 498 499 if (sc->iicbus != NULL) 500 device_delete_child(dev, sc->iicbus); 501 502 /* Release bus-recover pins; gpio_pin_release() handles NULL args. */ 503 gpio_pin_release(sc->rb_sclpin); 504 gpio_pin_release(sc->rb_sdapin); 505 506 if (sc->res != NULL) 507 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 508 509 return (0); 510 } 511 512 static int 513 i2c_repeated_start(device_t dev, u_char slave, int timeout) 514 { 515 struct i2c_softc *sc; 516 int error; 517 518 sc = device_get_softc(dev); 519 520 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 521 return (IIC_EBUSERR); 522 } 523 524 /* 525 * Set repeated start condition, delay (per reference manual, min 156nS) 526 * before writing slave address, wait for ack after write. 527 */ 528 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 529 DELAY(1); 530 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 531 i2c_write_reg(sc, I2C_DATA_REG, slave); 532 sc->slave = slave; 533 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); 534 error = wait_for_xfer(sc, true); 535 return (i2c_error_handler(sc, error)); 536 } 537 538 static int 539 i2c_start_ll(device_t dev, u_char slave, int timeout) 540 { 541 struct i2c_softc *sc; 542 int error; 543 544 sc = device_get_softc(dev); 545 546 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 547 DELAY(10); /* Delay for controller to sample bus state. */ 548 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 549 return (i2c_error_handler(sc, IIC_EBUSERR)); 550 } 551 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 552 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 553 return (i2c_error_handler(sc, error)); 554 i2c_write_reg(sc, I2C_STATUS_REG, 0); 555 i2c_write_reg(sc, I2C_DATA_REG, slave); 556 sc->slave = slave; 557 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); 558 error = wait_for_xfer(sc, true); 559 return (i2c_error_handler(sc, error)); 560 } 561 562 static int 563 i2c_start(device_t dev, u_char slave, int timeout) 564 { 565 struct i2c_softc *sc; 566 int error; 567 568 sc = device_get_softc(dev); 569 570 /* 571 * Invoke the low-level code to put the bus into master mode and address 572 * the given slave. If that fails, idle the controller and attempt a 573 * bus recovery, and then try again one time. Signaling a start and 574 * addressing the slave is the only operation that a low-level driver 575 * can safely retry without any help from the upper layers that know 576 * more about the slave device. 577 */ 578 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 579 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 580 if ((error = i2c_recover_bus(sc)) != 0) 581 return (error); 582 error = i2c_start_ll(dev, slave, timeout); 583 } 584 return (error); 585 } 586 587 static int 588 i2c_stop(device_t dev) 589 { 590 struct i2c_softc *sc; 591 592 sc = device_get_softc(dev); 593 594 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 595 wait_for_busbusy(sc, false); 596 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 597 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); 598 return (IIC_NOERR); 599 } 600 601 static int 602 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 603 { 604 struct i2c_softc *sc; 605 u_int busfreq, div, i, ipgfreq; 606 #ifdef IMX_ENABLE_CLOCKS 607 int err; 608 uint64_t freq; 609 #endif 610 611 sc = device_get_softc(dev); 612 613 DEVICE_DEBUGF(sc, 1, "reset\n"); 614 615 /* 616 * Look up the divisor that gives the nearest speed that doesn't exceed 617 * the configured value for the bus. 618 */ 619 #ifdef IMX_ENABLE_CLOCKS 620 err = clk_get_freq(sc->ipgclk, &freq); 621 if (err != 0) { 622 device_printf(sc->dev, "cannot get frequency\n"); 623 return (err); 624 } 625 ipgfreq = (int32_t)freq; 626 #else 627 ipgfreq = imx_ccm_ipg_hz(); 628 #endif 629 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 630 div = howmany(ipgfreq, busfreq); 631 for (i = 0; i < nitems(clkdiv_table); i++) { 632 if (clkdiv_table[i].divisor >= div) 633 break; 634 } 635 636 /* 637 * Calculate roughly how long it will take to transfer a byte (which 638 * requires 9 clock cycles) at the new bus speed. This value is used to 639 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 640 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 641 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 642 */ 643 busfreq = ipgfreq / clkdiv_table[i].divisor; 644 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 645 646 /* 647 * Disable the controller (do the reset), and set the new clock divisor. 648 */ 649 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 650 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 651 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 652 653 /* 654 * Now that the controller is idle, perform bus recovery. If the bus 655 * isn't hung, this a fairly fast no-op. 656 */ 657 return (i2c_recover_bus(sc)); 658 } 659 660 static int 661 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 662 { 663 struct i2c_softc *sc; 664 int error, reg; 665 666 sc = device_get_softc(dev); 667 *read = 0; 668 669 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); 670 if (len) { 671 if (len == 1) 672 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 673 I2CCR_MSTA | I2CCR_TXAK); 674 else 675 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 676 I2CCR_MSTA); 677 /* Dummy read to prime the receiver. */ 678 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 679 i2c_read_reg(sc, I2C_DATA_REG); 680 } 681 682 error = 0; 683 *read = 0; 684 while (*read < len) { 685 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 686 break; 687 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 688 if (last) { 689 if (*read == len - 2) { 690 /* NO ACK on last byte */ 691 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 692 I2CCR_MSTA | I2CCR_TXAK); 693 } else if (*read == len - 1) { 694 /* Transfer done, signal stop. */ 695 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 696 I2CCR_TXAK); 697 wait_for_busbusy(sc, false); 698 } 699 } 700 reg = i2c_read_reg(sc, I2C_DATA_REG); 701 DEBUGF(sc, 1, "0x%02x ", reg); 702 *buf++ = reg; 703 (*read)++; 704 } 705 DEBUGF(sc, 1, "\n"); 706 707 return (i2c_error_handler(sc, error)); 708 } 709 710 static int 711 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 712 { 713 struct i2c_softc *sc; 714 int error; 715 716 sc = device_get_softc(dev); 717 718 error = 0; 719 *sent = 0; 720 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); 721 while (*sent < len) { 722 DEBUGF(sc, 1, "0x%02x ", *buf); 723 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 724 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 725 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 726 break; 727 (*sent)++; 728 } 729 DEBUGF(sc, 1, "\n"); 730 return (i2c_error_handler(sc, error)); 731 } 732