1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/gpio.h> 52 #include <sys/kernel.h> 53 #include <sys/limits.h> 54 #include <sys/module.h> 55 #include <sys/resource.h> 56 #include <sys/sysctl.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/rman.h> 61 62 #include <arm/freescale/imx/imx_ccmvar.h> 63 64 #include <dev/iicbus/iiconf.h> 65 #include <dev/iicbus/iicbus.h> 66 #include <dev/iicbus/iic_recover_bus.h> 67 #include "iicbus_if.h" 68 69 #include <dev/ofw/openfirm.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include <dev/fdt/fdt_pinctrl.h> 74 #include <dev/gpio/gpiobusvar.h> 75 76 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 77 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 78 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 79 #define I2C_STATUS_REG 0x0C /* I2C status register */ 80 #define I2C_DATA_REG 0x10 /* I2C data register */ 81 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 82 83 #define I2CCR_MEN (1 << 7) /* Module enable */ 84 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 85 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 86 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 87 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 88 89 #define I2CSR_MCF (1 << 7) /* Data transfer */ 90 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 91 #define I2CSR_MBB (1 << 5) /* Bus busy */ 92 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 93 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 94 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 95 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 96 97 #define I2C_BAUD_RATE_FAST 0x31 98 #define I2C_BAUD_RATE_DEF 0x3F 99 #define I2C_DFSSR_DIV 0x10 100 101 /* 102 * A table of available divisors and the associated coded values to put in the 103 * FDR register to achieve that divisor.. There is no algorithmic relationship I 104 * can see between divisors and the codes that go into the register. The table 105 * begins and ends with entries that handle insane configuration values. 106 */ 107 struct clkdiv { 108 u_int divisor; 109 u_int regcode; 110 }; 111 static struct clkdiv clkdiv_table[] = { 112 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 113 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 114 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 115 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 116 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 117 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 118 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 119 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 120 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 121 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 122 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 123 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 124 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 125 }; 126 127 static struct ofw_compat_data compat_data[] = { 128 {"fsl,imx6q-i2c", 1}, 129 {"fsl,imx-i2c", 1}, 130 {NULL, 0} 131 }; 132 133 struct i2c_softc { 134 device_t dev; 135 device_t iicbus; 136 struct resource *res; 137 int rid; 138 sbintime_t byte_time_sbt; 139 int rb_pinctl_idx; 140 gpio_pin_t rb_sclpin; 141 gpio_pin_t rb_sdapin; 142 u_int debug; 143 u_int slave; 144 }; 145 146 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 147 if ((lvl) <= (sc)->debug) \ 148 device_printf((sc)->dev, fmt, ##args) 149 150 #define DEBUGF(sc, lvl, fmt, args...) \ 151 if ((lvl) <= (sc)->debug) \ 152 printf(fmt, ##args) 153 154 static phandle_t i2c_get_node(device_t, device_t); 155 static int i2c_probe(device_t); 156 static int i2c_attach(device_t); 157 158 static int i2c_repeated_start(device_t, u_char, int); 159 static int i2c_start(device_t, u_char, int); 160 static int i2c_stop(device_t); 161 static int i2c_reset(device_t, u_char, u_char, u_char *); 162 static int i2c_read(device_t, char *, int, int *, int, int); 163 static int i2c_write(device_t, const char *, int, int *, int); 164 165 static device_method_t i2c_methods[] = { 166 DEVMETHOD(device_probe, i2c_probe), 167 DEVMETHOD(device_attach, i2c_attach), 168 169 /* OFW methods */ 170 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 171 172 DEVMETHOD(iicbus_callback, iicbus_null_callback), 173 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 174 DEVMETHOD(iicbus_start, i2c_start), 175 DEVMETHOD(iicbus_stop, i2c_stop), 176 DEVMETHOD(iicbus_reset, i2c_reset), 177 DEVMETHOD(iicbus_read, i2c_read), 178 DEVMETHOD(iicbus_write, i2c_write), 179 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 180 181 DEVMETHOD_END 182 }; 183 184 static driver_t i2c_driver = { 185 "iichb", 186 i2c_methods, 187 sizeof(struct i2c_softc), 188 }; 189 static devclass_t i2c_devclass; 190 191 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 192 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 193 194 static phandle_t 195 i2c_get_node(device_t bus, device_t dev) 196 { 197 /* 198 * Share controller node with iicbus device 199 */ 200 return ofw_bus_get_node(bus); 201 } 202 203 static __inline void 204 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 205 { 206 207 bus_write_1(sc->res, off, val); 208 } 209 210 static __inline uint8_t 211 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 212 { 213 214 return (bus_read_1(sc->res, off)); 215 } 216 217 static __inline void 218 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 219 { 220 uint8_t status; 221 222 status = i2c_read_reg(sc, off); 223 status |= mask; 224 i2c_write_reg(sc, off, status); 225 } 226 227 /* Wait for bus to become busy or not-busy. */ 228 static int 229 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 230 { 231 int retry, srb; 232 233 retry = 1000; 234 while (retry --) { 235 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 236 if ((srb && wantbusy) || (!srb && !wantbusy)) 237 return (IIC_NOERR); 238 DELAY(1); 239 } 240 return (IIC_ETIMEOUT); 241 } 242 243 /* Wait for transfer to complete, optionally check RXAK. */ 244 static int 245 wait_for_xfer(struct i2c_softc *sc, int checkack) 246 { 247 int retry, sr; 248 249 /* 250 * Sleep for about the time it takes to transfer a byte (with precision 251 * set to tolerate 5% oversleep). We calculate the approximate byte 252 * transfer time when we set the bus speed divisor. Slaves are allowed 253 * to do clock-stretching so the actual transfer time can be larger, but 254 * this gets the bulk of the waiting out of the way without tying up the 255 * processor the whole time. 256 */ 257 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 258 259 retry = 10000; 260 while (retry --) { 261 sr = i2c_read_reg(sc, I2C_STATUS_REG); 262 if (sr & I2CSR_MIF) { 263 if (sr & I2CSR_MAL) 264 return (IIC_EBUSERR); 265 else if (checkack && (sr & I2CSR_RXAK)) 266 return (IIC_ENOACK); 267 else 268 return (IIC_NOERR); 269 } 270 DELAY(1); 271 } 272 return (IIC_ETIMEOUT); 273 } 274 275 /* 276 * Implement the error handling shown in the state diagram of the imx6 reference 277 * manual. If there was an error, then: 278 * - Clear master mode (MSTA and MTX). 279 * - Wait for the bus to become free or for a timeout to happen. 280 * - Disable the controller. 281 */ 282 static int 283 i2c_error_handler(struct i2c_softc *sc, int error) 284 { 285 286 if (error != 0) { 287 i2c_write_reg(sc, I2C_STATUS_REG, 0); 288 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 289 wait_for_busbusy(sc, false); 290 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 291 } 292 return (error); 293 } 294 295 static int 296 i2c_recover_getsda(void *ctx) 297 { 298 bool active; 299 300 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 301 return (active); 302 } 303 304 static void 305 i2c_recover_setsda(void *ctx, int value) 306 { 307 308 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 309 } 310 311 static int 312 i2c_recover_getscl(void *ctx) 313 { 314 bool active; 315 316 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 317 return (active); 318 319 } 320 321 static void 322 i2c_recover_setscl(void *ctx, int value) 323 { 324 325 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 326 } 327 328 static int 329 i2c_recover_bus(struct i2c_softc *sc) 330 { 331 struct iicrb_pin_access pins; 332 int err; 333 334 /* 335 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 336 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 337 * recovery sequence if necessary, then configure the pins back to i2c 338 * mode (idx 0). 339 */ 340 if (sc->rb_pinctl_idx == 0) 341 return (0); 342 343 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 344 345 pins.ctx = sc; 346 pins.getsda = i2c_recover_getsda; 347 pins.setsda = i2c_recover_setsda; 348 pins.getscl = i2c_recover_getscl; 349 pins.setscl = i2c_recover_setscl; 350 err = iic_recover_bus(&pins); 351 352 fdt_pinctrl_configure(sc->dev, 0); 353 354 return (err); 355 } 356 357 static int 358 i2c_probe(device_t dev) 359 { 360 361 if (!ofw_bus_status_okay(dev)) 362 return (ENXIO); 363 364 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 365 return (ENXIO); 366 367 device_set_desc(dev, "Freescale i.MX I2C"); 368 369 return (BUS_PROBE_DEFAULT); 370 } 371 372 static int 373 i2c_attach(device_t dev) 374 { 375 char wrkstr[16]; 376 struct i2c_softc *sc; 377 phandle_t node; 378 int err, cfgidx; 379 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 sc->rid = 0; 383 384 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 385 RF_ACTIVE); 386 if (sc->res == NULL) { 387 device_printf(dev, "could not allocate resources"); 388 return (ENXIO); 389 } 390 391 sc->iicbus = device_add_child(dev, "iicbus", -1); 392 if (sc->iicbus == NULL) { 393 device_printf(dev, "could not add iicbus child"); 394 return (ENXIO); 395 } 396 397 /* Set up debug-enable sysctl. */ 398 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 399 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 400 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 401 "Enable debug; 1=reads/writes, 2=add starts/stops"); 402 403 /* 404 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 405 * properties are present. This is optional. If all the config data is 406 * not in place, we just don't do gpio bitbang bus recovery. 407 */ 408 node = ofw_bus_get_node(sc->dev); 409 410 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 411 &sc->rb_sclpin); 412 if (err != 0) 413 goto no_recovery; 414 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 415 &sc->rb_sdapin); 416 if (err != 0) 417 goto no_recovery; 418 419 /* 420 * Preset the gpio pins to output high (idle bus state). The signal 421 * won't actually appear on the pins until the bus recovery code changes 422 * the pinmux config from i2c to gpio. 423 */ 424 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 425 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 426 gpio_pin_set_active(sc->rb_sclpin, true); 427 gpio_pin_set_active(sc->rb_sdapin, true); 428 429 /* 430 * Obtain the index of pinctrl node for bus recovery using gpio pins, 431 * then confirm that pinctrl properties exist for that index and for the 432 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 433 * will also do a bus recovery, so setting this value must be last. 434 */ 435 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 436 if (err == 0) { 437 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 438 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 439 sc->rb_pinctl_idx = cfgidx; 440 } 441 442 no_recovery: 443 444 /* We don't do a hardware reset here because iicbus_attach() does it. */ 445 446 /* Probe and attach the iicbus when interrupts are available. */ 447 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 448 return (0); 449 } 450 451 static int 452 i2c_repeated_start(device_t dev, u_char slave, int timeout) 453 { 454 struct i2c_softc *sc; 455 int error; 456 457 sc = device_get_softc(dev); 458 459 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 460 return (IIC_EBUSERR); 461 } 462 463 /* 464 * Set repeated start condition, delay (per reference manual, min 156nS) 465 * before writing slave address, wait for ack after write. 466 */ 467 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 468 DELAY(1); 469 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 470 i2c_write_reg(sc, I2C_DATA_REG, slave); 471 sc->slave = slave; 472 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); 473 error = wait_for_xfer(sc, true); 474 return (i2c_error_handler(sc, error)); 475 } 476 477 static int 478 i2c_start_ll(device_t dev, u_char slave, int timeout) 479 { 480 struct i2c_softc *sc; 481 int error; 482 483 sc = device_get_softc(dev); 484 485 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 486 DELAY(10); /* Delay for controller to sample bus state. */ 487 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 488 return (i2c_error_handler(sc, IIC_EBUSERR)); 489 } 490 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 491 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 492 return (i2c_error_handler(sc, error)); 493 i2c_write_reg(sc, I2C_STATUS_REG, 0); 494 i2c_write_reg(sc, I2C_DATA_REG, slave); 495 sc->slave = slave; 496 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); 497 error = wait_for_xfer(sc, true); 498 return (i2c_error_handler(sc, error)); 499 } 500 501 static int 502 i2c_start(device_t dev, u_char slave, int timeout) 503 { 504 struct i2c_softc *sc; 505 int error; 506 507 sc = device_get_softc(dev); 508 509 /* 510 * Invoke the low-level code to put the bus into master mode and address 511 * the given slave. If that fails, idle the controller and attempt a 512 * bus recovery, and then try again one time. Signaling a start and 513 * addressing the slave is the only operation that a low-level driver 514 * can safely retry without any help from the upper layers that know 515 * more about the slave device. 516 */ 517 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 518 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 519 if ((error = i2c_recover_bus(sc)) != 0) 520 return (error); 521 error = i2c_start_ll(dev, slave, timeout); 522 } 523 return (error); 524 } 525 526 static int 527 i2c_stop(device_t dev) 528 { 529 struct i2c_softc *sc; 530 531 sc = device_get_softc(dev); 532 533 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 534 wait_for_busbusy(sc, false); 535 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 536 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); 537 return (IIC_NOERR); 538 } 539 540 static int 541 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 542 { 543 struct i2c_softc *sc; 544 u_int busfreq, div, i, ipgfreq; 545 546 sc = device_get_softc(dev); 547 548 DEVICE_DEBUGF(sc, 1, "reset\n"); 549 550 /* 551 * Look up the divisor that gives the nearest speed that doesn't exceed 552 * the configured value for the bus. 553 */ 554 ipgfreq = imx_ccm_ipg_hz(); 555 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 556 div = howmany(ipgfreq, busfreq); 557 for (i = 0; i < nitems(clkdiv_table); i++) { 558 if (clkdiv_table[i].divisor >= div) 559 break; 560 } 561 562 /* 563 * Calculate roughly how long it will take to transfer a byte (which 564 * requires 9 clock cycles) at the new bus speed. This value is used to 565 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 566 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 567 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 568 */ 569 busfreq = ipgfreq / clkdiv_table[i].divisor; 570 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 571 572 /* 573 * Disable the controller (do the reset), and set the new clock divisor. 574 */ 575 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 576 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 577 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 578 579 /* 580 * Now that the controller is idle, perform bus recovery. If the bus 581 * isn't hung, this a fairly fast no-op. 582 */ 583 return (i2c_recover_bus(sc)); 584 } 585 586 static int 587 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 588 { 589 struct i2c_softc *sc; 590 int error, reg; 591 592 sc = device_get_softc(dev); 593 *read = 0; 594 595 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); 596 if (len) { 597 if (len == 1) 598 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 599 I2CCR_MSTA | I2CCR_TXAK); 600 else 601 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 602 I2CCR_MSTA); 603 /* Dummy read to prime the receiver. */ 604 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 605 i2c_read_reg(sc, I2C_DATA_REG); 606 } 607 608 error = 0; 609 *read = 0; 610 while (*read < len) { 611 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 612 break; 613 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 614 if (last) { 615 if (*read == len - 2) { 616 /* NO ACK on last byte */ 617 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 618 I2CCR_MSTA | I2CCR_TXAK); 619 } else if (*read == len - 1) { 620 /* Transfer done, signal stop. */ 621 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 622 I2CCR_TXAK); 623 wait_for_busbusy(sc, false); 624 } 625 } 626 reg = i2c_read_reg(sc, I2C_DATA_REG); 627 DEBUGF(sc, 1, "0x%02x ", reg); 628 *buf++ = reg; 629 (*read)++; 630 } 631 DEBUGF(sc, 1, "\n"); 632 633 return (i2c_error_handler(sc, error)); 634 } 635 636 static int 637 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 638 { 639 struct i2c_softc *sc; 640 int error; 641 642 sc = device_get_softc(dev); 643 644 error = 0; 645 *sent = 0; 646 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); 647 while (*sent < len) { 648 DEBUGF(sc, 1, "0x%02x ", *buf); 649 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 650 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 651 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 652 break; 653 (*sent)++; 654 } 655 DEBUGF(sc, 1, "\n"); 656 return (i2c_error_handler(sc, error)); 657 } 658