1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/gpio.h> 52 #include <sys/kernel.h> 53 #include <sys/limits.h> 54 #include <sys/module.h> 55 #include <sys/resource.h> 56 #include <sys/sysctl.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/rman.h> 61 62 #include <arm/freescale/imx/imx_ccmvar.h> 63 64 #include <dev/iicbus/iiconf.h> 65 #include <dev/iicbus/iicbus.h> 66 #include <dev/iicbus/iic_recover_bus.h> 67 #include "iicbus_if.h" 68 69 #include <dev/ofw/openfirm.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include <dev/fdt/fdt_pinctrl.h> 74 #include <dev/gpio/gpiobusvar.h> 75 76 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 77 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 78 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 79 #define I2C_STATUS_REG 0x0C /* I2C status register */ 80 #define I2C_DATA_REG 0x10 /* I2C data register */ 81 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 82 83 #define I2CCR_MEN (1 << 7) /* Module enable */ 84 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 85 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 86 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 87 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 88 89 #define I2CSR_MCF (1 << 7) /* Data transfer */ 90 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 91 #define I2CSR_MBB (1 << 5) /* Bus busy */ 92 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 93 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 94 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 95 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 96 97 #define I2C_BAUD_RATE_FAST 0x31 98 #define I2C_BAUD_RATE_DEF 0x3F 99 #define I2C_DFSSR_DIV 0x10 100 101 /* 102 * A table of available divisors and the associated coded values to put in the 103 * FDR register to achieve that divisor.. There is no algorithmic relationship I 104 * can see between divisors and the codes that go into the register. The table 105 * begins and ends with entries that handle insane configuration values. 106 */ 107 struct clkdiv { 108 u_int divisor; 109 u_int regcode; 110 }; 111 static struct clkdiv clkdiv_table[] = { 112 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 113 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 114 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 115 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 116 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 117 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 118 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 119 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 120 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 121 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 122 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 123 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 124 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 125 }; 126 127 static struct ofw_compat_data compat_data[] = { 128 {"fsl,imx6q-i2c", 1}, 129 {"fsl,imx-i2c", 1}, 130 {NULL, 0} 131 }; 132 133 struct i2c_softc { 134 device_t dev; 135 device_t iicbus; 136 struct resource *res; 137 int rid; 138 sbintime_t byte_time_sbt; 139 int rb_pinctl_idx; 140 gpio_pin_t rb_sclpin; 141 gpio_pin_t rb_sdapin; 142 u_int debug; 143 u_int slave; 144 }; 145 146 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 147 if ((lvl) <= (sc)->debug) \ 148 device_printf((sc)->dev, fmt, ##args) 149 150 #define DEBUGF(sc, lvl, fmt, args...) \ 151 if ((lvl) <= (sc)->debug) \ 152 printf(fmt, ##args) 153 154 static phandle_t i2c_get_node(device_t, device_t); 155 static int i2c_probe(device_t); 156 static int i2c_attach(device_t); 157 static int i2c_detach(device_t); 158 159 static int i2c_repeated_start(device_t, u_char, int); 160 static int i2c_start(device_t, u_char, int); 161 static int i2c_stop(device_t); 162 static int i2c_reset(device_t, u_char, u_char, u_char *); 163 static int i2c_read(device_t, char *, int, int *, int, int); 164 static int i2c_write(device_t, const char *, int, int *, int); 165 166 static device_method_t i2c_methods[] = { 167 DEVMETHOD(device_probe, i2c_probe), 168 DEVMETHOD(device_attach, i2c_attach), 169 DEVMETHOD(device_detach, i2c_detach), 170 171 /* OFW methods */ 172 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 173 174 DEVMETHOD(iicbus_callback, iicbus_null_callback), 175 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 176 DEVMETHOD(iicbus_start, i2c_start), 177 DEVMETHOD(iicbus_stop, i2c_stop), 178 DEVMETHOD(iicbus_reset, i2c_reset), 179 DEVMETHOD(iicbus_read, i2c_read), 180 DEVMETHOD(iicbus_write, i2c_write), 181 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 182 183 DEVMETHOD_END 184 }; 185 186 static driver_t i2c_driver = { 187 "imx_i2c", 188 i2c_methods, 189 sizeof(struct i2c_softc), 190 }; 191 static devclass_t i2c_devclass; 192 193 DRIVER_MODULE(imx_i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 194 DRIVER_MODULE(ofw_iicbus, imx_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 0, 0); 195 MODULE_DEPEND(imx_i2c, iicbus, 1, 1, 1); 196 MODULE_DEPEND(imx_i2c, ofw_iicbus, 1, 1, 1); 197 SIMPLEBUS_PNP_INFO(compat_data); 198 199 static phandle_t 200 i2c_get_node(device_t bus, device_t dev) 201 { 202 /* 203 * Share controller node with iicbus device 204 */ 205 return ofw_bus_get_node(bus); 206 } 207 208 static __inline void 209 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 210 { 211 212 bus_write_1(sc->res, off, val); 213 } 214 215 static __inline uint8_t 216 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 217 { 218 219 return (bus_read_1(sc->res, off)); 220 } 221 222 static __inline void 223 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 224 { 225 uint8_t status; 226 227 status = i2c_read_reg(sc, off); 228 status |= mask; 229 i2c_write_reg(sc, off, status); 230 } 231 232 /* Wait for bus to become busy or not-busy. */ 233 static int 234 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 235 { 236 int retry, srb; 237 238 retry = 1000; 239 while (retry --) { 240 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 241 if ((srb && wantbusy) || (!srb && !wantbusy)) 242 return (IIC_NOERR); 243 DELAY(1); 244 } 245 return (IIC_ETIMEOUT); 246 } 247 248 /* Wait for transfer to complete, optionally check RXAK. */ 249 static int 250 wait_for_xfer(struct i2c_softc *sc, int checkack) 251 { 252 int retry, sr; 253 254 /* 255 * Sleep for about the time it takes to transfer a byte (with precision 256 * set to tolerate 5% oversleep). We calculate the approximate byte 257 * transfer time when we set the bus speed divisor. Slaves are allowed 258 * to do clock-stretching so the actual transfer time can be larger, but 259 * this gets the bulk of the waiting out of the way without tying up the 260 * processor the whole time. 261 */ 262 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 263 264 retry = 10000; 265 while (retry --) { 266 sr = i2c_read_reg(sc, I2C_STATUS_REG); 267 if (sr & I2CSR_MIF) { 268 if (sr & I2CSR_MAL) 269 return (IIC_EBUSERR); 270 else if (checkack && (sr & I2CSR_RXAK)) 271 return (IIC_ENOACK); 272 else 273 return (IIC_NOERR); 274 } 275 DELAY(1); 276 } 277 return (IIC_ETIMEOUT); 278 } 279 280 /* 281 * Implement the error handling shown in the state diagram of the imx6 reference 282 * manual. If there was an error, then: 283 * - Clear master mode (MSTA and MTX). 284 * - Wait for the bus to become free or for a timeout to happen. 285 * - Disable the controller. 286 */ 287 static int 288 i2c_error_handler(struct i2c_softc *sc, int error) 289 { 290 291 if (error != 0) { 292 i2c_write_reg(sc, I2C_STATUS_REG, 0); 293 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 294 wait_for_busbusy(sc, false); 295 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 296 } 297 return (error); 298 } 299 300 static int 301 i2c_recover_getsda(void *ctx) 302 { 303 bool active; 304 305 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 306 return (active); 307 } 308 309 static void 310 i2c_recover_setsda(void *ctx, int value) 311 { 312 313 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 314 } 315 316 static int 317 i2c_recover_getscl(void *ctx) 318 { 319 bool active; 320 321 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 322 return (active); 323 324 } 325 326 static void 327 i2c_recover_setscl(void *ctx, int value) 328 { 329 330 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 331 } 332 333 static int 334 i2c_recover_bus(struct i2c_softc *sc) 335 { 336 struct iicrb_pin_access pins; 337 int err; 338 339 /* 340 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 341 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 342 * recovery sequence if necessary, then configure the pins back to i2c 343 * mode (idx 0). 344 */ 345 if (sc->rb_pinctl_idx == 0) 346 return (0); 347 348 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 349 350 pins.ctx = sc; 351 pins.getsda = i2c_recover_getsda; 352 pins.setsda = i2c_recover_setsda; 353 pins.getscl = i2c_recover_getscl; 354 pins.setscl = i2c_recover_setscl; 355 err = iic_recover_bus(&pins); 356 357 fdt_pinctrl_configure(sc->dev, 0); 358 359 return (err); 360 } 361 362 static int 363 i2c_probe(device_t dev) 364 { 365 366 if (!ofw_bus_status_okay(dev)) 367 return (ENXIO); 368 369 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 370 return (ENXIO); 371 372 device_set_desc(dev, "Freescale i.MX I2C"); 373 374 return (BUS_PROBE_DEFAULT); 375 } 376 377 static int 378 i2c_attach(device_t dev) 379 { 380 char wrkstr[16]; 381 struct i2c_softc *sc; 382 phandle_t node; 383 int err, cfgidx; 384 385 sc = device_get_softc(dev); 386 sc->dev = dev; 387 sc->rid = 0; 388 389 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 390 RF_ACTIVE); 391 if (sc->res == NULL) { 392 device_printf(dev, "could not allocate resources"); 393 return (ENXIO); 394 } 395 396 sc->iicbus = device_add_child(dev, "iicbus", -1); 397 if (sc->iicbus == NULL) { 398 device_printf(dev, "could not add iicbus child"); 399 return (ENXIO); 400 } 401 402 /* Set up debug-enable sysctl. */ 403 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 404 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 405 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 406 "Enable debug; 1=reads/writes, 2=add starts/stops"); 407 408 /* 409 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 410 * properties are present. This is optional. If all the config data is 411 * not in place, we just don't do gpio bitbang bus recovery. 412 */ 413 node = ofw_bus_get_node(sc->dev); 414 415 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 416 &sc->rb_sclpin); 417 if (err != 0) 418 goto no_recovery; 419 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 420 &sc->rb_sdapin); 421 if (err != 0) 422 goto no_recovery; 423 424 /* 425 * Preset the gpio pins to output high (idle bus state). The signal 426 * won't actually appear on the pins until the bus recovery code changes 427 * the pinmux config from i2c to gpio. 428 */ 429 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 430 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 431 gpio_pin_set_active(sc->rb_sclpin, true); 432 gpio_pin_set_active(sc->rb_sdapin, true); 433 434 /* 435 * Obtain the index of pinctrl node for bus recovery using gpio pins, 436 * then confirm that pinctrl properties exist for that index and for the 437 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 438 * will also do a bus recovery, so setting this value must be last. 439 */ 440 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 441 if (err == 0) { 442 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 443 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 444 sc->rb_pinctl_idx = cfgidx; 445 } 446 447 no_recovery: 448 449 /* We don't do a hardware reset here because iicbus_attach() does it. */ 450 451 /* Probe and attach the iicbus when interrupts are available. */ 452 return (bus_delayed_attach_children(dev)); 453 } 454 455 static int 456 i2c_detach(device_t dev) 457 { 458 struct i2c_softc *sc; 459 int error; 460 461 sc = device_get_softc(dev); 462 463 if ((error = bus_generic_detach(sc->dev)) != 0) { 464 device_printf(sc->dev, "cannot detach child devices\n"); 465 return (error); 466 } 467 468 if (sc->iicbus != NULL) 469 device_delete_child(dev, sc->iicbus); 470 471 /* Release bus-recover pins; gpio_pin_release() handles NULL args. */ 472 gpio_pin_release(sc->rb_sclpin); 473 gpio_pin_release(sc->rb_sdapin); 474 475 if (sc->res != NULL) 476 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 477 478 return (0); 479 } 480 481 static int 482 i2c_repeated_start(device_t dev, u_char slave, int timeout) 483 { 484 struct i2c_softc *sc; 485 int error; 486 487 sc = device_get_softc(dev); 488 489 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 490 return (IIC_EBUSERR); 491 } 492 493 /* 494 * Set repeated start condition, delay (per reference manual, min 156nS) 495 * before writing slave address, wait for ack after write. 496 */ 497 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 498 DELAY(1); 499 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 500 i2c_write_reg(sc, I2C_DATA_REG, slave); 501 sc->slave = slave; 502 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); 503 error = wait_for_xfer(sc, true); 504 return (i2c_error_handler(sc, error)); 505 } 506 507 static int 508 i2c_start_ll(device_t dev, u_char slave, int timeout) 509 { 510 struct i2c_softc *sc; 511 int error; 512 513 sc = device_get_softc(dev); 514 515 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 516 DELAY(10); /* Delay for controller to sample bus state. */ 517 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 518 return (i2c_error_handler(sc, IIC_EBUSERR)); 519 } 520 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 521 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 522 return (i2c_error_handler(sc, error)); 523 i2c_write_reg(sc, I2C_STATUS_REG, 0); 524 i2c_write_reg(sc, I2C_DATA_REG, slave); 525 sc->slave = slave; 526 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); 527 error = wait_for_xfer(sc, true); 528 return (i2c_error_handler(sc, error)); 529 } 530 531 static int 532 i2c_start(device_t dev, u_char slave, int timeout) 533 { 534 struct i2c_softc *sc; 535 int error; 536 537 sc = device_get_softc(dev); 538 539 /* 540 * Invoke the low-level code to put the bus into master mode and address 541 * the given slave. If that fails, idle the controller and attempt a 542 * bus recovery, and then try again one time. Signaling a start and 543 * addressing the slave is the only operation that a low-level driver 544 * can safely retry without any help from the upper layers that know 545 * more about the slave device. 546 */ 547 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 548 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 549 if ((error = i2c_recover_bus(sc)) != 0) 550 return (error); 551 error = i2c_start_ll(dev, slave, timeout); 552 } 553 return (error); 554 } 555 556 static int 557 i2c_stop(device_t dev) 558 { 559 struct i2c_softc *sc; 560 561 sc = device_get_softc(dev); 562 563 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 564 wait_for_busbusy(sc, false); 565 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 566 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); 567 return (IIC_NOERR); 568 } 569 570 static int 571 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 572 { 573 struct i2c_softc *sc; 574 u_int busfreq, div, i, ipgfreq; 575 576 sc = device_get_softc(dev); 577 578 DEVICE_DEBUGF(sc, 1, "reset\n"); 579 580 /* 581 * Look up the divisor that gives the nearest speed that doesn't exceed 582 * the configured value for the bus. 583 */ 584 ipgfreq = imx_ccm_ipg_hz(); 585 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 586 div = howmany(ipgfreq, busfreq); 587 for (i = 0; i < nitems(clkdiv_table); i++) { 588 if (clkdiv_table[i].divisor >= div) 589 break; 590 } 591 592 /* 593 * Calculate roughly how long it will take to transfer a byte (which 594 * requires 9 clock cycles) at the new bus speed. This value is used to 595 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 596 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 597 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 598 */ 599 busfreq = ipgfreq / clkdiv_table[i].divisor; 600 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 601 602 /* 603 * Disable the controller (do the reset), and set the new clock divisor. 604 */ 605 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 606 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 607 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 608 609 /* 610 * Now that the controller is idle, perform bus recovery. If the bus 611 * isn't hung, this a fairly fast no-op. 612 */ 613 return (i2c_recover_bus(sc)); 614 } 615 616 static int 617 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 618 { 619 struct i2c_softc *sc; 620 int error, reg; 621 622 sc = device_get_softc(dev); 623 *read = 0; 624 625 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); 626 if (len) { 627 if (len == 1) 628 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 629 I2CCR_MSTA | I2CCR_TXAK); 630 else 631 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 632 I2CCR_MSTA); 633 /* Dummy read to prime the receiver. */ 634 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 635 i2c_read_reg(sc, I2C_DATA_REG); 636 } 637 638 error = 0; 639 *read = 0; 640 while (*read < len) { 641 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 642 break; 643 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 644 if (last) { 645 if (*read == len - 2) { 646 /* NO ACK on last byte */ 647 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 648 I2CCR_MSTA | I2CCR_TXAK); 649 } else if (*read == len - 1) { 650 /* Transfer done, signal stop. */ 651 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 652 I2CCR_TXAK); 653 wait_for_busbusy(sc, false); 654 } 655 } 656 reg = i2c_read_reg(sc, I2C_DATA_REG); 657 DEBUGF(sc, 1, "0x%02x ", reg); 658 *buf++ = reg; 659 (*read)++; 660 } 661 DEBUGF(sc, 1, "\n"); 662 663 return (i2c_error_handler(sc, error)); 664 } 665 666 static int 667 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 668 { 669 struct i2c_softc *sc; 670 int error; 671 672 sc = device_get_softc(dev); 673 674 error = 0; 675 *sent = 0; 676 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); 677 while (*sent < len) { 678 DEBUGF(sc, 1, "0x%02x ", *buf); 679 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 680 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 681 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 682 break; 683 (*sent)++; 684 } 685 DEBUGF(sc, 1, "\n"); 686 return (i2c_error_handler(sc, error)); 687 } 688