1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012, 2013 The FreeBSD Foundation 5 * 6 * This software was developed by Oleksandr Rybalko under sponsorship 7 * from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Registers definition for Freescale i.MX515 Generic Periodic Timer */ 32 33 #define IMX_GPT_CR 0x0000 /* Control Register R/W */ 34 #define GPT_CR_FO3 (1U << 31) 35 #define GPT_CR_FO2 (1 << 30) 36 #define GPT_CR_FO1 (1 << 29) 37 #define GPT_CR_OM3_SHIFT 26 38 #define GPT_CR_OM3_MASK 0x1c000000 39 #define GPT_CR_OM2_SHIFT 23 40 #define GPT_CR_OM2_MASK 0x03800000 41 #define GPT_CR_OM1_SHIFT 20 42 #define GPT_CR_OM1_MASK 0x00700000 43 #define GPT_CR_OMX_NONE 0 44 #define GPT_CR_OMX_TOGGLE 1 45 #define GPT_CR_OMX_CLEAR 2 46 #define GPT_CR_OMX_SET 3 47 #define GPT_CR_OMX_PULSE 4 /* Run CLKSRC on output pin */ 48 #define GPT_CR_IM2_SHIFT 18 49 #define GPT_CR_IM2_MASK 0x000c0000 50 #define GPT_CR_IM1_SHIFT 16 51 #define GPT_CR_IM1_MASK 0x00030000 52 #define GPT_CR_IMX_NONE 0 53 #define GPT_CR_IMX_REDGE 1 54 #define GPT_CR_IMX_FEDGE 2 55 #define GPT_CR_IMX_BOTH 3 56 #define GPT_CR_SWR (1 << 15) 57 #define GPT_CR_24MEN (1 << 10) 58 #define GPT_CR_FRR (1 << 9) 59 #define GPT_CR_CLKSRC_NONE (0 << 6) 60 #define GPT_CR_CLKSRC_IPG (1 << 6) 61 #define GPT_CR_CLKSRC_IPG_HIGH (2 << 6) 62 #define GPT_CR_CLKSRC_EXT (3 << 6) 63 #define GPT_CR_CLKSRC_32K (4 << 6) 64 #define GPT_CR_CLKSRC_24M (5 << 6) 65 #define GPT_CR_STOPEN (1 << 5) 66 #define GPT_CR_DOZEEN (1 << 4) 67 #define GPT_CR_WAITEN (1 << 3) 68 #define GPT_CR_DBGEN (1 << 2) 69 #define GPT_CR_ENMOD (1 << 1) 70 #define GPT_CR_EN (1 << 0) 71 72 #define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */ 73 #define GPT_PR_VALUE_SHIFT 0 74 #define GPT_PR_VALUE_MASK 0x00000fff 75 #define GPT_PR_VALUE_SHIFT_24M 12 76 #define GPT_PR_VALUE_MASK_24M 0x0000f000 77 78 /* Same map for SR and IR */ 79 #define IMX_GPT_SR 0x0008 /* Status Register R/W */ 80 #define IMX_GPT_IR 0x000c /* Interrupt Register R/W */ 81 #define GPT_IR_ROV (1 << 5) 82 #define GPT_IR_IF2 (1 << 4) 83 #define GPT_IR_IF1 (1 << 3) 84 #define GPT_IR_OF3 (1 << 2) 85 #define GPT_IR_OF2 (1 << 1) 86 #define GPT_IR_OF1 (1 << 0) 87 #define GPT_IR_ALL \ 88 (GPT_IR_ROV | \ 89 GPT_IR_IF2 | \ 90 GPT_IR_IF1 | \ 91 GPT_IR_OF3 | \ 92 GPT_IR_OF2 | \ 93 GPT_IR_OF1) 94 95 #define IMX_GPT_OCR1 0x0010 /* Output Compare Register 1 R/W */ 96 #define IMX_GPT_OCR2 0x0014 /* Output Compare Register 2 R/W */ 97 #define IMX_GPT_OCR3 0x0018 /* Output Compare Register 3 R/W */ 98 #define IMX_GPT_ICR1 0x001c /* Input capture Register 1 RO */ 99 #define IMX_GPT_ICR2 0x0020 /* Input capture Register 2 RO */ 100 #define IMX_GPT_CNT 0x0024 /* Counter Register RO */ 101