1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2013 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Oleksandr Rybalko under sponsorship 8 * from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 /* Registers definition for Freescale i.MX515 Generic Periodic Timer */ 35 36 #define IMX_GPT_CR 0x0000 /* Control Register R/W */ 37 #define GPT_CR_FO3 (1U << 31) 38 #define GPT_CR_FO2 (1 << 30) 39 #define GPT_CR_FO1 (1 << 29) 40 #define GPT_CR_OM3_SHIFT 26 41 #define GPT_CR_OM3_MASK 0x1c000000 42 #define GPT_CR_OM2_SHIFT 23 43 #define GPT_CR_OM2_MASK 0x03800000 44 #define GPT_CR_OM1_SHIFT 20 45 #define GPT_CR_OM1_MASK 0x00700000 46 #define GPT_CR_OMX_NONE 0 47 #define GPT_CR_OMX_TOGGLE 1 48 #define GPT_CR_OMX_CLEAR 2 49 #define GPT_CR_OMX_SET 3 50 #define GPT_CR_OMX_PULSE 4 /* Run CLKSRC on output pin */ 51 #define GPT_CR_IM2_SHIFT 18 52 #define GPT_CR_IM2_MASK 0x000c0000 53 #define GPT_CR_IM1_SHIFT 16 54 #define GPT_CR_IM1_MASK 0x00030000 55 #define GPT_CR_IMX_NONE 0 56 #define GPT_CR_IMX_REDGE 1 57 #define GPT_CR_IMX_FEDGE 2 58 #define GPT_CR_IMX_BOTH 3 59 #define GPT_CR_SWR (1 << 15) 60 #define GPT_CR_24MEN (1 << 10) 61 #define GPT_CR_FRR (1 << 9) 62 #define GPT_CR_CLKSRC_NONE (0 << 6) 63 #define GPT_CR_CLKSRC_IPG (1 << 6) 64 #define GPT_CR_CLKSRC_IPG_HIGH (2 << 6) 65 #define GPT_CR_CLKSRC_EXT (3 << 6) 66 #define GPT_CR_CLKSRC_32K (4 << 6) 67 #define GPT_CR_CLKSRC_24M (5 << 6) 68 #define GPT_CR_STOPEN (1 << 5) 69 #define GPT_CR_DOZEEN (1 << 4) 70 #define GPT_CR_WAITEN (1 << 3) 71 #define GPT_CR_DBGEN (1 << 2) 72 #define GPT_CR_ENMOD (1 << 1) 73 #define GPT_CR_EN (1 << 0) 74 75 #define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */ 76 #define GPT_PR_VALUE_SHIFT 0 77 #define GPT_PR_VALUE_MASK 0x00000fff 78 #define GPT_PR_VALUE_SHIFT_24M 12 79 #define GPT_PR_VALUE_MASK_24M 0x0000f000 80 81 /* Same map for SR and IR */ 82 #define IMX_GPT_SR 0x0008 /* Status Register R/W */ 83 #define IMX_GPT_IR 0x000c /* Interrupt Register R/W */ 84 #define GPT_IR_ROV (1 << 5) 85 #define GPT_IR_IF2 (1 << 4) 86 #define GPT_IR_IF1 (1 << 3) 87 #define GPT_IR_OF3 (1 << 2) 88 #define GPT_IR_OF2 (1 << 1) 89 #define GPT_IR_OF1 (1 << 0) 90 #define GPT_IR_ALL \ 91 (GPT_IR_ROV | \ 92 GPT_IR_IF2 | \ 93 GPT_IR_IF1 | \ 94 GPT_IR_OF3 | \ 95 GPT_IR_OF2 | \ 96 GPT_IR_OF1) 97 98 #define IMX_GPT_OCR1 0x0010 /* Output Compare Register 1 R/W */ 99 #define IMX_GPT_OCR2 0x0014 /* Output Compare Register 2 R/W */ 100 #define IMX_GPT_OCR3 0x0018 /* Output Compare Register 3 R/W */ 101 #define IMX_GPT_ICR1 0x001c /* Input capture Register 1 RO */ 102 #define IMX_GPT_ICR2 0x0020 /* Input capture Register 2 RO */ 103 #define IMX_GPT_CNT 0x0024 /* Counter Register RO */ 104