1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/malloc.h> 39 #include <sys/rman.h> 40 #include <sys/timeet.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 #include <machine/frame.h> 46 #include <machine/intr.h> 47 48 #include <machine/fdt.h> 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <arm/freescale/imx/imx_gptvar.h> 55 #include <arm/freescale/imx/imx_gptreg.h> 56 57 #include <sys/kdb.h> 58 #include <arm/freescale/imx/imx51_ccmvar.h> 59 60 #define WRITE4(_sc, _r, _v) \ 61 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 62 #define READ4(_sc, _r) \ 63 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 64 #define SET4(_sc, _r, _m) \ 65 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 66 #define CLEAR4(_sc, _r, _m) \ 67 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 68 69 static u_int imx_gpt_get_timecount(struct timecounter *); 70 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 71 sbintime_t); 72 static int imx_gpt_timer_stop(struct eventtimer *); 73 74 static int imx_gpt_intr(void *); 75 static int imx_gpt_probe(device_t); 76 static int imx_gpt_attach(device_t); 77 78 static struct timecounter imx_gpt_timecounter = { 79 .tc_name = "i.MX GPT Timecounter", 80 .tc_get_timecount = imx_gpt_get_timecount, 81 .tc_counter_mask = ~0u, 82 .tc_frequency = 0, 83 .tc_quality = 1000, 84 }; 85 86 /* Global softc pointer for use in DELAY(). */ 87 struct imx_gpt_softc *imx_gpt_sc = NULL; 88 89 /* 90 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 91 * at 792mhz. It will delay a bit too long on slower processors -- that's 92 * better than not delaying long enough. In practice this is unlikely to get 93 * used much since the clock driver is one of the first to start up, and once 94 * we're attached the delay loop switches to using the timer hardware. 95 */ 96 static const int imx_gpt_delay_count = 78; 97 98 /* Try to divide down an available fast clock to this frequency. */ 99 #define TARGET_FREQUENCY 1000000 100 101 /* Don't try to set an event timer period smaller than this. */ 102 #define MIN_ET_PERIOD 10LLU 103 104 105 static struct resource_spec imx_gpt_spec[] = { 106 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 107 { SYS_RES_IRQ, 0, RF_ACTIVE }, 108 { -1, 0 } 109 }; 110 111 static int 112 imx_gpt_probe(device_t dev) 113 { 114 115 if (!ofw_bus_is_compatible(dev, "fsl,imx51-gpt") && 116 !ofw_bus_is_compatible(dev, "fsl,imx53-gpt")) 117 return (ENXIO); 118 119 device_set_desc(dev, "Freescale i.MX GPT timer"); 120 return (BUS_PROBE_DEFAULT); 121 } 122 123 static int 124 imx_gpt_attach(device_t dev) 125 { 126 struct imx_gpt_softc *sc; 127 int ctlreg, err; 128 uint32_t basefreq, prescale; 129 130 sc = device_get_softc(dev); 131 132 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 133 device_printf(dev, "could not allocate resources\n"); 134 return (ENXIO); 135 } 136 137 sc->sc_dev = dev; 138 sc->sc_iot = rman_get_bustag(sc->res[0]); 139 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 140 141 /* 142 * For now, just automatically choose a good clock for the hardware 143 * we're running on. Eventually we could allow selection from the fdt; 144 * the code in this driver will cope with any clock frequency. 145 */ 146 if (ofw_bus_is_compatible(dev, "fsl,imx6-gpt")) 147 sc->sc_clksrc = GPT_CR_CLKSRC_24M; 148 else 149 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 150 151 ctlreg = 0; 152 153 switch (sc->sc_clksrc) { 154 case GPT_CR_CLKSRC_32K: 155 basefreq = 32768; 156 break; 157 case GPT_CR_CLKSRC_IPG: 158 basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); 159 break; 160 case GPT_CR_CLKSRC_IPG_HIGH: 161 basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2; 162 break; 163 case GPT_CR_CLKSRC_24M: 164 ctlreg |= GPT_CR_24MEN; 165 basefreq = 24000000; 166 break; 167 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 168 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 169 default: 170 device_printf(dev, "Unsupported clock source '%d'\n", 171 sc->sc_clksrc); 172 return (EINVAL); 173 } 174 175 /* 176 * The following setup sequence is from the I.MX6 reference manual, 177 * "Selecting the clock source". First, disable the clock and 178 * interrupts. This also clears input and output mode bits and in 179 * general completes several of the early steps in the procedure. 180 */ 181 WRITE4(sc, IMX_GPT_CR, 0); 182 WRITE4(sc, IMX_GPT_IR, 0); 183 184 /* Choose the clock and the power-saving behaviors. */ 185 ctlreg |= 186 sc->sc_clksrc | /* Use selected clock */ 187 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 188 GPT_CR_STOPEN | /* Run in STOP mode */ 189 GPT_CR_DOZEEN | /* Run in DOZE mode */ 190 GPT_CR_WAITEN | /* Run in WAIT mode */ 191 GPT_CR_DBGEN; /* Run in DEBUG mode */ 192 WRITE4(sc, IMX_GPT_CR, ctlreg); 193 194 /* 195 * The datasheet says to do the software reset after choosing the clock 196 * source. It says nothing about needing to wait for the reset to 197 * complete, but the register description does document the fact that 198 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 199 * The reset also clears all registers except for a few of the bits in 200 * CR, but we'll rewrite all the CR bits when we start the counter. 201 */ 202 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 203 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 204 continue; 205 206 /* Set a prescaler value that gets us near the target frequency. */ 207 if (basefreq < TARGET_FREQUENCY) { 208 prescale = 0; 209 sc->clkfreq = basefreq; 210 } else { 211 prescale = basefreq / TARGET_FREQUENCY; 212 sc->clkfreq = basefreq / prescale; 213 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 214 } 215 WRITE4(sc, IMX_GPT_PR, prescale); 216 217 /* Clear the status register. */ 218 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 219 220 /* Start the counter. */ 221 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 222 223 if (bootverbose) 224 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 225 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 226 227 /* Setup the timer interrupt. */ 228 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 229 NULL, sc, &sc->sc_ih); 230 if (err != 0) { 231 bus_release_resources(dev, imx_gpt_spec, sc->res); 232 device_printf(dev, "Unable to setup the clock irq handler, " 233 "err = %d\n", err); 234 return (ENXIO); 235 } 236 237 /* Register as an eventtimer. */ 238 sc->et.et_name = "i.MXxxx GPT Eventtimer"; 239 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 240 sc->et.et_quality = 1000; 241 sc->et.et_frequency = sc->clkfreq; 242 sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 243 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 244 sc->et.et_start = imx_gpt_timer_start; 245 sc->et.et_stop = imx_gpt_timer_stop; 246 sc->et.et_priv = sc; 247 et_register(&sc->et); 248 249 /* Register as a timecounter. */ 250 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 251 tc_init(&imx_gpt_timecounter); 252 253 /* If this is the first unit, store the softc for use in DELAY. */ 254 if (device_get_unit(dev) == 0) 255 imx_gpt_sc = sc; 256 257 return (0); 258 } 259 260 static int 261 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 262 { 263 struct imx_gpt_softc *sc; 264 uint32_t ticks; 265 266 sc = (struct imx_gpt_softc *)et->et_priv; 267 268 if (period != 0) { 269 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 270 /* Set expected value */ 271 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 272 /* Enable compare register 2 Interrupt */ 273 SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 274 } else if (first != 0) { 275 ticks = ((uint32_t)et->et_frequency * first) >> 32; 276 277 /* 278 * TODO: setupt second compare reg with time which will save 279 * us in case correct one lost, f.e. if period to short and 280 * setup done later than counter reach target value. 281 */ 282 /* Do not disturb, otherwise event will be lost */ 283 spinlock_enter(); 284 /* Set expected value */ 285 WRITE4(sc, IMX_GPT_OCR1, READ4(sc, IMX_GPT_CNT) + ticks); 286 /* Enable compare register 1 Interrupt */ 287 SET4(sc, IMX_GPT_IR, GPT_IR_OF1); 288 /* Now everybody can relax */ 289 spinlock_exit(); 290 291 return (0); 292 } 293 294 return (EINVAL); 295 } 296 297 static int 298 imx_gpt_timer_stop(struct eventtimer *et) 299 { 300 struct imx_gpt_softc *sc; 301 302 sc = (struct imx_gpt_softc *)et->et_priv; 303 304 /* Disable OF2 Interrupt */ 305 CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 306 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 307 sc->sc_period = 0; 308 309 return (0); 310 } 311 312 int 313 imx_gpt_get_timerfreq(struct imx_gpt_softc *sc) 314 { 315 316 return (sc->clkfreq); 317 } 318 319 void 320 cpu_initclocks(void) 321 { 322 323 if (imx_gpt_sc == NULL) { 324 panic("%s: i.MX GPT driver has not been initialized!", __func__); 325 } 326 327 cpu_initclocks_bsp(); 328 } 329 330 static int 331 imx_gpt_intr(void *arg) 332 { 333 struct imx_gpt_softc *sc; 334 uint32_t status; 335 336 sc = (struct imx_gpt_softc *)arg; 337 338 /* Sometime we not get staus bit when interrupt arrive. Cache? */ 339 while (!(status = READ4(sc, IMX_GPT_SR))) 340 ; 341 342 if (status & GPT_IR_OF1) { 343 if (sc->et.et_active) { 344 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 345 } 346 } 347 if (status & GPT_IR_OF2) { 348 if (sc->et.et_active) { 349 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 350 /* Set expected value */ 351 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 352 sc->sc_period); 353 } 354 } 355 356 /* ACK */ 357 WRITE4(sc, IMX_GPT_SR, status); 358 359 return (FILTER_HANDLED); 360 } 361 362 u_int 363 imx_gpt_get_timecount(struct timecounter *tc) 364 { 365 366 if (imx_gpt_sc == NULL) 367 return (0); 368 369 return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 370 } 371 372 static device_method_t imx_gpt_methods[] = { 373 DEVMETHOD(device_probe, imx_gpt_probe), 374 DEVMETHOD(device_attach, imx_gpt_attach), 375 376 DEVMETHOD_END 377 }; 378 379 static driver_t imx_gpt_driver = { 380 "imx_gpt", 381 imx_gpt_methods, 382 sizeof(struct imx_gpt_softc), 383 }; 384 385 static devclass_t imx_gpt_devclass; 386 387 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 388 0, BUS_PASS_TIMER); 389 390 void 391 DELAY(int usec) 392 { 393 uint64_t curcnt, endcnt, startcnt, ticks; 394 395 /* If the timer hardware is not accessible, just use a loop. */ 396 if (imx_gpt_sc == NULL) { 397 while (usec-- > 0) 398 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 399 cpufunc_nullop(); 400 return; 401 } 402 403 /* 404 * Calculate the tick count with 64-bit values so that it works for any 405 * clock frequency. Loop until the hardware count reaches start+ticks. 406 * If the 32-bit hardware count rolls over while we're looping, just 407 * manually do a carry into the high bits after each read; don't worry 408 * that doing this on each loop iteration is inefficient -- we're trying 409 * to waste time here. 410 */ 411 ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 412 curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 413 endcnt = startcnt + ticks; 414 while (curcnt < endcnt) { 415 curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 416 if (curcnt < startcnt) 417 curcnt += 1ULL << 32; 418 } 419 } 420