1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/malloc.h> 39 #include <sys/rman.h> 40 #include <sys/timeet.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 #include <machine/intr.h> 46 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <arm/freescale/imx/imx_gptvar.h> 52 #include <arm/freescale/imx/imx_gptreg.h> 53 54 #include <sys/kdb.h> 55 #include <arm/freescale/imx/imx_ccmvar.h> 56 57 #define WRITE4(_sc, _r, _v) \ 58 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 59 #define READ4(_sc, _r) \ 60 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 61 #define SET4(_sc, _r, _m) \ 62 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 63 #define CLEAR4(_sc, _r, _m) \ 64 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 65 66 static u_int imx_gpt_get_timecount(struct timecounter *); 67 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 68 sbintime_t); 69 static int imx_gpt_timer_stop(struct eventtimer *); 70 71 static int imx_gpt_intr(void *); 72 static int imx_gpt_probe(device_t); 73 static int imx_gpt_attach(device_t); 74 75 static struct timecounter imx_gpt_timecounter = { 76 .tc_name = "iMXGPT", 77 .tc_get_timecount = imx_gpt_get_timecount, 78 .tc_counter_mask = ~0u, 79 .tc_frequency = 0, 80 .tc_quality = 1000, 81 }; 82 83 /* Global softc pointer for use in DELAY(). */ 84 struct imx_gpt_softc *imx_gpt_sc = NULL; 85 86 /* 87 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 88 * at 792mhz. It will delay a bit too long on slower processors -- that's 89 * better than not delaying long enough. In practice this is unlikely to get 90 * used much since the clock driver is one of the first to start up, and once 91 * we're attached the delay loop switches to using the timer hardware. 92 */ 93 static const int imx_gpt_delay_count = 78; 94 95 /* Try to divide down an available fast clock to this frequency. */ 96 #define TARGET_FREQUENCY 1000000000 97 98 /* Don't try to set an event timer period smaller than this. */ 99 #define MIN_ET_PERIOD 10LLU 100 101 102 static struct resource_spec imx_gpt_spec[] = { 103 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 104 { SYS_RES_IRQ, 0, RF_ACTIVE }, 105 { -1, 0 } 106 }; 107 108 static struct ofw_compat_data compat_data[] = { 109 {"fsl,imx6q-gpt", 1}, 110 {"fsl,imx53-gpt", 1}, 111 {"fsl,imx51-gpt", 1}, 112 {"fsl,imx31-gpt", 1}, 113 {"fsl,imx27-gpt", 1}, 114 {"fsl,imx25-gpt", 1}, 115 {NULL, 0} 116 }; 117 118 static int 119 imx_gpt_probe(device_t dev) 120 { 121 122 if (!ofw_bus_status_okay(dev)) 123 return (ENXIO); 124 125 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 126 device_set_desc(dev, "Freescale i.MX GPT timer"); 127 return (BUS_PROBE_DEFAULT); 128 } 129 130 return (ENXIO); 131 } 132 133 static int 134 imx_gpt_attach(device_t dev) 135 { 136 struct imx_gpt_softc *sc; 137 int ctlreg, err; 138 uint32_t basefreq, prescale; 139 140 sc = device_get_softc(dev); 141 142 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 143 device_printf(dev, "could not allocate resources\n"); 144 return (ENXIO); 145 } 146 147 sc->sc_dev = dev; 148 sc->sc_iot = rman_get_bustag(sc->res[0]); 149 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 150 151 /* 152 * For now, just automatically choose a good clock for the hardware 153 * we're running on. Eventually we could allow selection from the fdt; 154 * the code in this driver will cope with any clock frequency. 155 */ 156 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 157 158 ctlreg = 0; 159 160 switch (sc->sc_clksrc) { 161 case GPT_CR_CLKSRC_32K: 162 basefreq = 32768; 163 break; 164 case GPT_CR_CLKSRC_IPG: 165 basefreq = imx_ccm_ipg_hz(); 166 break; 167 case GPT_CR_CLKSRC_IPG_HIGH: 168 basefreq = imx_ccm_ipg_hz() * 2; 169 break; 170 case GPT_CR_CLKSRC_24M: 171 ctlreg |= GPT_CR_24MEN; 172 basefreq = 24000000; 173 break; 174 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 175 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 176 default: 177 device_printf(dev, "Unsupported clock source '%d'\n", 178 sc->sc_clksrc); 179 return (EINVAL); 180 } 181 182 /* 183 * The following setup sequence is from the I.MX6 reference manual, 184 * "Selecting the clock source". First, disable the clock and 185 * interrupts. This also clears input and output mode bits and in 186 * general completes several of the early steps in the procedure. 187 */ 188 WRITE4(sc, IMX_GPT_CR, 0); 189 WRITE4(sc, IMX_GPT_IR, 0); 190 191 /* Choose the clock and the power-saving behaviors. */ 192 ctlreg |= 193 sc->sc_clksrc | /* Use selected clock */ 194 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 195 GPT_CR_STOPEN | /* Run in STOP mode */ 196 GPT_CR_DOZEEN | /* Run in DOZE mode */ 197 GPT_CR_WAITEN | /* Run in WAIT mode */ 198 GPT_CR_DBGEN; /* Run in DEBUG mode */ 199 WRITE4(sc, IMX_GPT_CR, ctlreg); 200 201 /* 202 * The datasheet says to do the software reset after choosing the clock 203 * source. It says nothing about needing to wait for the reset to 204 * complete, but the register description does document the fact that 205 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 206 * The reset also clears all registers except for a few of the bits in 207 * CR, but we'll rewrite all the CR bits when we start the counter. 208 */ 209 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 210 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 211 continue; 212 213 /* Set a prescaler value that gets us near the target frequency. */ 214 if (basefreq < TARGET_FREQUENCY) { 215 prescale = 0; 216 sc->clkfreq = basefreq; 217 } else { 218 prescale = basefreq / TARGET_FREQUENCY; 219 sc->clkfreq = basefreq / prescale; 220 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 221 } 222 WRITE4(sc, IMX_GPT_PR, prescale); 223 224 /* Clear the status register. */ 225 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 226 227 /* Start the counter. */ 228 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 229 230 if (bootverbose) 231 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 232 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 233 234 /* Setup the timer interrupt. */ 235 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 236 NULL, sc, &sc->sc_ih); 237 if (err != 0) { 238 bus_release_resources(dev, imx_gpt_spec, sc->res); 239 device_printf(dev, "Unable to setup the clock irq handler, " 240 "err = %d\n", err); 241 return (ENXIO); 242 } 243 244 /* Register as an eventtimer. */ 245 sc->et.et_name = "iMXGPT"; 246 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 247 sc->et.et_quality = 800; 248 sc->et.et_frequency = sc->clkfreq; 249 sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 250 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 251 sc->et.et_start = imx_gpt_timer_start; 252 sc->et.et_stop = imx_gpt_timer_stop; 253 sc->et.et_priv = sc; 254 et_register(&sc->et); 255 256 /* Register as a timecounter. */ 257 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 258 tc_init(&imx_gpt_timecounter); 259 260 /* If this is the first unit, store the softc for use in DELAY. */ 261 if (device_get_unit(dev) == 0) 262 imx_gpt_sc = sc; 263 264 return (0); 265 } 266 267 static int 268 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 269 { 270 struct imx_gpt_softc *sc; 271 uint32_t ticks; 272 273 sc = (struct imx_gpt_softc *)et->et_priv; 274 275 if (period != 0) { 276 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 277 /* Set expected value */ 278 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 279 /* Enable compare register 2 Interrupt */ 280 SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 281 return (0); 282 } else if (first != 0) { 283 ticks = ((uint32_t)et->et_frequency * first) >> 32; 284 /* Do not disturb, otherwise event will be lost */ 285 spinlock_enter(); 286 /* Set expected value */ 287 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 288 /* Enable compare register 1 Interrupt */ 289 SET4(sc, IMX_GPT_IR, GPT_IR_OF3); 290 /* Now everybody can relax */ 291 spinlock_exit(); 292 return (0); 293 } 294 295 return (EINVAL); 296 } 297 298 static int 299 imx_gpt_timer_stop(struct eventtimer *et) 300 { 301 struct imx_gpt_softc *sc; 302 303 sc = (struct imx_gpt_softc *)et->et_priv; 304 305 /* Disable OF2 Interrupt */ 306 CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 307 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 308 sc->sc_period = 0; 309 310 return (0); 311 } 312 313 int 314 imx_gpt_get_timerfreq(struct imx_gpt_softc *sc) 315 { 316 317 return (sc->clkfreq); 318 } 319 320 static int 321 imx_gpt_intr(void *arg) 322 { 323 struct imx_gpt_softc *sc; 324 uint32_t status; 325 326 sc = (struct imx_gpt_softc *)arg; 327 328 status = READ4(sc, IMX_GPT_SR); 329 330 /* 331 * Clear interrupt status before invoking event callbacks. The callback 332 * often sets up a new one-shot timer event and if the interval is short 333 * enough it can fire before we get out of this function. If we cleared 334 * at the bottom we'd miss the interrupt and hang until the clock wraps. 335 */ 336 WRITE4(sc, IMX_GPT_SR, status); 337 338 /* Handle one-shot timer events. */ 339 if (status & GPT_IR_OF3) { 340 if (sc->et.et_active) { 341 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 342 } 343 } 344 345 /* Handle periodic timer events. */ 346 if (status & GPT_IR_OF2) { 347 if (sc->et.et_active) 348 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 349 if (sc->sc_period != 0) 350 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 351 sc->sc_period); 352 } 353 354 return (FILTER_HANDLED); 355 } 356 357 u_int 358 imx_gpt_get_timecount(struct timecounter *tc) 359 { 360 361 if (imx_gpt_sc == NULL) 362 return (0); 363 364 return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 365 } 366 367 static device_method_t imx_gpt_methods[] = { 368 DEVMETHOD(device_probe, imx_gpt_probe), 369 DEVMETHOD(device_attach, imx_gpt_attach), 370 371 DEVMETHOD_END 372 }; 373 374 static driver_t imx_gpt_driver = { 375 "imx_gpt", 376 imx_gpt_methods, 377 sizeof(struct imx_gpt_softc), 378 }; 379 380 static devclass_t imx_gpt_devclass; 381 382 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 383 0, BUS_PASS_TIMER); 384 385 void 386 DELAY(int usec) 387 { 388 uint64_t curcnt, endcnt, startcnt, ticks; 389 390 /* If the timer hardware is not accessible, just use a loop. */ 391 if (imx_gpt_sc == NULL) { 392 while (usec-- > 0) 393 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 394 cpufunc_nullop(); 395 return; 396 } 397 398 /* 399 * Calculate the tick count with 64-bit values so that it works for any 400 * clock frequency. Loop until the hardware count reaches start+ticks. 401 * If the 32-bit hardware count rolls over while we're looping, just 402 * manually do a carry into the high bits after each read; don't worry 403 * that doing this on each loop iteration is inefficient -- we're trying 404 * to waste time here. 405 */ 406 ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 407 curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 408 endcnt = startcnt + ticks; 409 while (curcnt < endcnt) { 410 curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 411 if (curcnt < startcnt) 412 curcnt += 1ULL << 32; 413 } 414 } 415