1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/timeet.h> 40 #include <sys/timetc.h> 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <arm/freescale/imx/imx_ccmvar.h> 49 #include <arm/freescale/imx/imx_gptreg.h> 50 51 #define WRITE4(_sc, _r, _v) \ 52 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 53 #define READ4(_sc, _r) \ 54 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 55 #define SET4(_sc, _r, _m) \ 56 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 57 #define CLEAR4(_sc, _r, _m) \ 58 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 59 60 static u_int imx_gpt_get_timecount(struct timecounter *); 61 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 62 sbintime_t); 63 static int imx_gpt_timer_stop(struct eventtimer *); 64 65 static int imx_gpt_intr(void *); 66 static int imx_gpt_probe(device_t); 67 static int imx_gpt_attach(device_t); 68 69 static struct timecounter imx_gpt_timecounter = { 70 .tc_name = "iMXGPT", 71 .tc_get_timecount = imx_gpt_get_timecount, 72 .tc_counter_mask = ~0u, 73 .tc_frequency = 0, 74 .tc_quality = 1000, 75 }; 76 77 struct imx_gpt_softc { 78 device_t sc_dev; 79 struct resource * res[2]; 80 bus_space_tag_t sc_iot; 81 bus_space_handle_t sc_ioh; 82 void * sc_ih; /* interrupt handler */ 83 uint32_t sc_period; 84 uint32_t sc_clksrc; 85 uint32_t clkfreq; 86 uint32_t ir_reg; 87 struct eventtimer et; 88 }; 89 90 /* Global softc pointer for use in DELAY(). */ 91 static struct imx_gpt_softc *imx_gpt_sc; 92 93 /* 94 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 95 * at 792mhz. It will delay a bit too long on slower processors -- that's 96 * better than not delaying long enough. In practice this is unlikely to get 97 * used much since the clock driver is one of the first to start up, and once 98 * we're attached the delay loop switches to using the timer hardware. 99 */ 100 static const int imx_gpt_delay_count = 78; 101 102 /* Try to divide down an available fast clock to this frequency. */ 103 #define TARGET_FREQUENCY 1000000000 104 105 static struct resource_spec imx_gpt_spec[] = { 106 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 107 { SYS_RES_IRQ, 0, RF_ACTIVE }, 108 { -1, 0 } 109 }; 110 111 static struct ofw_compat_data compat_data[] = { 112 {"fsl,imx6dl-gpt", 1}, 113 {"fsl,imx6q-gpt", 1}, 114 {"fsl,imx53-gpt", 1}, 115 {"fsl,imx51-gpt", 1}, 116 {"fsl,imx31-gpt", 1}, 117 {"fsl,imx27-gpt", 1}, 118 {"fsl,imx25-gpt", 1}, 119 {NULL, 0} 120 }; 121 122 static int 123 imx_gpt_probe(device_t dev) 124 { 125 126 if (!ofw_bus_status_okay(dev)) 127 return (ENXIO); 128 129 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 130 device_set_desc(dev, "Freescale i.MX GPT timer"); 131 return (BUS_PROBE_DEFAULT); 132 } 133 134 return (ENXIO); 135 } 136 137 static int 138 imx_gpt_attach(device_t dev) 139 { 140 struct imx_gpt_softc *sc; 141 int ctlreg, err; 142 uint32_t basefreq, prescale, setup_ticks, t1, t2; 143 144 sc = device_get_softc(dev); 145 146 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 147 device_printf(dev, "could not allocate resources\n"); 148 return (ENXIO); 149 } 150 151 sc->sc_dev = dev; 152 sc->sc_iot = rman_get_bustag(sc->res[0]); 153 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 154 155 /* 156 * For now, just automatically choose a good clock for the hardware 157 * we're running on. Eventually we could allow selection from the fdt; 158 * the code in this driver will cope with any clock frequency. 159 */ 160 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 161 162 ctlreg = 0; 163 164 switch (sc->sc_clksrc) { 165 case GPT_CR_CLKSRC_32K: 166 basefreq = 32768; 167 break; 168 case GPT_CR_CLKSRC_IPG: 169 basefreq = imx_ccm_ipg_hz(); 170 break; 171 case GPT_CR_CLKSRC_IPG_HIGH: 172 basefreq = imx_ccm_ipg_hz() * 2; 173 break; 174 case GPT_CR_CLKSRC_24M: 175 ctlreg |= GPT_CR_24MEN; 176 basefreq = 24000000; 177 break; 178 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 179 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 180 default: 181 device_printf(dev, "Unsupported clock source '%d'\n", 182 sc->sc_clksrc); 183 return (EINVAL); 184 } 185 186 /* 187 * The following setup sequence is from the I.MX6 reference manual, 188 * "Selecting the clock source". First, disable the clock and 189 * interrupts. This also clears input and output mode bits and in 190 * general completes several of the early steps in the procedure. 191 */ 192 WRITE4(sc, IMX_GPT_CR, 0); 193 WRITE4(sc, IMX_GPT_IR, 0); 194 195 /* Choose the clock and the power-saving behaviors. */ 196 ctlreg |= 197 sc->sc_clksrc | /* Use selected clock */ 198 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 199 GPT_CR_STOPEN | /* Run in STOP mode */ 200 GPT_CR_DOZEEN | /* Run in DOZE mode */ 201 GPT_CR_WAITEN | /* Run in WAIT mode */ 202 GPT_CR_DBGEN; /* Run in DEBUG mode */ 203 WRITE4(sc, IMX_GPT_CR, ctlreg); 204 205 /* 206 * The datasheet says to do the software reset after choosing the clock 207 * source. It says nothing about needing to wait for the reset to 208 * complete, but the register description does document the fact that 209 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 210 * The reset also clears all registers except for a few of the bits in 211 * CR, but we'll rewrite all the CR bits when we start the counter. 212 */ 213 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 214 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 215 continue; 216 217 /* Set a prescaler value that gets us near the target frequency. */ 218 if (basefreq < TARGET_FREQUENCY) { 219 prescale = 0; 220 sc->clkfreq = basefreq; 221 } else { 222 prescale = basefreq / TARGET_FREQUENCY; 223 sc->clkfreq = basefreq / prescale; 224 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 225 } 226 WRITE4(sc, IMX_GPT_PR, prescale); 227 228 /* Clear the status register. */ 229 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 230 231 /* Start the counter. */ 232 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 233 234 if (bootverbose) 235 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 236 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 237 238 /* Setup the timer interrupt. */ 239 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 240 NULL, sc, &sc->sc_ih); 241 if (err != 0) { 242 bus_release_resources(dev, imx_gpt_spec, sc->res); 243 device_printf(dev, "Unable to setup the clock irq handler, " 244 "err = %d\n", err); 245 return (ENXIO); 246 } 247 248 /* 249 * Measure how many clock ticks it takes to setup a one-shot event (it's 250 * longer than you might think, due to wait states in accessing gpt 251 * registers). Scale up the result by a factor of 1.5 to be safe, 252 * and use that to set the minimum eventtimer period we can schedule. In 253 * the real world, the value works out to about 750ns on imx5 hardware. 254 */ 255 t1 = READ4(sc, IMX_GPT_CNT); 256 WRITE4(sc, IMX_GPT_OCR3, 0); 257 t2 = READ4(sc, IMX_GPT_CNT); 258 setup_ticks = ((t2 - t1 + 1) * 3) / 2; 259 260 /* Register as an eventtimer. */ 261 sc->et.et_name = "iMXGPT"; 262 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 263 sc->et.et_quality = 800; 264 sc->et.et_frequency = sc->clkfreq; 265 sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq; 266 sc->et.et_max_period = ((uint64_t)0xfffffffe << 32) / sc->clkfreq; 267 sc->et.et_start = imx_gpt_timer_start; 268 sc->et.et_stop = imx_gpt_timer_stop; 269 sc->et.et_priv = sc; 270 et_register(&sc->et); 271 272 /* Register as a timecounter. */ 273 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 274 imx_gpt_timecounter.tc_priv = sc; 275 tc_init(&imx_gpt_timecounter); 276 277 /* If this is the first unit, store the softc for use in DELAY. */ 278 if (device_get_unit(dev) == 0) 279 imx_gpt_sc = sc; 280 281 return (0); 282 } 283 284 static int 285 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 286 { 287 struct imx_gpt_softc *sc; 288 uint32_t ticks; 289 290 sc = (struct imx_gpt_softc *)et->et_priv; 291 292 if (period != 0) { 293 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 294 /* Set expected value */ 295 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 296 /* Enable compare register 2 Interrupt */ 297 sc->ir_reg |= GPT_IR_OF2; 298 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 299 return (0); 300 } else if (first != 0) { 301 /* Enable compare register 3 interrupt if not already on. */ 302 if ((sc->ir_reg & GPT_IR_OF3) == 0) { 303 sc->ir_reg |= GPT_IR_OF3; 304 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 305 } 306 ticks = ((uint32_t)et->et_frequency * first) >> 32; 307 /* Do not disturb, otherwise event will be lost */ 308 spinlock_enter(); 309 /* Set expected value */ 310 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 311 /* Now everybody can relax */ 312 spinlock_exit(); 313 return (0); 314 } 315 316 return (EINVAL); 317 } 318 319 static int 320 imx_gpt_timer_stop(struct eventtimer *et) 321 { 322 struct imx_gpt_softc *sc; 323 324 sc = (struct imx_gpt_softc *)et->et_priv; 325 326 /* Disable interrupts and clear any pending status. */ 327 sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3); 328 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 329 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3); 330 sc->sc_period = 0; 331 332 return (0); 333 } 334 335 static int 336 imx_gpt_intr(void *arg) 337 { 338 struct imx_gpt_softc *sc; 339 uint32_t status; 340 341 sc = (struct imx_gpt_softc *)arg; 342 343 status = READ4(sc, IMX_GPT_SR); 344 345 /* 346 * Clear interrupt status before invoking event callbacks. The callback 347 * often sets up a new one-shot timer event and if the interval is short 348 * enough it can fire before we get out of this function. If we cleared 349 * at the bottom we'd miss the interrupt and hang until the clock wraps. 350 */ 351 WRITE4(sc, IMX_GPT_SR, status); 352 353 /* Handle one-shot timer events. */ 354 if (status & GPT_IR_OF3) { 355 if (sc->et.et_active) { 356 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 357 } 358 } 359 360 /* Handle periodic timer events. */ 361 if (status & GPT_IR_OF2) { 362 if (sc->et.et_active) 363 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 364 if (sc->sc_period != 0) 365 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 366 sc->sc_period); 367 } 368 369 return (FILTER_HANDLED); 370 } 371 372 static u_int 373 imx_gpt_get_timecount(struct timecounter *tc) 374 { 375 struct imx_gpt_softc *sc; 376 377 sc = tc->tc_priv; 378 return (READ4(sc, IMX_GPT_CNT)); 379 } 380 381 static device_method_t imx_gpt_methods[] = { 382 DEVMETHOD(device_probe, imx_gpt_probe), 383 DEVMETHOD(device_attach, imx_gpt_attach), 384 385 DEVMETHOD_END 386 }; 387 388 static driver_t imx_gpt_driver = { 389 "imx_gpt", 390 imx_gpt_methods, 391 sizeof(struct imx_gpt_softc), 392 }; 393 394 static devclass_t imx_gpt_devclass; 395 396 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 397 0, BUS_PASS_TIMER); 398 399 void 400 DELAY(int usec) 401 { 402 uint64_t curcnt, endcnt, startcnt, ticks; 403 404 /* If the timer hardware is not accessible, just use a loop. */ 405 if (imx_gpt_sc == NULL) { 406 while (usec-- > 0) 407 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 408 cpufunc_nullop(); 409 return; 410 } 411 412 /* 413 * Calculate the tick count with 64-bit values so that it works for any 414 * clock frequency. Loop until the hardware count reaches start+ticks. 415 * If the 32-bit hardware count rolls over while we're looping, just 416 * manually do a carry into the high bits after each read; don't worry 417 * that doing this on each loop iteration is inefficient -- we're trying 418 * to waste time here. 419 */ 420 ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 421 curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 422 endcnt = startcnt + ticks; 423 while (curcnt < endcnt) { 424 curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 425 if (curcnt < startcnt) 426 curcnt += 1ULL << 32; 427 } 428 } 429