1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/timeet.h> 40 #include <sys/timetc.h> 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 #ifdef MULTIDELAY 44 #include <machine/machdep.h> /* For arm_set_delay */ 45 #endif 46 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <arm/freescale/imx/imx_ccmvar.h> 52 #include <arm/freescale/imx/imx_gptreg.h> 53 54 #define WRITE4(_sc, _r, _v) \ 55 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 56 #define READ4(_sc, _r) \ 57 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 58 #define SET4(_sc, _r, _m) \ 59 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 60 #define CLEAR4(_sc, _r, _m) \ 61 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 62 63 static u_int imx_gpt_get_timecount(struct timecounter *); 64 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 65 sbintime_t); 66 static int imx_gpt_timer_stop(struct eventtimer *); 67 68 static void imx_gpt_do_delay(int, void *); 69 70 static int imx_gpt_intr(void *); 71 static int imx_gpt_probe(device_t); 72 static int imx_gpt_attach(device_t); 73 74 static struct timecounter imx_gpt_timecounter = { 75 .tc_name = "iMXGPT", 76 .tc_get_timecount = imx_gpt_get_timecount, 77 .tc_counter_mask = ~0u, 78 .tc_frequency = 0, 79 .tc_quality = 1000, 80 }; 81 82 struct imx_gpt_softc { 83 device_t sc_dev; 84 struct resource * res[2]; 85 bus_space_tag_t sc_iot; 86 bus_space_handle_t sc_ioh; 87 void * sc_ih; /* interrupt handler */ 88 uint32_t sc_period; 89 uint32_t sc_clksrc; 90 uint32_t clkfreq; 91 uint32_t ir_reg; 92 struct eventtimer et; 93 }; 94 95 #ifndef MULTIDELAY 96 /* Global softc pointer for use in DELAY(). */ 97 static struct imx_gpt_softc *imx_gpt_sc; 98 99 /* 100 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 101 * at 792mhz. It will delay a bit too long on slower processors -- that's 102 * better than not delaying long enough. In practice this is unlikely to get 103 * used much since the clock driver is one of the first to start up, and once 104 * we're attached the delay loop switches to using the timer hardware. 105 */ 106 static const int imx_gpt_delay_count = 78; 107 #endif 108 109 /* Try to divide down an available fast clock to this frequency. */ 110 #define TARGET_FREQUENCY 1000000000 111 112 static struct resource_spec imx_gpt_spec[] = { 113 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 114 { SYS_RES_IRQ, 0, RF_ACTIVE }, 115 { -1, 0 } 116 }; 117 118 static struct ofw_compat_data compat_data[] = { 119 {"fsl,imx6dl-gpt", 1}, 120 {"fsl,imx6q-gpt", 1}, 121 {"fsl,imx53-gpt", 1}, 122 {"fsl,imx51-gpt", 1}, 123 {"fsl,imx31-gpt", 1}, 124 {"fsl,imx27-gpt", 1}, 125 {"fsl,imx25-gpt", 1}, 126 {NULL, 0} 127 }; 128 129 static int 130 imx_gpt_probe(device_t dev) 131 { 132 133 if (!ofw_bus_status_okay(dev)) 134 return (ENXIO); 135 136 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 137 device_set_desc(dev, "Freescale i.MX GPT timer"); 138 return (BUS_PROBE_DEFAULT); 139 } 140 141 return (ENXIO); 142 } 143 144 static int 145 imx_gpt_attach(device_t dev) 146 { 147 struct imx_gpt_softc *sc; 148 int ctlreg, err; 149 uint32_t basefreq, prescale, setup_ticks, t1, t2; 150 151 sc = device_get_softc(dev); 152 153 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 154 device_printf(dev, "could not allocate resources\n"); 155 return (ENXIO); 156 } 157 158 sc->sc_dev = dev; 159 sc->sc_iot = rman_get_bustag(sc->res[0]); 160 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 161 162 /* 163 * For now, just automatically choose a good clock for the hardware 164 * we're running on. Eventually we could allow selection from the fdt; 165 * the code in this driver will cope with any clock frequency. 166 */ 167 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 168 169 ctlreg = 0; 170 171 switch (sc->sc_clksrc) { 172 case GPT_CR_CLKSRC_32K: 173 basefreq = 32768; 174 break; 175 case GPT_CR_CLKSRC_IPG: 176 basefreq = imx_ccm_ipg_hz(); 177 break; 178 case GPT_CR_CLKSRC_IPG_HIGH: 179 basefreq = imx_ccm_ipg_hz() * 2; 180 break; 181 case GPT_CR_CLKSRC_24M: 182 ctlreg |= GPT_CR_24MEN; 183 basefreq = 24000000; 184 break; 185 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 186 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 187 default: 188 device_printf(dev, "Unsupported clock source '%d'\n", 189 sc->sc_clksrc); 190 return (EINVAL); 191 } 192 193 /* 194 * The following setup sequence is from the I.MX6 reference manual, 195 * "Selecting the clock source". First, disable the clock and 196 * interrupts. This also clears input and output mode bits and in 197 * general completes several of the early steps in the procedure. 198 */ 199 WRITE4(sc, IMX_GPT_CR, 0); 200 WRITE4(sc, IMX_GPT_IR, 0); 201 202 /* Choose the clock and the power-saving behaviors. */ 203 ctlreg |= 204 sc->sc_clksrc | /* Use selected clock */ 205 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 206 GPT_CR_STOPEN | /* Run in STOP mode */ 207 GPT_CR_DOZEEN | /* Run in DOZE mode */ 208 GPT_CR_WAITEN | /* Run in WAIT mode */ 209 GPT_CR_DBGEN; /* Run in DEBUG mode */ 210 WRITE4(sc, IMX_GPT_CR, ctlreg); 211 212 /* 213 * The datasheet says to do the software reset after choosing the clock 214 * source. It says nothing about needing to wait for the reset to 215 * complete, but the register description does document the fact that 216 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 217 * The reset also clears all registers except for a few of the bits in 218 * CR, but we'll rewrite all the CR bits when we start the counter. 219 */ 220 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 221 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 222 continue; 223 224 /* Set a prescaler value that gets us near the target frequency. */ 225 if (basefreq < TARGET_FREQUENCY) { 226 prescale = 0; 227 sc->clkfreq = basefreq; 228 } else { 229 prescale = basefreq / TARGET_FREQUENCY; 230 sc->clkfreq = basefreq / prescale; 231 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 232 } 233 WRITE4(sc, IMX_GPT_PR, prescale); 234 235 /* Clear the status register. */ 236 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 237 238 /* Start the counter. */ 239 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 240 241 if (bootverbose) 242 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 243 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 244 245 /* Setup the timer interrupt. */ 246 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 247 NULL, sc, &sc->sc_ih); 248 if (err != 0) { 249 bus_release_resources(dev, imx_gpt_spec, sc->res); 250 device_printf(dev, "Unable to setup the clock irq handler, " 251 "err = %d\n", err); 252 return (ENXIO); 253 } 254 255 /* 256 * Measure how many clock ticks it takes to setup a one-shot event (it's 257 * longer than you might think, due to wait states in accessing gpt 258 * registers). Scale up the result by a factor of 1.5 to be safe, 259 * and use that to set the minimum eventtimer period we can schedule. In 260 * the real world, the value works out to about 750ns on imx5 hardware. 261 */ 262 t1 = READ4(sc, IMX_GPT_CNT); 263 WRITE4(sc, IMX_GPT_OCR3, 0); 264 t2 = READ4(sc, IMX_GPT_CNT); 265 setup_ticks = ((t2 - t1 + 1) * 3) / 2; 266 267 /* Register as an eventtimer. */ 268 sc->et.et_name = "iMXGPT"; 269 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 270 sc->et.et_quality = 800; 271 sc->et.et_frequency = sc->clkfreq; 272 sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq; 273 sc->et.et_max_period = ((uint64_t)0xfffffffe << 32) / sc->clkfreq; 274 sc->et.et_start = imx_gpt_timer_start; 275 sc->et.et_stop = imx_gpt_timer_stop; 276 sc->et.et_priv = sc; 277 et_register(&sc->et); 278 279 /* Register as a timecounter. */ 280 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 281 imx_gpt_timecounter.tc_priv = sc; 282 tc_init(&imx_gpt_timecounter); 283 284 /* If this is the first unit, store the softc for use in DELAY. */ 285 if (device_get_unit(dev) == 0) { 286 #ifdef MULTIDELAY 287 arm_set_delay(imx_gpt_do_delay, sc); 288 #else 289 imx_gpt_sc = sc; 290 #endif 291 } 292 293 return (0); 294 } 295 296 static int 297 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 298 { 299 struct imx_gpt_softc *sc; 300 uint32_t ticks; 301 302 sc = (struct imx_gpt_softc *)et->et_priv; 303 304 if (period != 0) { 305 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 306 /* Set expected value */ 307 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 308 /* Enable compare register 2 Interrupt */ 309 sc->ir_reg |= GPT_IR_OF2; 310 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 311 return (0); 312 } else if (first != 0) { 313 /* Enable compare register 3 interrupt if not already on. */ 314 if ((sc->ir_reg & GPT_IR_OF3) == 0) { 315 sc->ir_reg |= GPT_IR_OF3; 316 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 317 } 318 ticks = ((uint32_t)et->et_frequency * first) >> 32; 319 /* Do not disturb, otherwise event will be lost */ 320 spinlock_enter(); 321 /* Set expected value */ 322 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 323 /* Now everybody can relax */ 324 spinlock_exit(); 325 return (0); 326 } 327 328 return (EINVAL); 329 } 330 331 static int 332 imx_gpt_timer_stop(struct eventtimer *et) 333 { 334 struct imx_gpt_softc *sc; 335 336 sc = (struct imx_gpt_softc *)et->et_priv; 337 338 /* Disable interrupts and clear any pending status. */ 339 sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3); 340 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 341 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3); 342 sc->sc_period = 0; 343 344 return (0); 345 } 346 347 static int 348 imx_gpt_intr(void *arg) 349 { 350 struct imx_gpt_softc *sc; 351 uint32_t status; 352 353 sc = (struct imx_gpt_softc *)arg; 354 355 status = READ4(sc, IMX_GPT_SR); 356 357 /* 358 * Clear interrupt status before invoking event callbacks. The callback 359 * often sets up a new one-shot timer event and if the interval is short 360 * enough it can fire before we get out of this function. If we cleared 361 * at the bottom we'd miss the interrupt and hang until the clock wraps. 362 */ 363 WRITE4(sc, IMX_GPT_SR, status); 364 365 /* Handle one-shot timer events. */ 366 if (status & GPT_IR_OF3) { 367 if (sc->et.et_active) { 368 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 369 } 370 } 371 372 /* Handle periodic timer events. */ 373 if (status & GPT_IR_OF2) { 374 if (sc->et.et_active) 375 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 376 if (sc->sc_period != 0) 377 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 378 sc->sc_period); 379 } 380 381 return (FILTER_HANDLED); 382 } 383 384 static u_int 385 imx_gpt_get_timecount(struct timecounter *tc) 386 { 387 struct imx_gpt_softc *sc; 388 389 sc = tc->tc_priv; 390 return (READ4(sc, IMX_GPT_CNT)); 391 } 392 393 static device_method_t imx_gpt_methods[] = { 394 DEVMETHOD(device_probe, imx_gpt_probe), 395 DEVMETHOD(device_attach, imx_gpt_attach), 396 397 DEVMETHOD_END 398 }; 399 400 static driver_t imx_gpt_driver = { 401 "imx_gpt", 402 imx_gpt_methods, 403 sizeof(struct imx_gpt_softc), 404 }; 405 406 static devclass_t imx_gpt_devclass; 407 408 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 409 0, BUS_PASS_TIMER); 410 411 static void 412 imx_gpt_do_delay(int usec, void *arg) 413 { 414 struct imx_gpt_softc *sc = arg; 415 uint64_t curcnt, endcnt, startcnt, ticks; 416 417 /* 418 * Calculate the tick count with 64-bit values so that it works for any 419 * clock frequency. Loop until the hardware count reaches start+ticks. 420 * If the 32-bit hardware count rolls over while we're looping, just 421 * manually do a carry into the high bits after each read; don't worry 422 * that doing this on each loop iteration is inefficient -- we're trying 423 * to waste time here. 424 */ 425 ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000; 426 curcnt = startcnt = READ4(sc, IMX_GPT_CNT); 427 endcnt = startcnt + ticks; 428 while (curcnt < endcnt) { 429 curcnt = READ4(sc, IMX_GPT_CNT); 430 if (curcnt < startcnt) 431 curcnt += 1ULL << 32; 432 } 433 } 434 435 #ifndef MULTIDELAY 436 void 437 DELAY(int usec) 438 { 439 uint64_t ticks; 440 441 /* If the timer hardware is not accessible, just use a loop. */ 442 if (imx_gpt_sc == NULL) { 443 while (usec-- > 0) 444 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 445 cpufunc_nullop(); 446 return; 447 } else 448 imx_gpt_do_delay(usec, imx_gpt_sc); 449 450 } 451 #endif 452