1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012, 2013 The FreeBSD Foundation 5 * 6 * This software was developed by Oleksandr Rybalko under sponsorship 7 * from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 #include <sys/timeet.h> 39 #include <sys/timetc.h> 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 #include <machine/machdep.h> /* For arm_set_delay */ 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <arm/freescale/imx/imx_ccmvar.h> 49 #include <arm/freescale/imx/imx_gptreg.h> 50 51 #define WRITE4(_sc, _r, _v) \ 52 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 53 #define READ4(_sc, _r) \ 54 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 55 #define SET4(_sc, _r, _m) \ 56 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 57 #define CLEAR4(_sc, _r, _m) \ 58 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 59 60 static u_int imx_gpt_get_timecount(struct timecounter *); 61 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 62 sbintime_t); 63 static int imx_gpt_timer_stop(struct eventtimer *); 64 65 static void imx_gpt_do_delay(int, void *); 66 67 static int imx_gpt_intr(void *); 68 static int imx_gpt_probe(device_t); 69 static int imx_gpt_attach(device_t); 70 71 static struct timecounter imx_gpt_timecounter = { 72 .tc_name = "iMXGPT", 73 .tc_get_timecount = imx_gpt_get_timecount, 74 .tc_counter_mask = ~0u, 75 .tc_frequency = 0, 76 .tc_quality = 1000, 77 }; 78 79 struct imx_gpt_softc { 80 device_t sc_dev; 81 struct resource * res[2]; 82 bus_space_tag_t sc_iot; 83 bus_space_handle_t sc_ioh; 84 void * sc_ih; /* interrupt handler */ 85 uint32_t sc_period; 86 uint32_t sc_clksrc; 87 uint32_t clkfreq; 88 uint32_t ir_reg; 89 struct eventtimer et; 90 }; 91 92 /* Try to divide down an available fast clock to this frequency. */ 93 #define TARGET_FREQUENCY 1000000000 94 95 static struct resource_spec imx_gpt_spec[] = { 96 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 97 { SYS_RES_IRQ, 0, RF_ACTIVE }, 98 { -1, 0 } 99 }; 100 101 static struct ofw_compat_data compat_data[] = { 102 {"fsl,imx6dl-gpt", 1}, 103 {"fsl,imx6q-gpt", 1}, 104 {"fsl,imx6ul-gpt", 1}, 105 {"fsl,imx53-gpt", 1}, 106 {"fsl,imx51-gpt", 1}, 107 {"fsl,imx31-gpt", 1}, 108 {"fsl,imx27-gpt", 1}, 109 {"fsl,imx25-gpt", 1}, 110 {NULL, 0} 111 }; 112 113 static int 114 imx_gpt_probe(device_t dev) 115 { 116 117 if (!ofw_bus_status_okay(dev)) 118 return (ENXIO); 119 120 /* 121 * We only support a single unit, because the only thing this driver 122 * does with the complex timer hardware is supply the system 123 * timecounter and eventtimer. There is nothing useful we can do with 124 * the additional device instances that exist in some chips. 125 */ 126 if (device_get_unit(dev) > 0) 127 return (ENXIO); 128 129 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 130 device_set_desc(dev, "Freescale i.MX GPT timer"); 131 return (BUS_PROBE_DEFAULT); 132 } 133 134 return (ENXIO); 135 } 136 137 static int 138 imx_gpt_attach(device_t dev) 139 { 140 struct imx_gpt_softc *sc; 141 int ctlreg, err; 142 uint32_t basefreq, prescale, setup_ticks, t1, t2; 143 144 sc = device_get_softc(dev); 145 146 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 147 device_printf(dev, "could not allocate resources\n"); 148 return (ENXIO); 149 } 150 151 sc->sc_dev = dev; 152 sc->sc_iot = rman_get_bustag(sc->res[0]); 153 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 154 155 /* 156 * For now, just automatically choose a good clock for the hardware 157 * we're running on. Eventually we could allow selection from the fdt; 158 * the code in this driver will cope with any clock frequency. 159 */ 160 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 161 162 ctlreg = 0; 163 164 switch (sc->sc_clksrc) { 165 case GPT_CR_CLKSRC_32K: 166 basefreq = 32768; 167 break; 168 case GPT_CR_CLKSRC_IPG: 169 basefreq = imx_ccm_ipg_hz(); 170 break; 171 case GPT_CR_CLKSRC_IPG_HIGH: 172 basefreq = imx_ccm_ipg_hz() * 2; 173 break; 174 case GPT_CR_CLKSRC_24M: 175 ctlreg |= GPT_CR_24MEN; 176 basefreq = 24000000; 177 break; 178 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 179 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 180 default: 181 device_printf(dev, "Unsupported clock source '%d'\n", 182 sc->sc_clksrc); 183 return (EINVAL); 184 } 185 186 /* 187 * The following setup sequence is from the I.MX6 reference manual, 188 * "Selecting the clock source". First, disable the clock and 189 * interrupts. This also clears input and output mode bits and in 190 * general completes several of the early steps in the procedure. 191 */ 192 WRITE4(sc, IMX_GPT_CR, 0); 193 WRITE4(sc, IMX_GPT_IR, 0); 194 195 /* Choose the clock and the power-saving behaviors. */ 196 ctlreg |= 197 sc->sc_clksrc | /* Use selected clock */ 198 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 199 GPT_CR_STOPEN | /* Run in STOP mode */ 200 GPT_CR_DOZEEN | /* Run in DOZE mode */ 201 GPT_CR_WAITEN | /* Run in WAIT mode */ 202 GPT_CR_DBGEN; /* Run in DEBUG mode */ 203 WRITE4(sc, IMX_GPT_CR, ctlreg); 204 205 /* 206 * The datasheet says to do the software reset after choosing the clock 207 * source. It says nothing about needing to wait for the reset to 208 * complete, but the register description does document the fact that 209 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 210 * The reset also clears all registers except for a few of the bits in 211 * CR, but we'll rewrite all the CR bits when we start the counter. 212 */ 213 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 214 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 215 continue; 216 217 /* Set a prescaler value that gets us near the target frequency. */ 218 if (basefreq < TARGET_FREQUENCY) { 219 prescale = 0; 220 sc->clkfreq = basefreq; 221 } else { 222 prescale = basefreq / TARGET_FREQUENCY; 223 sc->clkfreq = basefreq / prescale; 224 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 225 } 226 WRITE4(sc, IMX_GPT_PR, prescale); 227 228 /* Clear the status register. */ 229 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 230 231 /* Start the counter. */ 232 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 233 234 if (bootverbose) 235 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 236 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 237 238 /* Setup the timer interrupt. */ 239 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 240 NULL, sc, &sc->sc_ih); 241 if (err != 0) { 242 bus_release_resources(dev, imx_gpt_spec, sc->res); 243 device_printf(dev, "Unable to setup the clock irq handler, " 244 "err = %d\n", err); 245 return (ENXIO); 246 } 247 248 /* 249 * Measure how many clock ticks it takes to setup a one-shot event (it's 250 * longer than you might think, due to wait states in accessing gpt 251 * registers). Scale up the result by a factor of 1.5 to be safe, 252 * and use that to set the minimum eventtimer period we can schedule. In 253 * the real world, the value works out to about 750ns on imx5 hardware. 254 */ 255 t1 = READ4(sc, IMX_GPT_CNT); 256 WRITE4(sc, IMX_GPT_OCR3, 0); 257 t2 = READ4(sc, IMX_GPT_CNT); 258 setup_ticks = ((t2 - t1 + 1) * 3) / 2; 259 260 /* Register as an eventtimer. */ 261 sc->et.et_name = "iMXGPT"; 262 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 263 sc->et.et_quality = 800; 264 sc->et.et_frequency = sc->clkfreq; 265 sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq; 266 sc->et.et_max_period = ((uint64_t)0xfffffffe << 32) / sc->clkfreq; 267 sc->et.et_start = imx_gpt_timer_start; 268 sc->et.et_stop = imx_gpt_timer_stop; 269 sc->et.et_priv = sc; 270 et_register(&sc->et); 271 272 /* Register as a timecounter. */ 273 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 274 imx_gpt_timecounter.tc_priv = sc; 275 tc_init(&imx_gpt_timecounter); 276 277 /* If this is the first unit, store the softc for use in DELAY. */ 278 if (device_get_unit(dev) == 0) { 279 arm_set_delay(imx_gpt_do_delay, sc); 280 } 281 282 return (0); 283 } 284 285 static int 286 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 287 { 288 struct imx_gpt_softc *sc; 289 uint32_t ticks; 290 291 sc = (struct imx_gpt_softc *)et->et_priv; 292 293 if (period != 0) { 294 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 295 /* Set expected value */ 296 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 297 /* Enable compare register 2 Interrupt */ 298 sc->ir_reg |= GPT_IR_OF2; 299 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 300 return (0); 301 } else if (first != 0) { 302 /* Enable compare register 3 interrupt if not already on. */ 303 if ((sc->ir_reg & GPT_IR_OF3) == 0) { 304 sc->ir_reg |= GPT_IR_OF3; 305 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 306 } 307 ticks = ((uint32_t)et->et_frequency * first) >> 32; 308 /* Do not disturb, otherwise event will be lost */ 309 spinlock_enter(); 310 /* Set expected value */ 311 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 312 /* Now everybody can relax */ 313 spinlock_exit(); 314 return (0); 315 } 316 317 return (EINVAL); 318 } 319 320 static int 321 imx_gpt_timer_stop(struct eventtimer *et) 322 { 323 struct imx_gpt_softc *sc; 324 325 sc = (struct imx_gpt_softc *)et->et_priv; 326 327 /* Disable interrupts and clear any pending status. */ 328 sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3); 329 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 330 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3); 331 sc->sc_period = 0; 332 333 return (0); 334 } 335 336 static int 337 imx_gpt_intr(void *arg) 338 { 339 struct imx_gpt_softc *sc; 340 uint32_t status; 341 342 sc = (struct imx_gpt_softc *)arg; 343 344 status = READ4(sc, IMX_GPT_SR); 345 346 /* 347 * Clear interrupt status before invoking event callbacks. The callback 348 * often sets up a new one-shot timer event and if the interval is short 349 * enough it can fire before we get out of this function. If we cleared 350 * at the bottom we'd miss the interrupt and hang until the clock wraps. 351 */ 352 WRITE4(sc, IMX_GPT_SR, status); 353 354 /* Handle one-shot timer events. */ 355 if (status & GPT_IR_OF3) { 356 if (sc->et.et_active) { 357 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 358 } 359 } 360 361 /* Handle periodic timer events. */ 362 if (status & GPT_IR_OF2) { 363 if (sc->et.et_active) 364 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 365 if (sc->sc_period != 0) 366 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 367 sc->sc_period); 368 } 369 370 return (FILTER_HANDLED); 371 } 372 373 static u_int 374 imx_gpt_get_timecount(struct timecounter *tc) 375 { 376 struct imx_gpt_softc *sc; 377 378 sc = tc->tc_priv; 379 return (READ4(sc, IMX_GPT_CNT)); 380 } 381 382 static device_method_t imx_gpt_methods[] = { 383 DEVMETHOD(device_probe, imx_gpt_probe), 384 DEVMETHOD(device_attach, imx_gpt_attach), 385 386 DEVMETHOD_END 387 }; 388 389 static driver_t imx_gpt_driver = { 390 "imx_gpt", 391 imx_gpt_methods, 392 sizeof(struct imx_gpt_softc), 393 }; 394 395 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, 0, 0, BUS_PASS_TIMER); 396 397 static void 398 imx_gpt_do_delay(int usec, void *arg) 399 { 400 struct imx_gpt_softc *sc = arg; 401 uint64_t curcnt, endcnt, startcnt, ticks; 402 403 /* 404 * Calculate the tick count with 64-bit values so that it works for any 405 * clock frequency. Loop until the hardware count reaches start+ticks. 406 * If the 32-bit hardware count rolls over while we're looping, just 407 * manually do a carry into the high bits after each read; don't worry 408 * that doing this on each loop iteration is inefficient -- we're trying 409 * to waste time here. 410 */ 411 ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000; 412 curcnt = startcnt = READ4(sc, IMX_GPT_CNT); 413 endcnt = startcnt + ticks; 414 while (curcnt < endcnt) { 415 curcnt = READ4(sc, IMX_GPT_CNT); 416 if (curcnt < startcnt) 417 curcnt += 1ULL << 32; 418 } 419 } 420