1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/timeet.h> 40 #include <sys/timetc.h> 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 #include <machine/machdep.h> /* For arm_set_delay */ 44 45 #include <dev/ofw/openfirm.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/freescale/imx/imx_ccmvar.h> 50 #include <arm/freescale/imx/imx_gptreg.h> 51 52 #define WRITE4(_sc, _r, _v) \ 53 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 54 #define READ4(_sc, _r) \ 55 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 56 #define SET4(_sc, _r, _m) \ 57 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 58 #define CLEAR4(_sc, _r, _m) \ 59 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 60 61 static u_int imx_gpt_get_timecount(struct timecounter *); 62 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 63 sbintime_t); 64 static int imx_gpt_timer_stop(struct eventtimer *); 65 66 static void imx_gpt_do_delay(int, void *); 67 68 static int imx_gpt_intr(void *); 69 static int imx_gpt_probe(device_t); 70 static int imx_gpt_attach(device_t); 71 72 static struct timecounter imx_gpt_timecounter = { 73 .tc_name = "iMXGPT", 74 .tc_get_timecount = imx_gpt_get_timecount, 75 .tc_counter_mask = ~0u, 76 .tc_frequency = 0, 77 .tc_quality = 1000, 78 }; 79 80 struct imx_gpt_softc { 81 device_t sc_dev; 82 struct resource * res[2]; 83 bus_space_tag_t sc_iot; 84 bus_space_handle_t sc_ioh; 85 void * sc_ih; /* interrupt handler */ 86 uint32_t sc_period; 87 uint32_t sc_clksrc; 88 uint32_t clkfreq; 89 uint32_t ir_reg; 90 struct eventtimer et; 91 }; 92 93 /* Try to divide down an available fast clock to this frequency. */ 94 #define TARGET_FREQUENCY 1000000000 95 96 static struct resource_spec imx_gpt_spec[] = { 97 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 98 { SYS_RES_IRQ, 0, RF_ACTIVE }, 99 { -1, 0 } 100 }; 101 102 static struct ofw_compat_data compat_data[] = { 103 {"fsl,imx6dl-gpt", 1}, 104 {"fsl,imx6q-gpt", 1}, 105 {"fsl,imx6ul-gpt", 1}, 106 {"fsl,imx53-gpt", 1}, 107 {"fsl,imx51-gpt", 1}, 108 {"fsl,imx31-gpt", 1}, 109 {"fsl,imx27-gpt", 1}, 110 {"fsl,imx25-gpt", 1}, 111 {NULL, 0} 112 }; 113 114 static int 115 imx_gpt_probe(device_t dev) 116 { 117 118 if (!ofw_bus_status_okay(dev)) 119 return (ENXIO); 120 121 /* 122 * We only support a single unit, because the only thing this driver 123 * does with the complex timer hardware is supply the system 124 * timecounter and eventtimer. There is nothing useful we can do with 125 * the additional device instances that exist in some chips. 126 */ 127 if (device_get_unit(dev) > 0) 128 return (ENXIO); 129 130 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 131 device_set_desc(dev, "Freescale i.MX GPT timer"); 132 return (BUS_PROBE_DEFAULT); 133 } 134 135 return (ENXIO); 136 } 137 138 static int 139 imx_gpt_attach(device_t dev) 140 { 141 struct imx_gpt_softc *sc; 142 int ctlreg, err; 143 uint32_t basefreq, prescale, setup_ticks, t1, t2; 144 145 sc = device_get_softc(dev); 146 147 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 148 device_printf(dev, "could not allocate resources\n"); 149 return (ENXIO); 150 } 151 152 sc->sc_dev = dev; 153 sc->sc_iot = rman_get_bustag(sc->res[0]); 154 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 155 156 /* 157 * For now, just automatically choose a good clock for the hardware 158 * we're running on. Eventually we could allow selection from the fdt; 159 * the code in this driver will cope with any clock frequency. 160 */ 161 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 162 163 ctlreg = 0; 164 165 switch (sc->sc_clksrc) { 166 case GPT_CR_CLKSRC_32K: 167 basefreq = 32768; 168 break; 169 case GPT_CR_CLKSRC_IPG: 170 basefreq = imx_ccm_ipg_hz(); 171 break; 172 case GPT_CR_CLKSRC_IPG_HIGH: 173 basefreq = imx_ccm_ipg_hz() * 2; 174 break; 175 case GPT_CR_CLKSRC_24M: 176 ctlreg |= GPT_CR_24MEN; 177 basefreq = 24000000; 178 break; 179 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 180 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 181 default: 182 device_printf(dev, "Unsupported clock source '%d'\n", 183 sc->sc_clksrc); 184 return (EINVAL); 185 } 186 187 /* 188 * The following setup sequence is from the I.MX6 reference manual, 189 * "Selecting the clock source". First, disable the clock and 190 * interrupts. This also clears input and output mode bits and in 191 * general completes several of the early steps in the procedure. 192 */ 193 WRITE4(sc, IMX_GPT_CR, 0); 194 WRITE4(sc, IMX_GPT_IR, 0); 195 196 /* Choose the clock and the power-saving behaviors. */ 197 ctlreg |= 198 sc->sc_clksrc | /* Use selected clock */ 199 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 200 GPT_CR_STOPEN | /* Run in STOP mode */ 201 GPT_CR_DOZEEN | /* Run in DOZE mode */ 202 GPT_CR_WAITEN | /* Run in WAIT mode */ 203 GPT_CR_DBGEN; /* Run in DEBUG mode */ 204 WRITE4(sc, IMX_GPT_CR, ctlreg); 205 206 /* 207 * The datasheet says to do the software reset after choosing the clock 208 * source. It says nothing about needing to wait for the reset to 209 * complete, but the register description does document the fact that 210 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 211 * The reset also clears all registers except for a few of the bits in 212 * CR, but we'll rewrite all the CR bits when we start the counter. 213 */ 214 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 215 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 216 continue; 217 218 /* Set a prescaler value that gets us near the target frequency. */ 219 if (basefreq < TARGET_FREQUENCY) { 220 prescale = 0; 221 sc->clkfreq = basefreq; 222 } else { 223 prescale = basefreq / TARGET_FREQUENCY; 224 sc->clkfreq = basefreq / prescale; 225 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 226 } 227 WRITE4(sc, IMX_GPT_PR, prescale); 228 229 /* Clear the status register. */ 230 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 231 232 /* Start the counter. */ 233 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 234 235 if (bootverbose) 236 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 237 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 238 239 /* Setup the timer interrupt. */ 240 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 241 NULL, sc, &sc->sc_ih); 242 if (err != 0) { 243 bus_release_resources(dev, imx_gpt_spec, sc->res); 244 device_printf(dev, "Unable to setup the clock irq handler, " 245 "err = %d\n", err); 246 return (ENXIO); 247 } 248 249 /* 250 * Measure how many clock ticks it takes to setup a one-shot event (it's 251 * longer than you might think, due to wait states in accessing gpt 252 * registers). Scale up the result by a factor of 1.5 to be safe, 253 * and use that to set the minimum eventtimer period we can schedule. In 254 * the real world, the value works out to about 750ns on imx5 hardware. 255 */ 256 t1 = READ4(sc, IMX_GPT_CNT); 257 WRITE4(sc, IMX_GPT_OCR3, 0); 258 t2 = READ4(sc, IMX_GPT_CNT); 259 setup_ticks = ((t2 - t1 + 1) * 3) / 2; 260 261 /* Register as an eventtimer. */ 262 sc->et.et_name = "iMXGPT"; 263 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 264 sc->et.et_quality = 800; 265 sc->et.et_frequency = sc->clkfreq; 266 sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq; 267 sc->et.et_max_period = ((uint64_t)0xfffffffe << 32) / sc->clkfreq; 268 sc->et.et_start = imx_gpt_timer_start; 269 sc->et.et_stop = imx_gpt_timer_stop; 270 sc->et.et_priv = sc; 271 et_register(&sc->et); 272 273 /* Register as a timecounter. */ 274 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 275 imx_gpt_timecounter.tc_priv = sc; 276 tc_init(&imx_gpt_timecounter); 277 278 /* If this is the first unit, store the softc for use in DELAY. */ 279 if (device_get_unit(dev) == 0) { 280 arm_set_delay(imx_gpt_do_delay, sc); 281 } 282 283 return (0); 284 } 285 286 static int 287 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 288 { 289 struct imx_gpt_softc *sc; 290 uint32_t ticks; 291 292 sc = (struct imx_gpt_softc *)et->et_priv; 293 294 if (period != 0) { 295 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 296 /* Set expected value */ 297 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 298 /* Enable compare register 2 Interrupt */ 299 sc->ir_reg |= GPT_IR_OF2; 300 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 301 return (0); 302 } else if (first != 0) { 303 /* Enable compare register 3 interrupt if not already on. */ 304 if ((sc->ir_reg & GPT_IR_OF3) == 0) { 305 sc->ir_reg |= GPT_IR_OF3; 306 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 307 } 308 ticks = ((uint32_t)et->et_frequency * first) >> 32; 309 /* Do not disturb, otherwise event will be lost */ 310 spinlock_enter(); 311 /* Set expected value */ 312 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 313 /* Now everybody can relax */ 314 spinlock_exit(); 315 return (0); 316 } 317 318 return (EINVAL); 319 } 320 321 static int 322 imx_gpt_timer_stop(struct eventtimer *et) 323 { 324 struct imx_gpt_softc *sc; 325 326 sc = (struct imx_gpt_softc *)et->et_priv; 327 328 /* Disable interrupts and clear any pending status. */ 329 sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3); 330 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); 331 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3); 332 sc->sc_period = 0; 333 334 return (0); 335 } 336 337 static int 338 imx_gpt_intr(void *arg) 339 { 340 struct imx_gpt_softc *sc; 341 uint32_t status; 342 343 sc = (struct imx_gpt_softc *)arg; 344 345 status = READ4(sc, IMX_GPT_SR); 346 347 /* 348 * Clear interrupt status before invoking event callbacks. The callback 349 * often sets up a new one-shot timer event and if the interval is short 350 * enough it can fire before we get out of this function. If we cleared 351 * at the bottom we'd miss the interrupt and hang until the clock wraps. 352 */ 353 WRITE4(sc, IMX_GPT_SR, status); 354 355 /* Handle one-shot timer events. */ 356 if (status & GPT_IR_OF3) { 357 if (sc->et.et_active) { 358 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 359 } 360 } 361 362 /* Handle periodic timer events. */ 363 if (status & GPT_IR_OF2) { 364 if (sc->et.et_active) 365 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 366 if (sc->sc_period != 0) 367 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 368 sc->sc_period); 369 } 370 371 return (FILTER_HANDLED); 372 } 373 374 static u_int 375 imx_gpt_get_timecount(struct timecounter *tc) 376 { 377 struct imx_gpt_softc *sc; 378 379 sc = tc->tc_priv; 380 return (READ4(sc, IMX_GPT_CNT)); 381 } 382 383 static device_method_t imx_gpt_methods[] = { 384 DEVMETHOD(device_probe, imx_gpt_probe), 385 DEVMETHOD(device_attach, imx_gpt_attach), 386 387 DEVMETHOD_END 388 }; 389 390 static driver_t imx_gpt_driver = { 391 "imx_gpt", 392 imx_gpt_methods, 393 sizeof(struct imx_gpt_softc), 394 }; 395 396 static devclass_t imx_gpt_devclass; 397 398 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 399 0, BUS_PASS_TIMER); 400 401 static void 402 imx_gpt_do_delay(int usec, void *arg) 403 { 404 struct imx_gpt_softc *sc = arg; 405 uint64_t curcnt, endcnt, startcnt, ticks; 406 407 /* 408 * Calculate the tick count with 64-bit values so that it works for any 409 * clock frequency. Loop until the hardware count reaches start+ticks. 410 * If the 32-bit hardware count rolls over while we're looping, just 411 * manually do a carry into the high bits after each read; don't worry 412 * that doing this on each loop iteration is inefficient -- we're trying 413 * to waste time here. 414 */ 415 ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000; 416 curcnt = startcnt = READ4(sc, IMX_GPT_CNT); 417 endcnt = startcnt + ticks; 418 while (curcnt < endcnt) { 419 curcnt = READ4(sc, IMX_GPT_CNT); 420 if (curcnt < startcnt) 421 curcnt += 1ULL << 32; 422 } 423 } 424