1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/malloc.h> 39 #include <sys/rman.h> 40 #include <sys/timeet.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 #include <machine/intr.h> 46 47 #include <machine/fdt.h> 48 #include <dev/fdt/fdt_common.h> 49 #include <dev/ofw/openfirm.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <arm/freescale/imx/imx_gptvar.h> 54 #include <arm/freescale/imx/imx_gptreg.h> 55 56 #include <sys/kdb.h> 57 #include <arm/freescale/imx/imx_ccmvar.h> 58 59 #define WRITE4(_sc, _r, _v) \ 60 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 61 #define READ4(_sc, _r) \ 62 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 63 #define SET4(_sc, _r, _m) \ 64 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 65 #define CLEAR4(_sc, _r, _m) \ 66 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 67 68 static u_int imx_gpt_get_timecount(struct timecounter *); 69 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 70 sbintime_t); 71 static int imx_gpt_timer_stop(struct eventtimer *); 72 73 static int imx_gpt_intr(void *); 74 static int imx_gpt_probe(device_t); 75 static int imx_gpt_attach(device_t); 76 77 static struct timecounter imx_gpt_timecounter = { 78 .tc_name = "iMXGPT", 79 .tc_get_timecount = imx_gpt_get_timecount, 80 .tc_counter_mask = ~0u, 81 .tc_frequency = 0, 82 .tc_quality = 1000, 83 }; 84 85 /* Global softc pointer for use in DELAY(). */ 86 struct imx_gpt_softc *imx_gpt_sc = NULL; 87 88 /* 89 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 90 * at 792mhz. It will delay a bit too long on slower processors -- that's 91 * better than not delaying long enough. In practice this is unlikely to get 92 * used much since the clock driver is one of the first to start up, and once 93 * we're attached the delay loop switches to using the timer hardware. 94 */ 95 static const int imx_gpt_delay_count = 78; 96 97 /* Try to divide down an available fast clock to this frequency. */ 98 #define TARGET_FREQUENCY 1000000000 99 100 /* Don't try to set an event timer period smaller than this. */ 101 #define MIN_ET_PERIOD 10LLU 102 103 104 static struct resource_spec imx_gpt_spec[] = { 105 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 106 { SYS_RES_IRQ, 0, RF_ACTIVE }, 107 { -1, 0 } 108 }; 109 110 static struct ofw_compat_data compat_data[] = { 111 {"fsl,imx6q-gpt", 1}, 112 {"fsl,imx53-gpt", 1}, 113 {"fsl,imx51-gpt", 1}, 114 {"fsl,imx31-gpt", 1}, 115 {"fsl,imx27-gpt", 1}, 116 {"fsl,imx25-gpt", 1}, 117 {NULL, 0} 118 }; 119 120 static int 121 imx_gpt_probe(device_t dev) 122 { 123 124 if (!ofw_bus_status_okay(dev)) 125 return (ENXIO); 126 127 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 128 device_set_desc(dev, "Freescale i.MX GPT timer"); 129 return (BUS_PROBE_DEFAULT); 130 } 131 132 return (ENXIO); 133 } 134 135 static int 136 imx_gpt_attach(device_t dev) 137 { 138 struct imx_gpt_softc *sc; 139 int ctlreg, err; 140 uint32_t basefreq, prescale; 141 142 sc = device_get_softc(dev); 143 144 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 145 device_printf(dev, "could not allocate resources\n"); 146 return (ENXIO); 147 } 148 149 sc->sc_dev = dev; 150 sc->sc_iot = rman_get_bustag(sc->res[0]); 151 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 152 153 /* 154 * For now, just automatically choose a good clock for the hardware 155 * we're running on. Eventually we could allow selection from the fdt; 156 * the code in this driver will cope with any clock frequency. 157 */ 158 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 159 160 ctlreg = 0; 161 162 switch (sc->sc_clksrc) { 163 case GPT_CR_CLKSRC_32K: 164 basefreq = 32768; 165 break; 166 case GPT_CR_CLKSRC_IPG: 167 basefreq = imx_ccm_ipg_hz(); 168 break; 169 case GPT_CR_CLKSRC_IPG_HIGH: 170 basefreq = imx_ccm_ipg_hz() * 2; 171 break; 172 case GPT_CR_CLKSRC_24M: 173 ctlreg |= GPT_CR_24MEN; 174 basefreq = 24000000; 175 break; 176 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 177 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 178 default: 179 device_printf(dev, "Unsupported clock source '%d'\n", 180 sc->sc_clksrc); 181 return (EINVAL); 182 } 183 184 /* 185 * The following setup sequence is from the I.MX6 reference manual, 186 * "Selecting the clock source". First, disable the clock and 187 * interrupts. This also clears input and output mode bits and in 188 * general completes several of the early steps in the procedure. 189 */ 190 WRITE4(sc, IMX_GPT_CR, 0); 191 WRITE4(sc, IMX_GPT_IR, 0); 192 193 /* Choose the clock and the power-saving behaviors. */ 194 ctlreg |= 195 sc->sc_clksrc | /* Use selected clock */ 196 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 197 GPT_CR_STOPEN | /* Run in STOP mode */ 198 GPT_CR_DOZEEN | /* Run in DOZE mode */ 199 GPT_CR_WAITEN | /* Run in WAIT mode */ 200 GPT_CR_DBGEN; /* Run in DEBUG mode */ 201 WRITE4(sc, IMX_GPT_CR, ctlreg); 202 203 /* 204 * The datasheet says to do the software reset after choosing the clock 205 * source. It says nothing about needing to wait for the reset to 206 * complete, but the register description does document the fact that 207 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 208 * The reset also clears all registers except for a few of the bits in 209 * CR, but we'll rewrite all the CR bits when we start the counter. 210 */ 211 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 212 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 213 continue; 214 215 /* Set a prescaler value that gets us near the target frequency. */ 216 if (basefreq < TARGET_FREQUENCY) { 217 prescale = 0; 218 sc->clkfreq = basefreq; 219 } else { 220 prescale = basefreq / TARGET_FREQUENCY; 221 sc->clkfreq = basefreq / prescale; 222 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 223 } 224 WRITE4(sc, IMX_GPT_PR, prescale); 225 226 /* Clear the status register. */ 227 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 228 229 /* Start the counter. */ 230 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 231 232 if (bootverbose) 233 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 234 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 235 236 /* Setup the timer interrupt. */ 237 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 238 NULL, sc, &sc->sc_ih); 239 if (err != 0) { 240 bus_release_resources(dev, imx_gpt_spec, sc->res); 241 device_printf(dev, "Unable to setup the clock irq handler, " 242 "err = %d\n", err); 243 return (ENXIO); 244 } 245 246 /* Register as an eventtimer. */ 247 sc->et.et_name = "iMXGPT"; 248 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 249 sc->et.et_quality = 800; 250 sc->et.et_frequency = sc->clkfreq; 251 sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 252 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 253 sc->et.et_start = imx_gpt_timer_start; 254 sc->et.et_stop = imx_gpt_timer_stop; 255 sc->et.et_priv = sc; 256 et_register(&sc->et); 257 258 /* Register as a timecounter. */ 259 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 260 tc_init(&imx_gpt_timecounter); 261 262 /* If this is the first unit, store the softc for use in DELAY. */ 263 if (device_get_unit(dev) == 0) 264 imx_gpt_sc = sc; 265 266 return (0); 267 } 268 269 static int 270 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 271 { 272 struct imx_gpt_softc *sc; 273 uint32_t ticks; 274 275 sc = (struct imx_gpt_softc *)et->et_priv; 276 277 if (period != 0) { 278 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 279 /* Set expected value */ 280 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 281 /* Enable compare register 2 Interrupt */ 282 SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 283 return (0); 284 } else if (first != 0) { 285 ticks = ((uint32_t)et->et_frequency * first) >> 32; 286 /* Do not disturb, otherwise event will be lost */ 287 spinlock_enter(); 288 /* Set expected value */ 289 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 290 /* Enable compare register 1 Interrupt */ 291 SET4(sc, IMX_GPT_IR, GPT_IR_OF3); 292 /* Now everybody can relax */ 293 spinlock_exit(); 294 return (0); 295 } 296 297 return (EINVAL); 298 } 299 300 static int 301 imx_gpt_timer_stop(struct eventtimer *et) 302 { 303 struct imx_gpt_softc *sc; 304 305 sc = (struct imx_gpt_softc *)et->et_priv; 306 307 /* Disable OF2 Interrupt */ 308 CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 309 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 310 sc->sc_period = 0; 311 312 return (0); 313 } 314 315 int 316 imx_gpt_get_timerfreq(struct imx_gpt_softc *sc) 317 { 318 319 return (sc->clkfreq); 320 } 321 322 static int 323 imx_gpt_intr(void *arg) 324 { 325 struct imx_gpt_softc *sc; 326 uint32_t status; 327 328 sc = (struct imx_gpt_softc *)arg; 329 330 status = READ4(sc, IMX_GPT_SR); 331 332 /* 333 * Clear interrupt status before invoking event callbacks. The callback 334 * often sets up a new one-shot timer event and if the interval is short 335 * enough it can fire before we get out of this function. If we cleared 336 * at the bottom we'd miss the interrupt and hang until the clock wraps. 337 */ 338 WRITE4(sc, IMX_GPT_SR, status); 339 340 /* Handle one-shot timer events. */ 341 if (status & GPT_IR_OF3) { 342 if (sc->et.et_active) { 343 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 344 } 345 } 346 347 /* Handle periodic timer events. */ 348 if (status & GPT_IR_OF2) { 349 if (sc->et.et_active) 350 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 351 if (sc->sc_period != 0) 352 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 353 sc->sc_period); 354 } 355 356 return (FILTER_HANDLED); 357 } 358 359 u_int 360 imx_gpt_get_timecount(struct timecounter *tc) 361 { 362 363 if (imx_gpt_sc == NULL) 364 return (0); 365 366 return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 367 } 368 369 static device_method_t imx_gpt_methods[] = { 370 DEVMETHOD(device_probe, imx_gpt_probe), 371 DEVMETHOD(device_attach, imx_gpt_attach), 372 373 DEVMETHOD_END 374 }; 375 376 static driver_t imx_gpt_driver = { 377 "imx_gpt", 378 imx_gpt_methods, 379 sizeof(struct imx_gpt_softc), 380 }; 381 382 static devclass_t imx_gpt_devclass; 383 384 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 385 0, BUS_PASS_TIMER); 386 387 void 388 DELAY(int usec) 389 { 390 uint64_t curcnt, endcnt, startcnt, ticks; 391 392 /* If the timer hardware is not accessible, just use a loop. */ 393 if (imx_gpt_sc == NULL) { 394 while (usec-- > 0) 395 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 396 cpufunc_nullop(); 397 return; 398 } 399 400 /* 401 * Calculate the tick count with 64-bit values so that it works for any 402 * clock frequency. Loop until the hardware count reaches start+ticks. 403 * If the 32-bit hardware count rolls over while we're looping, just 404 * manually do a carry into the high bits after each read; don't worry 405 * that doing this on each loop iteration is inefficient -- we're trying 406 * to waste time here. 407 */ 408 ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 409 curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 410 endcnt = startcnt + ticks; 411 while (curcnt < endcnt) { 412 curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 413 if (curcnt < startcnt) 414 curcnt += 1ULL << 32; 415 } 416 } 417