1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Freescale i.MX515 GPIO driver. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/gpio/gpiobusvar.h> 57 #include <dev/ofw/openfirm.h> 58 #include <dev/ofw/ofw_bus.h> 59 #include <dev/ofw/ofw_bus_subr.h> 60 61 #include "gpio_if.h" 62 63 #ifdef INTRNG 64 #include "pic_if.h" 65 #endif 66 67 #define WRITE4(_sc, _r, _v) \ 68 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 69 #define READ4(_sc, _r) \ 70 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 71 #define SET4(_sc, _r, _m) \ 72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 73 #define CLEAR4(_sc, _r, _m) \ 74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 75 76 /* Registers definition for Freescale i.MX515 GPIO controller */ 77 78 #define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 79 #define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 80 #define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 81 #define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 82 #define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 83 #define GPIO_ICR_COND_LOW 0 84 #define GPIO_ICR_COND_HIGH 1 85 #define GPIO_ICR_COND_RISE 2 86 #define GPIO_ICR_COND_FALL 3 87 #define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 88 #define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 89 #define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 90 91 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 92 #define NGPIO 32 93 94 #ifdef INTRNG 95 struct gpio_irqsrc { 96 struct intr_irqsrc gi_isrc; 97 u_int gi_irq; 98 enum intr_polarity gi_pol; 99 enum intr_trigger gi_trig; 100 }; 101 #endif 102 103 struct imx51_gpio_softc { 104 device_t dev; 105 device_t sc_busdev; 106 struct mtx sc_mtx; 107 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ 108 void *gpio_ih[2]; 109 bus_space_tag_t sc_iot; 110 bus_space_handle_t sc_ioh; 111 int gpio_npins; 112 struct gpio_pin gpio_pins[NGPIO]; 113 #ifdef INTRNG 114 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO]; 115 #endif 116 }; 117 118 static struct ofw_compat_data compat_data[] = { 119 {"fsl,imx6q-gpio", 1}, 120 {"fsl,imx53-gpio", 1}, 121 {"fsl,imx51-gpio", 1}, 122 {NULL, 0} 123 }; 124 125 static struct resource_spec imx_gpio_spec[] = { 126 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 127 { SYS_RES_IRQ, 0, RF_ACTIVE }, 128 { SYS_RES_IRQ, 1, RF_ACTIVE }, 129 { -1, 0 } 130 }; 131 132 /* 133 * Helpers 134 */ 135 static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 136 struct gpio_pin *, uint32_t); 137 138 /* 139 * Driver stuff 140 */ 141 static int imx51_gpio_probe(device_t); 142 static int imx51_gpio_attach(device_t); 143 static int imx51_gpio_detach(device_t); 144 145 /* 146 * GPIO interface 147 */ 148 static device_t imx51_gpio_get_bus(device_t); 149 static int imx51_gpio_pin_max(device_t, int *); 150 static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 151 static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 152 static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 153 static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 154 static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 155 static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 156 static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 157 158 #ifdef INTRNG 159 static int 160 gpio_pic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, 161 enum intr_polarity *polp, enum intr_trigger *trigp) 162 { 163 struct imx51_gpio_softc *sc; 164 u_int irq, tripol; 165 enum intr_polarity pol; 166 enum intr_trigger trig; 167 168 sc = device_get_softc(dev); 169 170 /* 171 * From devicetree/bindings/gpio/fsl-imx-gpio.txt: 172 * #interrupt-cells: 2. The first cell is the GPIO number. The second 173 * cell bits[3:0] is used to specify trigger type and level flags: 174 * 1 = low-to-high edge triggered. 175 * 2 = high-to-low edge triggered. 176 * 4 = active high level-sensitive. 177 * 8 = active low level-sensitive. 178 * We can do any single one of these modes, but nothing in combo. 179 */ 180 181 if (ncells != 2) { 182 device_printf(sc->dev, "Invalid #interrupt-cells"); 183 return (EINVAL); 184 } 185 186 irq = cells[0]; 187 tripol = cells[1]; 188 if (irq >= sc->gpio_npins) { 189 device_printf(sc->dev, "Invalid interrupt number %d", irq); 190 return (EINVAL); 191 } 192 switch (tripol) { 193 case 1: 194 trig = INTR_TRIGGER_EDGE; 195 pol = INTR_POLARITY_HIGH; 196 break; 197 case 2: 198 trig = INTR_TRIGGER_EDGE; 199 pol = INTR_POLARITY_LOW; 200 break; 201 case 4: 202 trig = INTR_TRIGGER_LEVEL; 203 pol = INTR_POLARITY_HIGH; 204 break; 205 case 8: 206 trig = INTR_TRIGGER_LEVEL; 207 pol = INTR_POLARITY_LOW; 208 break; 209 default: 210 device_printf(sc->dev, "unsupported trigger/polarity 0x%2x\n", 211 tripol); 212 return (ENOTSUP); 213 } 214 *irqp = irq; 215 if (polp != NULL) 216 *polp = pol; 217 if (trigp != NULL) 218 *trigp = trig; 219 return (0); 220 } 221 222 static int 223 gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 224 struct intr_irqsrc **isrcp) 225 { 226 int error; 227 u_int irq; 228 struct imx51_gpio_softc *sc; 229 230 if (data->type != INTR_MAP_DATA_FDT) 231 return (ENOTSUP); 232 233 error = gpio_pic_map_fdt(dev, data->fdt.ncells, data->fdt.cells, &irq, 234 NULL, NULL); 235 if (error == 0) { 236 sc = device_get_softc(dev); 237 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; 238 } 239 return (error); 240 } 241 242 static int 243 gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 244 struct resource *res, struct intr_map_data *data) 245 { 246 struct imx51_gpio_softc *sc; 247 struct gpio_irqsrc *gi; 248 249 sc = device_get_softc(dev); 250 if (isrc->isrc_handlers == 0) { 251 gi = (struct gpio_irqsrc *)isrc; 252 gi->gi_pol = INTR_POLARITY_CONFORM; 253 gi->gi_trig = INTR_TRIGGER_CONFORM; 254 255 // XXX Not sure this is necessary 256 mtx_lock_spin(&sc->sc_mtx); 257 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq)); 258 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); 259 mtx_unlock_spin(&sc->sc_mtx); 260 } 261 return (0); 262 } 263 264 static int 265 gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 266 struct resource *res, struct intr_map_data *data) 267 { 268 struct imx51_gpio_softc *sc; 269 struct gpio_irqsrc *gi; 270 int error, icfg; 271 u_int irq, reg, shift, wrk; 272 enum intr_trigger trig; 273 enum intr_polarity pol; 274 275 sc = device_get_softc(dev); 276 gi = (struct gpio_irqsrc *)isrc; 277 278 /* Get config for interrupt. */ 279 if (data == NULL || data->type != INTR_MAP_DATA_FDT) 280 return (ENOTSUP); 281 error = gpio_pic_map_fdt(dev, data->fdt.ncells, data->fdt.cells, &irq, 282 &pol, &trig); 283 if (error != 0) 284 return (error); 285 if (gi->gi_irq != irq) 286 return (EINVAL); 287 288 /* Compare config if this is not first setup. */ 289 if (isrc->isrc_handlers != 0) { 290 if (pol != gi->gi_pol || trig != gi->gi_trig) 291 return (EINVAL); 292 else 293 return (0); 294 } 295 296 gi->gi_pol = pol; 297 gi->gi_trig = trig; 298 299 if (trig == INTR_TRIGGER_LEVEL) { 300 if (pol == INTR_POLARITY_LOW) 301 icfg = GPIO_ICR_COND_LOW; 302 else 303 icfg = GPIO_ICR_COND_HIGH; 304 } else { 305 if (pol == INTR_POLARITY_HIGH) 306 icfg = GPIO_ICR_COND_FALL; 307 else 308 icfg = GPIO_ICR_COND_RISE; 309 } 310 311 if (irq < 16) { 312 reg = IMX_GPIO_ICR1_REG; 313 shift = 2 * irq; 314 } else { 315 reg = IMX_GPIO_ICR2_REG; 316 shift = 2 * (irq - 16); 317 } 318 319 mtx_lock_spin(&sc->sc_mtx); 320 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 321 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 322 wrk = READ4(sc, reg); 323 wrk &= ~(0x03 << shift); 324 wrk |= icfg << shift; 325 WRITE4(sc, reg, wrk); 326 mtx_unlock_spin(&sc->sc_mtx); 327 return (0); 328 } 329 330 /* 331 * this is mask_intr 332 */ 333 static void 334 gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 335 { 336 struct imx51_gpio_softc *sc; 337 u_int irq; 338 339 sc = device_get_softc(dev); 340 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 341 342 mtx_lock_spin(&sc->sc_mtx); 343 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 344 mtx_unlock_spin(&sc->sc_mtx); 345 } 346 347 /* 348 * this is unmask_intr 349 */ 350 static void 351 gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 352 { 353 struct imx51_gpio_softc *sc; 354 u_int irq; 355 356 sc = device_get_softc(dev); 357 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 358 359 mtx_lock_spin(&sc->sc_mtx); 360 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 361 mtx_unlock_spin(&sc->sc_mtx); 362 } 363 364 static void 365 gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 366 { 367 struct imx51_gpio_softc *sc; 368 u_int irq; 369 370 sc = device_get_softc(dev); 371 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 372 373 arm_irq_memory_barrier(0); 374 /* EOI. W1C reg so no r-m-w, no locking needed. */ 375 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 376 } 377 378 static void 379 gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 380 { 381 382 arm_irq_memory_barrier(0); 383 gpio_pic_enable_intr(dev, isrc); 384 } 385 386 static void 387 gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 388 { 389 390 gpio_pic_disable_intr(dev, isrc); 391 } 392 393 static int 394 gpio_pic_filter(void *arg) 395 { 396 struct imx51_gpio_softc *sc; 397 struct intr_irqsrc *isrc; 398 uint32_t i, interrupts; 399 400 sc = arg; 401 mtx_lock_spin(&sc->sc_mtx); 402 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); 403 mtx_unlock_spin(&sc->sc_mtx); 404 405 for (i = 0; interrupts != 0; i++, interrupts >>= 1) { 406 if ((interrupts & 0x1) == 0) 407 continue; 408 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc; 409 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { 410 gpio_pic_disable_intr(sc->dev, isrc); 411 gpio_pic_post_filter(sc->dev, isrc); 412 device_printf(sc->dev, "Stray irq %u disabled\n", i); 413 } 414 } 415 416 return (FILTER_HANDLED); 417 } 418 419 /* 420 * Initialize our isrcs and register them with intrng. 421 */ 422 static int 423 gpio_pic_register_isrcs(struct imx51_gpio_softc *sc) 424 { 425 int error; 426 uint32_t irq; 427 const char *name; 428 429 name = device_get_nameunit(sc->dev); 430 for (irq = 0; irq < NGPIO; irq++) { 431 sc->gpio_pic_irqsrc[irq].gi_irq = irq; 432 sc->gpio_pic_irqsrc[irq].gi_pol = INTR_POLARITY_CONFORM; 433 sc->gpio_pic_irqsrc[irq].gi_trig = INTR_TRIGGER_CONFORM; 434 435 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, 436 sc->dev, 0, "%s,%u", name, irq); 437 if (error != 0) { 438 /* XXX call intr_isrc_deregister() */ 439 device_printf(sc->dev, "%s failed", __func__); 440 return (error); 441 } 442 } 443 return (0); 444 } 445 #endif 446 447 /* 448 * 449 */ 450 static void 451 imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 452 unsigned int flags) 453 { 454 u_int newflags; 455 456 mtx_lock_spin(&sc->sc_mtx); 457 458 /* 459 * Manage input/output; other flags not supported yet. 460 * 461 * Note that changes to pin->gp_flags must be acccumulated in newflags 462 * and stored with a single writeback to gp_flags at the end, to enable 463 * unlocked reads of that value elsewhere. 464 */ 465 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 466 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 467 if (flags & GPIO_PIN_OUTPUT) { 468 newflags |= GPIO_PIN_OUTPUT; 469 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 470 } else { 471 newflags |= GPIO_PIN_INPUT; 472 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 473 } 474 pin->gp_flags = newflags; 475 } 476 477 mtx_unlock_spin(&sc->sc_mtx); 478 } 479 480 static device_t 481 imx51_gpio_get_bus(device_t dev) 482 { 483 struct imx51_gpio_softc *sc; 484 485 sc = device_get_softc(dev); 486 487 return (sc->sc_busdev); 488 } 489 490 static int 491 imx51_gpio_pin_max(device_t dev, int *maxpin) 492 { 493 struct imx51_gpio_softc *sc; 494 495 sc = device_get_softc(dev); 496 *maxpin = sc->gpio_npins - 1; 497 498 return (0); 499 } 500 501 static int 502 imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 503 { 504 struct imx51_gpio_softc *sc; 505 506 sc = device_get_softc(dev); 507 508 if (pin >= sc->gpio_npins) 509 return (EINVAL); 510 511 *caps = sc->gpio_pins[pin].gp_caps; 512 513 return (0); 514 } 515 516 static int 517 imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 518 { 519 struct imx51_gpio_softc *sc; 520 521 sc = device_get_softc(dev); 522 523 if (pin >= sc->gpio_npins) 524 return (EINVAL); 525 526 *flags = sc->gpio_pins[pin].gp_flags; 527 528 return (0); 529 } 530 531 static int 532 imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 533 { 534 struct imx51_gpio_softc *sc; 535 536 sc = device_get_softc(dev); 537 if (pin >= sc->gpio_npins) 538 return (EINVAL); 539 540 mtx_lock_spin(&sc->sc_mtx); 541 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 542 mtx_unlock_spin(&sc->sc_mtx); 543 544 return (0); 545 } 546 547 static int 548 imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 549 { 550 struct imx51_gpio_softc *sc; 551 552 sc = device_get_softc(dev); 553 554 if (pin >= sc->gpio_npins) 555 return (EINVAL); 556 557 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 558 559 return (0); 560 } 561 562 static int 563 imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 564 { 565 struct imx51_gpio_softc *sc; 566 567 sc = device_get_softc(dev); 568 569 if (pin >= sc->gpio_npins) 570 return (EINVAL); 571 572 mtx_lock_spin(&sc->sc_mtx); 573 if (value) 574 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); 575 else 576 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin)); 577 mtx_unlock_spin(&sc->sc_mtx); 578 579 return (0); 580 } 581 582 static int 583 imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 584 { 585 struct imx51_gpio_softc *sc; 586 587 sc = device_get_softc(dev); 588 589 if (pin >= sc->gpio_npins) 590 return (EINVAL); 591 592 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; 593 594 return (0); 595 } 596 597 static int 598 imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 599 { 600 struct imx51_gpio_softc *sc; 601 602 sc = device_get_softc(dev); 603 604 if (pin >= sc->gpio_npins) 605 return (EINVAL); 606 607 mtx_lock_spin(&sc->sc_mtx); 608 WRITE4(sc, IMX_GPIO_DR_REG, 609 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); 610 mtx_unlock_spin(&sc->sc_mtx); 611 612 return (0); 613 } 614 615 static int 616 imx51_gpio_probe(device_t dev) 617 { 618 619 if (!ofw_bus_status_okay(dev)) 620 return (ENXIO); 621 622 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 623 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 624 return (BUS_PROBE_DEFAULT); 625 } 626 627 return (ENXIO); 628 } 629 630 static int 631 imx51_gpio_attach(device_t dev) 632 { 633 struct imx51_gpio_softc *sc; 634 int i, irq, unit; 635 636 sc = device_get_softc(dev); 637 sc->dev = dev; 638 sc->gpio_npins = NGPIO; 639 640 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); 641 642 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 643 device_printf(dev, "could not allocate resources\n"); 644 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 645 mtx_destroy(&sc->sc_mtx); 646 return (ENXIO); 647 } 648 649 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 650 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 651 /* 652 * Mask off all interrupts in hardware, then set up interrupt handling. 653 */ 654 WRITE4(sc, IMX_GPIO_IMR_REG, 0); 655 for (irq = 0; irq < 2; irq++) { 656 #ifdef INTRNG 657 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, 658 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { 659 device_printf(dev, 660 "WARNING: unable to register interrupt handler\n"); 661 imx51_gpio_detach(dev); 662 return (ENXIO); 663 } 664 #endif 665 } 666 667 unit = device_get_unit(dev); 668 for (i = 0; i < sc->gpio_npins; i++) { 669 sc->gpio_pins[i].gp_pin = i; 670 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 671 sc->gpio_pins[i].gp_flags = 672 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : 673 GPIO_PIN_INPUT; 674 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 675 "imx_gpio%d.%d", unit, i); 676 } 677 678 #ifdef INTRNG 679 gpio_pic_register_isrcs(sc); 680 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); 681 #endif 682 sc->sc_busdev = gpiobus_attach_bus(dev); 683 684 if (sc->sc_busdev == NULL) { 685 imx51_gpio_detach(dev); 686 return (ENXIO); 687 } 688 689 return (0); 690 } 691 692 static int 693 imx51_gpio_detach(device_t dev) 694 { 695 int irq; 696 struct imx51_gpio_softc *sc; 697 698 sc = device_get_softc(dev); 699 700 gpiobus_detach_bus(dev); 701 for (irq = 1; irq <= 2; irq++) { 702 if (sc->gpio_ih[irq]) 703 bus_teardown_intr(dev, sc->sc_res[irq], sc->gpio_ih[irq]); 704 } 705 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 706 mtx_destroy(&sc->sc_mtx); 707 708 return(0); 709 } 710 711 static device_method_t imx51_gpio_methods[] = { 712 DEVMETHOD(device_probe, imx51_gpio_probe), 713 DEVMETHOD(device_attach, imx51_gpio_attach), 714 DEVMETHOD(device_detach, imx51_gpio_detach), 715 716 #ifdef INTRNG 717 /* Interrupt controller interface */ 718 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), 719 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), 720 DEVMETHOD(pic_map_intr, gpio_pic_map_intr), 721 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), 722 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), 723 DEVMETHOD(pic_post_filter, gpio_pic_post_filter), 724 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), 725 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), 726 #endif 727 728 /* GPIO protocol */ 729 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 730 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 731 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 732 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 733 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 734 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 735 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 736 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 737 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 738 {0, 0}, 739 }; 740 741 static driver_t imx51_gpio_driver = { 742 "gpio", 743 imx51_gpio_methods, 744 sizeof(struct imx51_gpio_softc), 745 }; 746 static devclass_t imx51_gpio_devclass; 747 748 DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass, 749 0, 0); 750