1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Freescale i.MX515 GPIO driver. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <dev/gpio/gpiobusvar.h> 56 #include <dev/ofw/openfirm.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 60 #include "gpio_if.h" 61 62 #ifdef INTRNG 63 #include "pic_if.h" 64 #endif 65 66 #define WRITE4(_sc, _r, _v) \ 67 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 68 #define READ4(_sc, _r) \ 69 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 70 #define SET4(_sc, _r, _m) \ 71 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 72 #define CLEAR4(_sc, _r, _m) \ 73 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 74 75 /* Registers definition for Freescale i.MX515 GPIO controller */ 76 77 #define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 78 #define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 79 #define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 80 #define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 81 #define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 82 #define GPIO_ICR_COND_LOW 0 83 #define GPIO_ICR_COND_HIGH 1 84 #define GPIO_ICR_COND_RISE 2 85 #define GPIO_ICR_COND_FALL 3 86 #define GPIO_ICR_COND_MASK 0x3 87 #define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 88 #define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 89 #define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 90 91 #ifdef INTRNG 92 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 93 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 94 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 95 #else 96 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 97 #endif 98 99 #define NGPIO 32 100 101 #ifdef INTRNG 102 struct gpio_irqsrc { 103 struct intr_irqsrc gi_isrc; 104 u_int gi_irq; 105 uint32_t gi_mode; 106 }; 107 #endif 108 109 struct imx51_gpio_softc { 110 device_t dev; 111 device_t sc_busdev; 112 struct mtx sc_mtx; 113 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ 114 void *gpio_ih[2]; 115 bus_space_tag_t sc_iot; 116 bus_space_handle_t sc_ioh; 117 int gpio_npins; 118 struct gpio_pin gpio_pins[NGPIO]; 119 #ifdef INTRNG 120 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO]; 121 #endif 122 }; 123 124 static struct ofw_compat_data compat_data[] = { 125 {"fsl,imx6q-gpio", 1}, 126 {"fsl,imx53-gpio", 1}, 127 {"fsl,imx51-gpio", 1}, 128 {NULL, 0} 129 }; 130 131 static struct resource_spec imx_gpio_spec[] = { 132 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 133 { SYS_RES_IRQ, 0, RF_ACTIVE }, 134 { SYS_RES_IRQ, 1, RF_ACTIVE }, 135 { -1, 0 } 136 }; 137 138 /* 139 * Helpers 140 */ 141 static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 142 struct gpio_pin *, uint32_t); 143 144 /* 145 * Driver stuff 146 */ 147 static int imx51_gpio_probe(device_t); 148 static int imx51_gpio_attach(device_t); 149 static int imx51_gpio_detach(device_t); 150 151 /* 152 * GPIO interface 153 */ 154 static device_t imx51_gpio_get_bus(device_t); 155 static int imx51_gpio_pin_max(device_t, int *); 156 static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 157 static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 158 static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 159 static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 160 static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 161 static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 162 static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 163 164 #ifdef INTRNG 165 static int 166 gpio_pic_map_fdt(struct imx51_gpio_softc *sc, struct intr_map_data_fdt *daf, 167 u_int *irqp, uint32_t *modep) 168 { 169 u_int irq; 170 uint32_t mode; 171 172 /* 173 * From devicetree/bindings/gpio/fsl-imx-gpio.txt: 174 * #interrupt-cells: 2. The first cell is the GPIO number. The second 175 * cell bits[3:0] is used to specify trigger type and level flags: 176 * 1 = low-to-high edge triggered. 177 * 2 = high-to-low edge triggered. 178 * 4 = active high level-sensitive. 179 * 8 = active low level-sensitive. 180 * We can do any single one of these modes, and also edge low+high 181 * (i.e., trigger on both edges); other combinations are not supported. 182 */ 183 184 if (daf->ncells != 2) { 185 device_printf(sc->dev, "Invalid #interrupt-cells\n"); 186 return (EINVAL); 187 } 188 189 irq = daf->cells[0]; 190 if (irq >= sc->gpio_npins) { 191 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 192 return (EINVAL); 193 } 194 switch (daf->cells[1]) { 195 case 1: 196 mode = GPIO_INTR_EDGE_RISING; 197 break; 198 case 2: 199 mode = GPIO_INTR_EDGE_FALLING; 200 break; 201 case 3: 202 mode = GPIO_INTR_EDGE_BOTH; 203 break; 204 case 4: 205 mode = GPIO_INTR_LEVEL_HIGH; 206 break; 207 case 8: 208 mode = GPIO_INTR_LEVEL_LOW; 209 break; 210 default: 211 device_printf(sc->dev, "Unsupported interrupt mode 0x%2x\n", 212 daf->cells[1]); 213 return (ENOTSUP); 214 } 215 *irqp = irq; 216 if (modep != NULL) 217 *modep = mode; 218 return (0); 219 } 220 221 static int 222 gpio_pic_map_gpio(struct imx51_gpio_softc *sc, struct intr_map_data_gpio *dag, 223 u_int *irqp, uint32_t *modep) 224 { 225 u_int irq; 226 227 irq = dag->gpio_pin_num; 228 if (irq >= sc->gpio_npins) { 229 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 230 return (EINVAL); 231 } 232 233 switch (dag->gpio_intr_mode) { 234 case GPIO_INTR_LEVEL_LOW: 235 case GPIO_INTR_LEVEL_HIGH: 236 case GPIO_INTR_EDGE_RISING: 237 case GPIO_INTR_EDGE_FALLING: 238 case GPIO_INTR_EDGE_BOTH: 239 break; 240 default: 241 device_printf(sc->dev, "Unsupported interrupt mode 0x%8x\n", 242 dag->gpio_intr_mode); 243 return (EINVAL); 244 } 245 246 *irqp = irq; 247 if (modep != NULL) 248 *modep = dag->gpio_intr_mode; 249 return (0); 250 } 251 252 static int 253 gpio_pic_map(struct imx51_gpio_softc *sc, struct intr_map_data *data, 254 u_int *irqp, uint32_t *modep) 255 { 256 257 switch (data->type) { 258 case INTR_MAP_DATA_FDT: 259 return (gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data, 260 irqp, modep)); 261 case INTR_MAP_DATA_GPIO: 262 return (gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data, 263 irqp, modep)); 264 default: 265 return (ENOTSUP); 266 } 267 } 268 269 static int 270 gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 271 struct intr_irqsrc **isrcp) 272 { 273 int error; 274 u_int irq; 275 struct imx51_gpio_softc *sc; 276 277 sc = device_get_softc(dev); 278 error = gpio_pic_map(sc, data, &irq, NULL); 279 if (error == 0) 280 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; 281 return (error); 282 } 283 284 static int 285 gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 286 struct resource *res, struct intr_map_data *data) 287 { 288 struct imx51_gpio_softc *sc; 289 struct gpio_irqsrc *gi; 290 291 sc = device_get_softc(dev); 292 if (isrc->isrc_handlers == 0) { 293 gi = (struct gpio_irqsrc *)isrc; 294 gi->gi_mode = GPIO_INTR_CONFORM; 295 296 // XXX Not sure this is necessary 297 mtx_lock_spin(&sc->sc_mtx); 298 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq)); 299 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); 300 mtx_unlock_spin(&sc->sc_mtx); 301 } 302 return (0); 303 } 304 305 static int 306 gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 307 struct resource *res, struct intr_map_data *data) 308 { 309 struct imx51_gpio_softc *sc; 310 struct gpio_irqsrc *gi; 311 int error; 312 u_int icfg, irq, reg, shift, wrk; 313 uint32_t mode; 314 315 if (data == NULL) 316 return (ENOTSUP); 317 318 sc = device_get_softc(dev); 319 gi = (struct gpio_irqsrc *)isrc; 320 321 /* Get config for interrupt. */ 322 error = gpio_pic_map(sc, data, &irq, &mode); 323 if (error != 0) 324 return (error); 325 if (gi->gi_irq != irq) 326 return (EINVAL); 327 328 /* Compare config if this is not first setup. */ 329 if (isrc->isrc_handlers != 0) 330 return (gi->gi_mode == mode ? 0 : EINVAL); 331 gi->gi_mode = mode; 332 333 /* 334 * To interrupt on both edges we have to use the EDGE register. The 335 * manual says it only exists for backwards compatibilty with older imx 336 * chips, but it's also the only way to configure interrupting on both 337 * edges. If the EDGE bit is on, the corresponding ICRn bit is ignored. 338 */ 339 mtx_lock_spin(&sc->sc_mtx); 340 if (mode == GPIO_INTR_EDGE_BOTH) { 341 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 342 } else { 343 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 344 switch (mode) { 345 default: 346 /* silence warnings; default can't actually happen. */ 347 /* FALLTHROUGH */ 348 case GPIO_INTR_LEVEL_LOW: 349 icfg = GPIO_ICR_COND_LOW; 350 break; 351 case GPIO_INTR_LEVEL_HIGH: 352 icfg = GPIO_ICR_COND_HIGH; 353 break; 354 case GPIO_INTR_EDGE_RISING: 355 icfg = GPIO_ICR_COND_RISE; 356 break; 357 case GPIO_INTR_EDGE_FALLING: 358 icfg = GPIO_ICR_COND_FALL; 359 break; 360 } 361 if (irq < 16) { 362 reg = IMX_GPIO_ICR1_REG; 363 shift = 2 * irq; 364 } else { 365 reg = IMX_GPIO_ICR2_REG; 366 shift = 2 * (irq - 16); 367 } 368 wrk = READ4(sc, reg); 369 wrk &= ~(GPIO_ICR_COND_MASK << shift); 370 wrk |= icfg << shift; 371 WRITE4(sc, reg, wrk); 372 } 373 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); 374 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq)); 375 mtx_unlock_spin(&sc->sc_mtx); 376 377 return (0); 378 } 379 380 /* 381 * this is mask_intr 382 */ 383 static void 384 gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 385 { 386 struct imx51_gpio_softc *sc; 387 u_int irq; 388 389 sc = device_get_softc(dev); 390 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 391 392 mtx_lock_spin(&sc->sc_mtx); 393 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 394 mtx_unlock_spin(&sc->sc_mtx); 395 } 396 397 /* 398 * this is unmask_intr 399 */ 400 static void 401 gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 402 { 403 struct imx51_gpio_softc *sc; 404 u_int irq; 405 406 sc = device_get_softc(dev); 407 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 408 409 mtx_lock_spin(&sc->sc_mtx); 410 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 411 mtx_unlock_spin(&sc->sc_mtx); 412 } 413 414 static void 415 gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 416 { 417 struct imx51_gpio_softc *sc; 418 u_int irq; 419 420 sc = device_get_softc(dev); 421 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 422 423 arm_irq_memory_barrier(0); 424 /* EOI. W1C reg so no r-m-w, no locking needed. */ 425 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 426 } 427 428 static void 429 gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 430 { 431 struct imx51_gpio_softc *sc; 432 u_int irq; 433 434 sc = device_get_softc(dev); 435 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 436 437 arm_irq_memory_barrier(0); 438 /* EOI. W1C reg so no r-m-w, no locking needed. */ 439 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 440 gpio_pic_enable_intr(dev, isrc); 441 } 442 443 static void 444 gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 445 { 446 gpio_pic_disable_intr(dev, isrc); 447 } 448 449 static int 450 gpio_pic_filter(void *arg) 451 { 452 struct imx51_gpio_softc *sc; 453 struct intr_irqsrc *isrc; 454 uint32_t i, interrupts; 455 456 sc = arg; 457 mtx_lock_spin(&sc->sc_mtx); 458 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); 459 mtx_unlock_spin(&sc->sc_mtx); 460 461 for (i = 0; interrupts != 0; i++, interrupts >>= 1) { 462 if ((interrupts & 0x1) == 0) 463 continue; 464 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc; 465 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { 466 gpio_pic_disable_intr(sc->dev, isrc); 467 gpio_pic_post_filter(sc->dev, isrc); 468 device_printf(sc->dev, "Stray irq %u disabled\n", i); 469 } 470 } 471 472 return (FILTER_HANDLED); 473 } 474 475 /* 476 * Initialize our isrcs and register them with intrng. 477 */ 478 static int 479 gpio_pic_register_isrcs(struct imx51_gpio_softc *sc) 480 { 481 int error; 482 uint32_t irq; 483 const char *name; 484 485 name = device_get_nameunit(sc->dev); 486 for (irq = 0; irq < NGPIO; irq++) { 487 sc->gpio_pic_irqsrc[irq].gi_irq = irq; 488 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM; 489 490 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, 491 sc->dev, 0, "%s,%u", name, irq); 492 if (error != 0) { 493 /* XXX call intr_isrc_deregister() */ 494 device_printf(sc->dev, "%s failed", __func__); 495 return (error); 496 } 497 } 498 return (0); 499 } 500 #endif 501 502 /* 503 * 504 */ 505 static void 506 imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 507 unsigned int flags) 508 { 509 u_int newflags; 510 511 mtx_lock_spin(&sc->sc_mtx); 512 513 /* 514 * Manage input/output; other flags not supported yet. 515 * 516 * Note that changes to pin->gp_flags must be acccumulated in newflags 517 * and stored with a single writeback to gp_flags at the end, to enable 518 * unlocked reads of that value elsewhere. 519 */ 520 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 521 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 522 if (flags & GPIO_PIN_OUTPUT) { 523 newflags |= GPIO_PIN_OUTPUT; 524 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 525 } else { 526 newflags |= GPIO_PIN_INPUT; 527 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 528 } 529 pin->gp_flags = newflags; 530 } 531 532 mtx_unlock_spin(&sc->sc_mtx); 533 } 534 535 static device_t 536 imx51_gpio_get_bus(device_t dev) 537 { 538 struct imx51_gpio_softc *sc; 539 540 sc = device_get_softc(dev); 541 542 return (sc->sc_busdev); 543 } 544 545 static int 546 imx51_gpio_pin_max(device_t dev, int *maxpin) 547 { 548 struct imx51_gpio_softc *sc; 549 550 sc = device_get_softc(dev); 551 *maxpin = sc->gpio_npins - 1; 552 553 return (0); 554 } 555 556 static int 557 imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 558 { 559 struct imx51_gpio_softc *sc; 560 561 sc = device_get_softc(dev); 562 563 if (pin >= sc->gpio_npins) 564 return (EINVAL); 565 566 *caps = sc->gpio_pins[pin].gp_caps; 567 568 return (0); 569 } 570 571 static int 572 imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 573 { 574 struct imx51_gpio_softc *sc; 575 576 sc = device_get_softc(dev); 577 578 if (pin >= sc->gpio_npins) 579 return (EINVAL); 580 581 *flags = sc->gpio_pins[pin].gp_flags; 582 583 return (0); 584 } 585 586 static int 587 imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 588 { 589 struct imx51_gpio_softc *sc; 590 591 sc = device_get_softc(dev); 592 if (pin >= sc->gpio_npins) 593 return (EINVAL); 594 595 mtx_lock_spin(&sc->sc_mtx); 596 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 597 mtx_unlock_spin(&sc->sc_mtx); 598 599 return (0); 600 } 601 602 static int 603 imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 604 { 605 struct imx51_gpio_softc *sc; 606 607 sc = device_get_softc(dev); 608 609 if (pin >= sc->gpio_npins) 610 return (EINVAL); 611 612 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 613 614 return (0); 615 } 616 617 static int 618 imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 619 { 620 struct imx51_gpio_softc *sc; 621 622 sc = device_get_softc(dev); 623 624 if (pin >= sc->gpio_npins) 625 return (EINVAL); 626 627 mtx_lock_spin(&sc->sc_mtx); 628 if (value) 629 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); 630 else 631 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin)); 632 mtx_unlock_spin(&sc->sc_mtx); 633 634 return (0); 635 } 636 637 static int 638 imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 639 { 640 struct imx51_gpio_softc *sc; 641 642 sc = device_get_softc(dev); 643 644 if (pin >= sc->gpio_npins) 645 return (EINVAL); 646 647 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; 648 649 return (0); 650 } 651 652 static int 653 imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 654 { 655 struct imx51_gpio_softc *sc; 656 657 sc = device_get_softc(dev); 658 659 if (pin >= sc->gpio_npins) 660 return (EINVAL); 661 662 mtx_lock_spin(&sc->sc_mtx); 663 WRITE4(sc, IMX_GPIO_DR_REG, 664 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); 665 mtx_unlock_spin(&sc->sc_mtx); 666 667 return (0); 668 } 669 670 static int 671 imx51_gpio_probe(device_t dev) 672 { 673 674 if (!ofw_bus_status_okay(dev)) 675 return (ENXIO); 676 677 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 678 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 679 return (BUS_PROBE_DEFAULT); 680 } 681 682 return (ENXIO); 683 } 684 685 static int 686 imx51_gpio_attach(device_t dev) 687 { 688 struct imx51_gpio_softc *sc; 689 int i, irq, unit; 690 691 sc = device_get_softc(dev); 692 sc->dev = dev; 693 sc->gpio_npins = NGPIO; 694 695 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); 696 697 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 698 device_printf(dev, "could not allocate resources\n"); 699 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 700 mtx_destroy(&sc->sc_mtx); 701 return (ENXIO); 702 } 703 704 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 705 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 706 /* 707 * Mask off all interrupts in hardware, then set up interrupt handling. 708 */ 709 WRITE4(sc, IMX_GPIO_IMR_REG, 0); 710 for (irq = 0; irq < 2; irq++) { 711 #ifdef INTRNG 712 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, 713 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { 714 device_printf(dev, 715 "WARNING: unable to register interrupt handler\n"); 716 imx51_gpio_detach(dev); 717 return (ENXIO); 718 } 719 #endif 720 } 721 722 unit = device_get_unit(dev); 723 for (i = 0; i < sc->gpio_npins; i++) { 724 sc->gpio_pins[i].gp_pin = i; 725 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 726 sc->gpio_pins[i].gp_flags = 727 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : 728 GPIO_PIN_INPUT; 729 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 730 "GPIO%d_IO%02d", unit + 1, i); 731 } 732 733 #ifdef INTRNG 734 gpio_pic_register_isrcs(sc); 735 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); 736 #endif 737 sc->sc_busdev = gpiobus_attach_bus(dev); 738 739 if (sc->sc_busdev == NULL) { 740 imx51_gpio_detach(dev); 741 return (ENXIO); 742 } 743 744 return (0); 745 } 746 747 static int 748 imx51_gpio_detach(device_t dev) 749 { 750 int irq; 751 struct imx51_gpio_softc *sc; 752 753 sc = device_get_softc(dev); 754 755 gpiobus_detach_bus(dev); 756 for (irq = 1; irq <= 2; irq++) { 757 if (sc->gpio_ih[irq]) 758 bus_teardown_intr(dev, sc->sc_res[irq], sc->gpio_ih[irq]); 759 } 760 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 761 mtx_destroy(&sc->sc_mtx); 762 763 return(0); 764 } 765 766 static device_method_t imx51_gpio_methods[] = { 767 DEVMETHOD(device_probe, imx51_gpio_probe), 768 DEVMETHOD(device_attach, imx51_gpio_attach), 769 DEVMETHOD(device_detach, imx51_gpio_detach), 770 771 #ifdef INTRNG 772 /* Interrupt controller interface */ 773 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), 774 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), 775 DEVMETHOD(pic_map_intr, gpio_pic_map_intr), 776 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), 777 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), 778 DEVMETHOD(pic_post_filter, gpio_pic_post_filter), 779 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), 780 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), 781 #endif 782 783 /* GPIO protocol */ 784 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 785 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 786 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 787 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 788 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 789 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 790 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 791 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 792 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 793 {0, 0}, 794 }; 795 796 static driver_t imx51_gpio_driver = { 797 "gpio", 798 imx51_gpio_methods, 799 sizeof(struct imx51_gpio_softc), 800 }; 801 static devclass_t imx51_gpio_devclass; 802 803 DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass, 804 0, 0); 805