1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Freescale i.MX515 GPIO driver. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/gpio/gpiobusvar.h> 57 #include <dev/ofw/openfirm.h> 58 #include <dev/ofw/ofw_bus.h> 59 #include <dev/ofw/ofw_bus_subr.h> 60 61 #include "gpio_if.h" 62 63 #ifdef INTRNG 64 #include "pic_if.h" 65 #endif 66 67 #define WRITE4(_sc, _r, _v) \ 68 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 69 #define READ4(_sc, _r) \ 70 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 71 #define SET4(_sc, _r, _m) \ 72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 73 #define CLEAR4(_sc, _r, _m) \ 74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 75 76 /* Registers definition for Freescale i.MX515 GPIO controller */ 77 78 #define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 79 #define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 80 #define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 81 #define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 82 #define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 83 #define GPIO_ICR_COND_LOW 0 84 #define GPIO_ICR_COND_HIGH 1 85 #define GPIO_ICR_COND_RISE 2 86 #define GPIO_ICR_COND_FALL 3 87 #define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 88 #define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 89 #define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 90 91 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 92 #define NGPIO 32 93 94 #ifdef INTRNG 95 struct gpio_irqsrc { 96 struct intr_irqsrc gi_isrc; 97 u_int gi_irq; 98 enum intr_polarity gi_pol; 99 enum intr_trigger gi_trig; 100 }; 101 #endif 102 103 struct imx51_gpio_softc { 104 device_t dev; 105 device_t sc_busdev; 106 struct mtx sc_mtx; 107 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ 108 void *gpio_ih[2]; 109 bus_space_tag_t sc_iot; 110 bus_space_handle_t sc_ioh; 111 int gpio_npins; 112 struct gpio_pin gpio_pins[NGPIO]; 113 #ifdef INTRNG 114 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO]; 115 #endif 116 }; 117 118 static struct ofw_compat_data compat_data[] = { 119 {"fsl,imx6q-gpio", 1}, 120 {"fsl,imx53-gpio", 1}, 121 {"fsl,imx51-gpio", 1}, 122 {NULL, 0} 123 }; 124 125 static struct resource_spec imx_gpio_spec[] = { 126 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 127 { SYS_RES_IRQ, 0, RF_ACTIVE }, 128 { SYS_RES_IRQ, 1, RF_ACTIVE }, 129 { -1, 0 } 130 }; 131 132 /* 133 * Helpers 134 */ 135 static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 136 struct gpio_pin *, uint32_t); 137 138 /* 139 * Driver stuff 140 */ 141 static int imx51_gpio_probe(device_t); 142 static int imx51_gpio_attach(device_t); 143 static int imx51_gpio_detach(device_t); 144 145 /* 146 * GPIO interface 147 */ 148 static device_t imx51_gpio_get_bus(device_t); 149 static int imx51_gpio_pin_max(device_t, int *); 150 static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 151 static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 152 static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 153 static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 154 static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 155 static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 156 static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 157 158 #ifdef INTRNG 159 static int 160 gpio_pic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, 161 enum intr_polarity *polp, enum intr_trigger *trigp) 162 { 163 struct imx51_gpio_softc *sc; 164 u_int irq, tripol; 165 enum intr_polarity pol; 166 enum intr_trigger trig; 167 168 sc = device_get_softc(dev); 169 170 /* 171 * From devicetree/bindings/gpio/fsl-imx-gpio.txt: 172 * #interrupt-cells: 2. The first cell is the GPIO number. The second 173 * cell bits[3:0] is used to specify trigger type and level flags: 174 * 1 = low-to-high edge triggered. 175 * 2 = high-to-low edge triggered. 176 * 4 = active high level-sensitive. 177 * 8 = active low level-sensitive. 178 * We can do any single one of these modes, but nothing in combo. 179 */ 180 181 if (ncells != 2) { 182 device_printf(sc->dev, "Invalid #interrupt-cells"); 183 return (EINVAL); 184 } 185 186 irq = cells[0]; 187 tripol = cells[1]; 188 if (irq >= sc->gpio_npins) { 189 device_printf(sc->dev, "Invalid interrupt number %d", irq); 190 return (EINVAL); 191 } 192 switch (tripol) { 193 case 1: 194 trig = INTR_TRIGGER_EDGE; 195 pol = INTR_POLARITY_HIGH; 196 break; 197 case 2: 198 trig = INTR_TRIGGER_EDGE; 199 pol = INTR_POLARITY_LOW; 200 break; 201 case 4: 202 trig = INTR_TRIGGER_LEVEL; 203 pol = INTR_POLARITY_HIGH; 204 break; 205 case 8: 206 trig = INTR_TRIGGER_LEVEL; 207 pol = INTR_POLARITY_LOW; 208 break; 209 default: 210 device_printf(sc->dev, "unsupported trigger/polarity 0x%2x\n", 211 tripol); 212 return (ENOTSUP); 213 } 214 *irqp = irq; 215 if (polp != NULL) 216 *polp = pol; 217 if (trigp != NULL) 218 *trigp = trig; 219 return (0); 220 } 221 222 static int 223 gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 224 struct intr_irqsrc **isrcp) 225 { 226 int error; 227 u_int irq; 228 struct intr_map_data_fdt *daf; 229 struct imx51_gpio_softc *sc; 230 231 if (data->type != INTR_MAP_DATA_FDT) 232 return (ENOTSUP); 233 234 daf = (struct intr_map_data_fdt *)data; 235 error = gpio_pic_map_fdt(dev, daf->ncells, daf->cells, &irq, NULL, 236 NULL); 237 if (error == 0) { 238 sc = device_get_softc(dev); 239 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; 240 } 241 return (error); 242 } 243 244 static int 245 gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 246 struct resource *res, struct intr_map_data *data) 247 { 248 struct imx51_gpio_softc *sc; 249 struct gpio_irqsrc *gi; 250 251 sc = device_get_softc(dev); 252 if (isrc->isrc_handlers == 0) { 253 gi = (struct gpio_irqsrc *)isrc; 254 gi->gi_pol = INTR_POLARITY_CONFORM; 255 gi->gi_trig = INTR_TRIGGER_CONFORM; 256 257 // XXX Not sure this is necessary 258 mtx_lock_spin(&sc->sc_mtx); 259 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq)); 260 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); 261 mtx_unlock_spin(&sc->sc_mtx); 262 } 263 return (0); 264 } 265 266 static int 267 gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 268 struct resource *res, struct intr_map_data *data) 269 { 270 struct intr_map_data_fdt *daf; 271 struct imx51_gpio_softc *sc; 272 struct gpio_irqsrc *gi; 273 int error, icfg; 274 u_int irq, reg, shift, wrk; 275 enum intr_trigger trig; 276 enum intr_polarity pol; 277 278 sc = device_get_softc(dev); 279 gi = (struct gpio_irqsrc *)isrc; 280 281 /* Get config for interrupt. */ 282 if (data == NULL || data->type != INTR_MAP_DATA_FDT) 283 return (ENOTSUP); 284 daf = (struct intr_map_data_fdt *)data; 285 error = gpio_pic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol, 286 &trig); 287 if (error != 0) 288 return (error); 289 if (gi->gi_irq != irq) 290 return (EINVAL); 291 292 /* Compare config if this is not first setup. */ 293 if (isrc->isrc_handlers != 0) { 294 if (pol != gi->gi_pol || trig != gi->gi_trig) 295 return (EINVAL); 296 else 297 return (0); 298 } 299 300 gi->gi_pol = pol; 301 gi->gi_trig = trig; 302 303 if (trig == INTR_TRIGGER_LEVEL) { 304 if (pol == INTR_POLARITY_LOW) 305 icfg = GPIO_ICR_COND_LOW; 306 else 307 icfg = GPIO_ICR_COND_HIGH; 308 } else { 309 if (pol == INTR_POLARITY_HIGH) 310 icfg = GPIO_ICR_COND_FALL; 311 else 312 icfg = GPIO_ICR_COND_RISE; 313 } 314 315 if (irq < 16) { 316 reg = IMX_GPIO_ICR1_REG; 317 shift = 2 * irq; 318 } else { 319 reg = IMX_GPIO_ICR2_REG; 320 shift = 2 * (irq - 16); 321 } 322 323 mtx_lock_spin(&sc->sc_mtx); 324 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 325 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 326 wrk = READ4(sc, reg); 327 wrk &= ~(0x03 << shift); 328 wrk |= icfg << shift; 329 WRITE4(sc, reg, wrk); 330 mtx_unlock_spin(&sc->sc_mtx); 331 return (0); 332 } 333 334 /* 335 * this is mask_intr 336 */ 337 static void 338 gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 339 { 340 struct imx51_gpio_softc *sc; 341 u_int irq; 342 343 sc = device_get_softc(dev); 344 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 345 346 mtx_lock_spin(&sc->sc_mtx); 347 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 348 mtx_unlock_spin(&sc->sc_mtx); 349 } 350 351 /* 352 * this is unmask_intr 353 */ 354 static void 355 gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 356 { 357 struct imx51_gpio_softc *sc; 358 u_int irq; 359 360 sc = device_get_softc(dev); 361 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 362 363 mtx_lock_spin(&sc->sc_mtx); 364 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 365 mtx_unlock_spin(&sc->sc_mtx); 366 } 367 368 static void 369 gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 370 { 371 struct imx51_gpio_softc *sc; 372 u_int irq; 373 374 sc = device_get_softc(dev); 375 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 376 377 arm_irq_memory_barrier(0); 378 /* EOI. W1C reg so no r-m-w, no locking needed. */ 379 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 380 } 381 382 static void 383 gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 384 { 385 386 arm_irq_memory_barrier(0); 387 gpio_pic_enable_intr(dev, isrc); 388 } 389 390 static void 391 gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 392 { 393 394 gpio_pic_disable_intr(dev, isrc); 395 } 396 397 static int 398 gpio_pic_filter(void *arg) 399 { 400 struct imx51_gpio_softc *sc; 401 struct intr_irqsrc *isrc; 402 uint32_t i, interrupts; 403 404 sc = arg; 405 mtx_lock_spin(&sc->sc_mtx); 406 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); 407 mtx_unlock_spin(&sc->sc_mtx); 408 409 for (i = 0; interrupts != 0; i++, interrupts >>= 1) { 410 if ((interrupts & 0x1) == 0) 411 continue; 412 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc; 413 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { 414 gpio_pic_disable_intr(sc->dev, isrc); 415 gpio_pic_post_filter(sc->dev, isrc); 416 device_printf(sc->dev, "Stray irq %u disabled\n", i); 417 } 418 } 419 420 return (FILTER_HANDLED); 421 } 422 423 /* 424 * Initialize our isrcs and register them with intrng. 425 */ 426 static int 427 gpio_pic_register_isrcs(struct imx51_gpio_softc *sc) 428 { 429 int error; 430 uint32_t irq; 431 const char *name; 432 433 name = device_get_nameunit(sc->dev); 434 for (irq = 0; irq < NGPIO; irq++) { 435 sc->gpio_pic_irqsrc[irq].gi_irq = irq; 436 sc->gpio_pic_irqsrc[irq].gi_pol = INTR_POLARITY_CONFORM; 437 sc->gpio_pic_irqsrc[irq].gi_trig = INTR_TRIGGER_CONFORM; 438 439 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, 440 sc->dev, 0, "%s,%u", name, irq); 441 if (error != 0) { 442 /* XXX call intr_isrc_deregister() */ 443 device_printf(sc->dev, "%s failed", __func__); 444 return (error); 445 } 446 } 447 return (0); 448 } 449 #endif 450 451 /* 452 * 453 */ 454 static void 455 imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 456 unsigned int flags) 457 { 458 u_int newflags; 459 460 mtx_lock_spin(&sc->sc_mtx); 461 462 /* 463 * Manage input/output; other flags not supported yet. 464 * 465 * Note that changes to pin->gp_flags must be acccumulated in newflags 466 * and stored with a single writeback to gp_flags at the end, to enable 467 * unlocked reads of that value elsewhere. 468 */ 469 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 470 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 471 if (flags & GPIO_PIN_OUTPUT) { 472 newflags |= GPIO_PIN_OUTPUT; 473 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 474 } else { 475 newflags |= GPIO_PIN_INPUT; 476 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 477 } 478 pin->gp_flags = newflags; 479 } 480 481 mtx_unlock_spin(&sc->sc_mtx); 482 } 483 484 static device_t 485 imx51_gpio_get_bus(device_t dev) 486 { 487 struct imx51_gpio_softc *sc; 488 489 sc = device_get_softc(dev); 490 491 return (sc->sc_busdev); 492 } 493 494 static int 495 imx51_gpio_pin_max(device_t dev, int *maxpin) 496 { 497 struct imx51_gpio_softc *sc; 498 499 sc = device_get_softc(dev); 500 *maxpin = sc->gpio_npins - 1; 501 502 return (0); 503 } 504 505 static int 506 imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 507 { 508 struct imx51_gpio_softc *sc; 509 510 sc = device_get_softc(dev); 511 512 if (pin >= sc->gpio_npins) 513 return (EINVAL); 514 515 *caps = sc->gpio_pins[pin].gp_caps; 516 517 return (0); 518 } 519 520 static int 521 imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 522 { 523 struct imx51_gpio_softc *sc; 524 525 sc = device_get_softc(dev); 526 527 if (pin >= sc->gpio_npins) 528 return (EINVAL); 529 530 *flags = sc->gpio_pins[pin].gp_flags; 531 532 return (0); 533 } 534 535 static int 536 imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 537 { 538 struct imx51_gpio_softc *sc; 539 540 sc = device_get_softc(dev); 541 if (pin >= sc->gpio_npins) 542 return (EINVAL); 543 544 mtx_lock_spin(&sc->sc_mtx); 545 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 546 mtx_unlock_spin(&sc->sc_mtx); 547 548 return (0); 549 } 550 551 static int 552 imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 553 { 554 struct imx51_gpio_softc *sc; 555 556 sc = device_get_softc(dev); 557 558 if (pin >= sc->gpio_npins) 559 return (EINVAL); 560 561 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 562 563 return (0); 564 } 565 566 static int 567 imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 568 { 569 struct imx51_gpio_softc *sc; 570 571 sc = device_get_softc(dev); 572 573 if (pin >= sc->gpio_npins) 574 return (EINVAL); 575 576 mtx_lock_spin(&sc->sc_mtx); 577 if (value) 578 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); 579 else 580 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin)); 581 mtx_unlock_spin(&sc->sc_mtx); 582 583 return (0); 584 } 585 586 static int 587 imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 588 { 589 struct imx51_gpio_softc *sc; 590 591 sc = device_get_softc(dev); 592 593 if (pin >= sc->gpio_npins) 594 return (EINVAL); 595 596 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; 597 598 return (0); 599 } 600 601 static int 602 imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 603 { 604 struct imx51_gpio_softc *sc; 605 606 sc = device_get_softc(dev); 607 608 if (pin >= sc->gpio_npins) 609 return (EINVAL); 610 611 mtx_lock_spin(&sc->sc_mtx); 612 WRITE4(sc, IMX_GPIO_DR_REG, 613 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); 614 mtx_unlock_spin(&sc->sc_mtx); 615 616 return (0); 617 } 618 619 static int 620 imx51_gpio_probe(device_t dev) 621 { 622 623 if (!ofw_bus_status_okay(dev)) 624 return (ENXIO); 625 626 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 627 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 628 return (BUS_PROBE_DEFAULT); 629 } 630 631 return (ENXIO); 632 } 633 634 static int 635 imx51_gpio_attach(device_t dev) 636 { 637 struct imx51_gpio_softc *sc; 638 int i, irq, unit; 639 640 sc = device_get_softc(dev); 641 sc->dev = dev; 642 sc->gpio_npins = NGPIO; 643 644 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); 645 646 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 647 device_printf(dev, "could not allocate resources\n"); 648 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 649 mtx_destroy(&sc->sc_mtx); 650 return (ENXIO); 651 } 652 653 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 654 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 655 /* 656 * Mask off all interrupts in hardware, then set up interrupt handling. 657 */ 658 WRITE4(sc, IMX_GPIO_IMR_REG, 0); 659 for (irq = 0; irq < 2; irq++) { 660 #ifdef INTRNG 661 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, 662 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { 663 device_printf(dev, 664 "WARNING: unable to register interrupt handler\n"); 665 imx51_gpio_detach(dev); 666 return (ENXIO); 667 } 668 #endif 669 } 670 671 unit = device_get_unit(dev); 672 for (i = 0; i < sc->gpio_npins; i++) { 673 sc->gpio_pins[i].gp_pin = i; 674 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 675 sc->gpio_pins[i].gp_flags = 676 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : 677 GPIO_PIN_INPUT; 678 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 679 "imx_gpio%d.%d", unit, i); 680 } 681 682 #ifdef INTRNG 683 gpio_pic_register_isrcs(sc); 684 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); 685 #endif 686 sc->sc_busdev = gpiobus_attach_bus(dev); 687 688 if (sc->sc_busdev == NULL) { 689 imx51_gpio_detach(dev); 690 return (ENXIO); 691 } 692 693 return (0); 694 } 695 696 static int 697 imx51_gpio_detach(device_t dev) 698 { 699 int irq; 700 struct imx51_gpio_softc *sc; 701 702 sc = device_get_softc(dev); 703 704 gpiobus_detach_bus(dev); 705 for (irq = 1; irq <= 2; irq++) { 706 if (sc->gpio_ih[irq]) 707 bus_teardown_intr(dev, sc->sc_res[irq], sc->gpio_ih[irq]); 708 } 709 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 710 mtx_destroy(&sc->sc_mtx); 711 712 return(0); 713 } 714 715 static device_method_t imx51_gpio_methods[] = { 716 DEVMETHOD(device_probe, imx51_gpio_probe), 717 DEVMETHOD(device_attach, imx51_gpio_attach), 718 DEVMETHOD(device_detach, imx51_gpio_detach), 719 720 #ifdef INTRNG 721 /* Interrupt controller interface */ 722 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), 723 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), 724 DEVMETHOD(pic_map_intr, gpio_pic_map_intr), 725 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), 726 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), 727 DEVMETHOD(pic_post_filter, gpio_pic_post_filter), 728 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), 729 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), 730 #endif 731 732 /* GPIO protocol */ 733 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 734 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 735 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 736 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 737 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 738 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 739 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 740 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 741 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 742 {0, 0}, 743 }; 744 745 static driver_t imx51_gpio_driver = { 746 "gpio", 747 imx51_gpio_methods, 748 sizeof(struct imx51_gpio_softc), 749 }; 750 static devclass_t imx51_gpio_devclass; 751 752 DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass, 753 0, 0); 754