1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Freescale i.MX515 GPIO driver. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/gpio.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/gpio/gpiobusvar.h> 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #include "gpio_if.h" 58 59 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 60 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 61 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \ 62 device_get_nameunit(_sc->sc_dev), "imx_gpio", MTX_DEF) 63 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 64 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 65 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 66 67 #define WRITE4(_sc, _r, _v) \ 68 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 69 #define READ4(_sc, _r) \ 70 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 71 #define SET4(_sc, _r, _m) \ 72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 73 #define CLEAR4(_sc, _r, _m) \ 74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 75 76 /* Registers definition for Freescale i.MX515 GPIO controller */ 77 78 #define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 79 #define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 80 #define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 81 #define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 82 #define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 83 #define GPIO_ICR_COND_LOW 0 84 #define GPIO_ICR_COND_HIGH 1 85 #define GPIO_ICR_COND_RISE 2 86 #define GPIO_ICR_COND_FALL 3 87 #define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 88 #define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 89 #define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 90 91 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 92 #define NGPIO 32 93 94 struct imx51_gpio_softc { 95 device_t dev; 96 device_t sc_busdev; 97 struct mtx sc_mtx; 98 struct resource *sc_res[11]; /* 1 x mem, 2 x IRQ, 8 x IRQ */ 99 void *gpio_ih[11]; /* 1 ptr is not a big waste */ 100 int sc_l_irq; /* Last irq resource */ 101 bus_space_tag_t sc_iot; 102 bus_space_handle_t sc_ioh; 103 int gpio_npins; 104 struct gpio_pin gpio_pins[NGPIO]; 105 }; 106 107 static struct ofw_compat_data compat_data[] = { 108 {"fsl,imx6q-gpio", 1}, 109 {"fsl,imx53-gpio", 1}, 110 {"fsl,imx51-gpio", 1}, 111 {NULL, 0} 112 }; 113 114 static struct resource_spec imx_gpio_spec[] = { 115 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 116 { SYS_RES_IRQ, 0, RF_ACTIVE }, 117 { SYS_RES_IRQ, 1, RF_ACTIVE }, 118 { -1, 0 } 119 }; 120 121 static struct resource_spec imx_gpio0irq_spec[] = { 122 { SYS_RES_IRQ, 2, RF_ACTIVE }, 123 { SYS_RES_IRQ, 3, RF_ACTIVE }, 124 { SYS_RES_IRQ, 4, RF_ACTIVE }, 125 { SYS_RES_IRQ, 5, RF_ACTIVE }, 126 { SYS_RES_IRQ, 6, RF_ACTIVE }, 127 { SYS_RES_IRQ, 7, RF_ACTIVE }, 128 { SYS_RES_IRQ, 8, RF_ACTIVE }, 129 { SYS_RES_IRQ, 9, RF_ACTIVE }, 130 { -1, 0 } 131 }; 132 133 /* 134 * Helpers 135 */ 136 static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 137 struct gpio_pin *, uint32_t); 138 139 /* 140 * Driver stuff 141 */ 142 static int imx51_gpio_probe(device_t); 143 static int imx51_gpio_attach(device_t); 144 static int imx51_gpio_detach(device_t); 145 static int imx51_gpio_intr(void *); 146 147 /* 148 * GPIO interface 149 */ 150 static device_t imx51_gpio_get_bus(device_t); 151 static int imx51_gpio_pin_max(device_t, int *); 152 static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 153 static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 154 static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 155 static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 156 static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 157 static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 158 static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 159 160 static void 161 imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 162 unsigned int flags) 163 { 164 165 GPIO_LOCK(sc); 166 167 /* 168 * Manage input/output 169 */ 170 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 171 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 172 if (flags & GPIO_PIN_OUTPUT) { 173 pin->gp_flags |= GPIO_PIN_OUTPUT; 174 SET4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin)); 175 } 176 else { 177 pin->gp_flags |= GPIO_PIN_INPUT; 178 CLEAR4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin)); 179 } 180 } 181 182 GPIO_UNLOCK(sc); 183 } 184 185 static device_t 186 imx51_gpio_get_bus(device_t dev) 187 { 188 struct imx51_gpio_softc *sc; 189 190 sc = device_get_softc(dev); 191 192 return (sc->sc_busdev); 193 } 194 195 static int 196 imx51_gpio_pin_max(device_t dev, int *maxpin) 197 { 198 199 *maxpin = NGPIO - 1; 200 return (0); 201 } 202 203 static int 204 imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 205 { 206 struct imx51_gpio_softc *sc; 207 int i; 208 209 sc = device_get_softc(dev); 210 for (i = 0; i < sc->gpio_npins; i++) { 211 if (sc->gpio_pins[i].gp_pin == pin) 212 break; 213 } 214 215 if (i >= sc->gpio_npins) 216 return (EINVAL); 217 218 GPIO_LOCK(sc); 219 *caps = sc->gpio_pins[i].gp_caps; 220 GPIO_UNLOCK(sc); 221 222 return (0); 223 } 224 225 static int 226 imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 227 { 228 struct imx51_gpio_softc *sc; 229 int i; 230 231 sc = device_get_softc(dev); 232 for (i = 0; i < sc->gpio_npins; i++) { 233 if (sc->gpio_pins[i].gp_pin == pin) 234 break; 235 } 236 237 if (i >= sc->gpio_npins) 238 return (EINVAL); 239 240 GPIO_LOCK(sc); 241 *flags = sc->gpio_pins[i].gp_flags; 242 GPIO_UNLOCK(sc); 243 244 return (0); 245 } 246 247 static int 248 imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 249 { 250 struct imx51_gpio_softc *sc; 251 int i; 252 253 sc = device_get_softc(dev); 254 for (i = 0; i < sc->gpio_npins; i++) { 255 if (sc->gpio_pins[i].gp_pin == pin) 256 break; 257 } 258 259 if (i >= sc->gpio_npins) 260 return (EINVAL); 261 262 GPIO_LOCK(sc); 263 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME); 264 GPIO_UNLOCK(sc); 265 266 return (0); 267 } 268 269 static int 270 imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 271 { 272 struct imx51_gpio_softc *sc; 273 int i; 274 275 sc = device_get_softc(dev); 276 for (i = 0; i < sc->gpio_npins; i++) { 277 if (sc->gpio_pins[i].gp_pin == pin) 278 break; 279 } 280 281 if (i >= sc->gpio_npins) 282 return (EINVAL); 283 284 imx51_gpio_pin_configure(sc, &sc->gpio_pins[i], flags); 285 286 return (0); 287 } 288 289 static int 290 imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 291 { 292 struct imx51_gpio_softc *sc; 293 int i; 294 295 sc = device_get_softc(dev); 296 for (i = 0; i < sc->gpio_npins; i++) { 297 if (sc->gpio_pins[i].gp_pin == pin) 298 break; 299 } 300 301 if (i >= sc->gpio_npins) 302 return (EINVAL); 303 304 GPIO_LOCK(sc); 305 if (value) 306 SET4(sc, IMX_GPIO_DR_REG, (1 << i)); 307 else 308 CLEAR4(sc, IMX_GPIO_DR_REG, (1 << i)); 309 GPIO_UNLOCK(sc); 310 311 return (0); 312 } 313 314 static int 315 imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 316 { 317 struct imx51_gpio_softc *sc; 318 int i; 319 320 sc = device_get_softc(dev); 321 for (i = 0; i < sc->gpio_npins; i++) { 322 if (sc->gpio_pins[i].gp_pin == pin) 323 break; 324 } 325 326 if (i >= sc->gpio_npins) 327 return (EINVAL); 328 329 GPIO_LOCK(sc); 330 *val = (READ4(sc, IMX_GPIO_DR_REG) >> i) & 1; 331 GPIO_UNLOCK(sc); 332 333 return (0); 334 } 335 336 static int 337 imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 338 { 339 struct imx51_gpio_softc *sc; 340 int i; 341 342 sc = device_get_softc(dev); 343 for (i = 0; i < sc->gpio_npins; i++) { 344 if (sc->gpio_pins[i].gp_pin == pin) 345 break; 346 } 347 348 if (i >= sc->gpio_npins) 349 return (EINVAL); 350 351 GPIO_LOCK(sc); 352 WRITE4(sc, IMX_GPIO_DR_REG, 353 (READ4(sc, IMX_GPIO_DR_REG) ^ (1 << i))); 354 GPIO_UNLOCK(sc); 355 356 return (0); 357 } 358 359 static int 360 imx51_gpio_intr(void *arg) 361 { 362 struct imx51_gpio_softc *sc; 363 uint32_t input, value; 364 365 sc = arg; 366 input = READ4(sc, IMX_GPIO_ISR_REG); 367 value = input & READ4(sc, IMX_GPIO_IMR_REG); 368 WRITE4(sc, IMX_GPIO_ISR_REG, input); 369 370 if (!value) 371 goto intr_done; 372 373 /* TODO: interrupt handling */ 374 375 intr_done: 376 return (FILTER_HANDLED); 377 } 378 379 static int 380 imx51_gpio_probe(device_t dev) 381 { 382 383 if (!ofw_bus_status_okay(dev)) 384 return (ENXIO); 385 386 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 387 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 388 return (BUS_PROBE_DEFAULT); 389 } 390 391 return (ENXIO); 392 } 393 394 static int 395 imx51_gpio_attach(device_t dev) 396 { 397 struct imx51_gpio_softc *sc; 398 int i, irq; 399 400 sc = device_get_softc(dev); 401 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 402 403 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 404 device_printf(dev, "could not allocate resources\n"); 405 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 406 mtx_destroy(&sc->sc_mtx); 407 return (ENXIO); 408 } 409 410 sc->dev = dev; 411 sc->gpio_npins = NGPIO; 412 sc->sc_l_irq = 2; 413 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 414 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 415 416 if (bus_alloc_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]) == 0) { 417 /* 418 * First GPIO unit able to serve +8 interrupts for 8 first 419 * pins. 420 */ 421 sc->sc_l_irq = 10; 422 } 423 424 for (irq = 1; irq <= sc->sc_l_irq; irq ++) { 425 if ((bus_setup_intr(dev, sc->sc_res[irq], INTR_TYPE_MISC, 426 imx51_gpio_intr, NULL, sc, &sc->gpio_ih[irq]))) { 427 device_printf(dev, 428 "WARNING: unable to register interrupt handler\n"); 429 imx51_gpio_detach(dev); 430 return (ENXIO); 431 } 432 } 433 434 for (i = 0; i < sc->gpio_npins; i++) { 435 sc->gpio_pins[i].gp_pin = i; 436 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 437 sc->gpio_pins[i].gp_flags = 438 (READ4(sc, IMX_GPIO_OE_REG) & (1 << i)) ? GPIO_PIN_OUTPUT: 439 GPIO_PIN_INPUT; 440 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 441 "imx_gpio%d.%d", device_get_unit(dev), i); 442 } 443 sc->sc_busdev = gpiobus_attach_bus(dev); 444 if (sc->sc_busdev == NULL) { 445 imx51_gpio_detach(dev); 446 return (ENXIO); 447 } 448 449 return (0); 450 } 451 452 static int 453 imx51_gpio_detach(device_t dev) 454 { 455 int irq; 456 struct imx51_gpio_softc *sc; 457 458 sc = device_get_softc(dev); 459 460 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 461 462 gpiobus_detach_bus(dev); 463 for (irq = 1; irq <= sc->sc_l_irq; irq ++) { 464 if (sc->gpio_ih[irq]) 465 bus_teardown_intr(dev, sc->sc_res[irq], sc->gpio_ih[irq]); 466 } 467 bus_release_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]); 468 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 469 mtx_destroy(&sc->sc_mtx); 470 471 return(0); 472 } 473 474 static device_method_t imx51_gpio_methods[] = { 475 DEVMETHOD(device_probe, imx51_gpio_probe), 476 DEVMETHOD(device_attach, imx51_gpio_attach), 477 DEVMETHOD(device_detach, imx51_gpio_detach), 478 479 /* GPIO protocol */ 480 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 481 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 482 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 483 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 484 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 485 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 486 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 487 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 488 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 489 {0, 0}, 490 }; 491 492 static driver_t imx51_gpio_driver = { 493 "gpio", 494 imx51_gpio_methods, 495 sizeof(struct imx51_gpio_softc), 496 }; 497 static devclass_t imx51_gpio_devclass; 498 499 DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass, 500 0, 0); 501