1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * i.MX6 Synchronous Serial Interface (SSI) 29 * 30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual, 31 * Rev. 1, 04/2013 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/chip.h> 49 #include <mixer_if.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <machine/bus.h> 56 #include <machine/cpu.h> 57 #include <machine/intr.h> 58 59 #include <arm/freescale/imx/imx6_sdma.h> 60 #include <arm/freescale/imx/imx6_anatopvar.h> 61 #include <arm/freescale/imx/imx_ccmvar.h> 62 63 #define READ4(_sc, _reg) \ 64 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 65 #define WRITE4(_sc, _reg, _val) \ 66 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 67 68 #define SSI_NCHANNELS 1 69 70 /* i.MX6 SSI registers */ 71 72 #define SSI_STX0 0x00 /* Transmit Data Register n */ 73 #define SSI_STX1 0x04 /* Transmit Data Register n */ 74 #define SSI_SRX0 0x08 /* Receive Data Register n */ 75 #define SSI_SRX1 0x0C /* Receive Data Register n */ 76 #define SSI_SCR 0x10 /* Control Register */ 77 #define SCR_I2S_MODE_S 5 /* I2S Mode Select. */ 78 #define SCR_I2S_MODE_M 0x3 79 #define SCR_SYN (1 << 4) 80 #define SCR_NET (1 << 3) /* Network mode */ 81 #define SCR_RE (1 << 2) /* Receive Enable. */ 82 #define SCR_TE (1 << 1) /* Transmit Enable. */ 83 #define SCR_SSIEN (1 << 0) /* SSI Enable */ 84 #define SSI_SISR 0x14 /* Interrupt Status Register */ 85 #define SSI_SIER 0x18 /* Interrupt Enable Register */ 86 #define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */ 87 #define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */ 88 #define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */ 89 #define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */ 90 #define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */ 91 #define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */ 92 #define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */ 93 #define SSI_STCR 0x1C /* Transmit Configuration Register */ 94 #define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */ 95 #define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */ 96 #define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */ 97 #define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */ 98 #define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */ 99 #define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */ 100 #define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */ 101 #define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */ 102 #define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */ 103 #define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */ 104 #define SSI_SRCR 0x20 /* Receive Configuration Register */ 105 #define SSI_STCCR 0x24 /* Transmit Clock Control Register */ 106 #define STCCR_DIV2 (1 << 18) /* Divide By 2. */ 107 #define STCCR_PSR (1 << 17) /* Divide clock by 8. */ 108 #define WL3_WL0_S 13 109 #define WL3_WL0_M 0xf 110 #define DC4_DC0_S 8 111 #define DC4_DC0_M 0x1f 112 #define PM7_PM0_S 0 113 #define PM7_PM0_M 0xff 114 #define SSI_SRCCR 0x28 /* Receive Clock Control Register */ 115 #define SSI_SFCSR 0x2C /* FIFO Control/Status Register */ 116 #define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */ 117 #define SFCSR_RFWM1_M 0xf 118 #define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */ 119 #define SFCSR_TFWM1_M 0xf 120 #define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */ 121 #define SFCSR_RFWM0_M 0xf 122 #define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */ 123 #define SFCSR_TFWM0_M 0xf 124 #define SSI_SACNT 0x38 /* AC97 Control Register */ 125 #define SSI_SACADD 0x3C /* AC97 Command Address Register */ 126 #define SSI_SACDAT 0x40 /* AC97 Command Data Register */ 127 #define SSI_SATAG 0x44 /* AC97 Tag Register */ 128 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */ 129 #define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */ 130 #define SSI_SACCST 0x50 /* AC97 Channel Status Register */ 131 #define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */ 132 #define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */ 133 134 static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio"); 135 136 uint32_t ssi_dma_intr(void *arg, int chn); 137 138 struct ssi_rate { 139 uint32_t speed; 140 uint32_t mfi; /* PLL4 Multiplication Factor Integer */ 141 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */ 142 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */ 143 /* More dividers to configure can be added here */ 144 }; 145 146 static struct ssi_rate rate_map[] = { 147 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */ 148 /* TODO: add more frequences */ 149 { 0, 0 }, 150 }; 151 152 /* 153 * i.MX6 example bit clock formula 154 * 155 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz = 156 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1) 157 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 158 * | | | | | | | | | | | 159 * Fref ------/ | | | | | | | | | | 160 * PLL4 div select -/ | | | | | | | | | 161 * PLL4 num --------------/ | | | | | | | | 162 * PLL4 denom -------------------/ | | | | | | | 163 * PLL4 post div ---------------------/ | | | | | | 164 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | | 165 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | | 166 * SSI PM7_PM0_S ---------------------------------/ | | | 167 * SSI Fixed divider ---------------------------------/ | | 168 * SSI DIV2 ----------------------------------------------/ | 169 * SSI PSR (prescaler /1 or /8) ------------------------------/ 170 * 171 * MCLK (Master clock) depends on DAC, usually BCLK * 4 172 */ 173 174 struct sc_info { 175 struct resource *res[2]; 176 bus_space_tag_t bst; 177 bus_space_handle_t bsh; 178 device_t dev; 179 struct mtx *lock; 180 void *ih; 181 int pos; 182 int dma_size; 183 bus_dma_tag_t dma_tag; 184 bus_dmamap_t dma_map; 185 bus_addr_t buf_base_phys; 186 uint32_t *buf_base; 187 struct sdma_conf *conf; 188 struct ssi_rate *sr; 189 struct sdma_softc *sdma_sc; 190 int sdma_ev_rx; 191 int sdma_ev_tx; 192 int sdma_channel; 193 }; 194 195 /* Channel registers */ 196 struct sc_chinfo { 197 struct snd_dbuf *buffer; 198 struct pcm_channel *channel; 199 struct sc_pcminfo *parent; 200 201 /* Channel information */ 202 uint32_t dir; 203 uint32_t format; 204 205 /* Flags */ 206 uint32_t run; 207 }; 208 209 /* PCM device private data */ 210 struct sc_pcminfo { 211 device_t dev; 212 uint32_t (*ih)(struct sc_pcminfo *scp); 213 uint32_t chnum; 214 struct sc_chinfo chan[SSI_NCHANNELS]; 215 struct sc_info *sc; 216 }; 217 218 static struct resource_spec ssi_spec[] = { 219 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 220 { SYS_RES_IRQ, 0, RF_ACTIVE }, 221 { -1, 0 } 222 }; 223 224 static int setup_dma(struct sc_pcminfo *scp); 225 static void setup_ssi(struct sc_info *); 226 static void ssi_configure_clock(struct sc_info *); 227 228 /* 229 * Mixer interface. 230 */ 231 232 static int 233 ssimixer_init(struct snd_mixer *m) 234 { 235 struct sc_pcminfo *scp; 236 struct sc_info *sc; 237 int mask; 238 239 scp = mix_getdevinfo(m); 240 sc = scp->sc; 241 242 if (sc == NULL) 243 return -1; 244 245 mask = SOUND_MASK_PCM; 246 mask |= SOUND_MASK_VOLUME; 247 248 snd_mtxlock(sc->lock); 249 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); 250 mix_setdevs(m, mask); 251 snd_mtxunlock(sc->lock); 252 253 return (0); 254 } 255 256 static int 257 ssimixer_set(struct snd_mixer *m, unsigned dev, 258 unsigned left, unsigned right) 259 { 260 struct sc_pcminfo *scp; 261 262 scp = mix_getdevinfo(m); 263 264 /* Here we can configure hardware volume on our DAC */ 265 266 #if 1 267 device_printf(scp->dev, "ssimixer_set() %d %d\n", 268 left, right); 269 #endif 270 271 return (0); 272 } 273 274 static kobj_method_t ssimixer_methods[] = { 275 KOBJMETHOD(mixer_init, ssimixer_init), 276 KOBJMETHOD(mixer_set, ssimixer_set), 277 KOBJMETHOD_END 278 }; 279 MIXER_DECLARE(ssimixer); 280 281 282 /* 283 * Channel interface. 284 */ 285 286 static void * 287 ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 288 struct pcm_channel *c, int dir) 289 { 290 struct sc_pcminfo *scp; 291 struct sc_chinfo *ch; 292 struct sc_info *sc; 293 294 scp = (struct sc_pcminfo *)devinfo; 295 sc = scp->sc; 296 297 snd_mtxlock(sc->lock); 298 ch = &scp->chan[0]; 299 ch->dir = dir; 300 ch->run = 0; 301 ch->buffer = b; 302 ch->channel = c; 303 ch->parent = scp; 304 snd_mtxunlock(sc->lock); 305 306 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) { 307 device_printf(scp->dev, "Can't setup sndbuf.\n"); 308 return NULL; 309 } 310 311 return ch; 312 } 313 314 static int 315 ssichan_free(kobj_t obj, void *data) 316 { 317 struct sc_chinfo *ch = data; 318 struct sc_pcminfo *scp = ch->parent; 319 struct sc_info *sc = scp->sc; 320 321 #if 0 322 device_printf(scp->dev, "ssichan_free()\n"); 323 #endif 324 325 snd_mtxlock(sc->lock); 326 /* TODO: free channel buffer */ 327 snd_mtxunlock(sc->lock); 328 329 return (0); 330 } 331 332 static int 333 ssichan_setformat(kobj_t obj, void *data, uint32_t format) 334 { 335 struct sc_chinfo *ch = data; 336 337 ch->format = format; 338 339 return (0); 340 } 341 342 static uint32_t 343 ssichan_setspeed(kobj_t obj, void *data, uint32_t speed) 344 { 345 struct sc_pcminfo *scp; 346 struct sc_chinfo *ch; 347 struct ssi_rate *sr; 348 struct sc_info *sc; 349 int threshold; 350 int i; 351 352 ch = data; 353 scp = ch->parent; 354 sc = scp->sc; 355 356 sr = NULL; 357 358 /* First look for equal frequency. */ 359 for (i = 0; rate_map[i].speed != 0; i++) { 360 if (rate_map[i].speed == speed) 361 sr = &rate_map[i]; 362 } 363 364 /* If no match, just find nearest. */ 365 if (sr == NULL) { 366 for (i = 0; rate_map[i].speed != 0; i++) { 367 sr = &rate_map[i]; 368 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ? 369 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0); 370 if (speed < threshold) 371 break; 372 } 373 } 374 375 sc->sr = sr; 376 377 ssi_configure_clock(sc); 378 379 return (sr->speed); 380 } 381 382 static void 383 ssi_configure_clock(struct sc_info *sc) 384 { 385 struct ssi_rate *sr; 386 387 sr = sc->sr; 388 389 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd); 390 391 /* Configure other dividers here, if any */ 392 } 393 394 static uint32_t 395 ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 396 { 397 struct sc_chinfo *ch = data; 398 struct sc_pcminfo *scp = ch->parent; 399 struct sc_info *sc = scp->sc; 400 401 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize); 402 403 setup_dma(scp); 404 405 return (sndbuf_getblksz(ch->buffer)); 406 } 407 408 uint32_t 409 ssi_dma_intr(void *arg, int chn) 410 { 411 struct sc_pcminfo *scp; 412 struct sdma_conf *conf; 413 struct sc_chinfo *ch; 414 struct sc_info *sc; 415 int bufsize; 416 417 scp = arg; 418 ch = &scp->chan[0]; 419 sc = scp->sc; 420 conf = sc->conf; 421 422 bufsize = sndbuf_getsize(ch->buffer); 423 424 sc->pos += conf->period; 425 if (sc->pos >= bufsize) 426 sc->pos -= bufsize; 427 428 if (ch->run) 429 chn_intr(ch->channel); 430 431 return (0); 432 } 433 434 static int 435 find_sdma_controller(struct sc_info *sc) 436 { 437 struct sdma_softc *sdma_sc; 438 phandle_t node, sdma_node; 439 device_t sdma_dev; 440 int dts_value[8]; 441 int len; 442 443 if ((node = ofw_bus_get_node(sc->dev)) == -1) 444 return (ENXIO); 445 446 if ((len = OF_getproplen(node, "dmas")) <= 0) 447 return (ENXIO); 448 449 OF_getencprop(node, "dmas", &dts_value, len); 450 451 sc->sdma_ev_rx = dts_value[1]; 452 sc->sdma_ev_tx = dts_value[5]; 453 454 sdma_node = OF_node_from_xref(dts_value[0]); 455 456 sdma_sc = NULL; 457 458 sdma_dev = devclass_get_device(devclass_find("sdma"), 0); 459 if (sdma_dev) 460 sdma_sc = device_get_softc(sdma_dev); 461 462 if (sdma_sc == NULL) { 463 device_printf(sc->dev, "No sDMA found. Can't operate\n"); 464 return (ENXIO); 465 } 466 467 sc->sdma_sc = sdma_sc; 468 469 return (0); 470 }; 471 472 static int 473 setup_dma(struct sc_pcminfo *scp) 474 { 475 struct sdma_conf *conf; 476 struct sc_chinfo *ch; 477 struct sc_info *sc; 478 int fmt; 479 480 ch = &scp->chan[0]; 481 sc = scp->sc; 482 conf = sc->conf; 483 484 conf->ih = ssi_dma_intr; 485 conf->ih_user = scp; 486 conf->saddr = sc->buf_base_phys; 487 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0; 488 conf->event = sc->sdma_ev_tx; /* SDMA TX event */ 489 conf->period = sndbuf_getblksz(ch->buffer); 490 conf->num_bd = sndbuf_getblkcnt(ch->buffer); 491 492 /* 493 * Word Length 494 * Can be 32, 24, 16 or 8 for sDMA. 495 * 496 * SSI supports 24 at max. 497 */ 498 499 fmt = sndbuf_getfmt(ch->buffer); 500 501 if (fmt & AFMT_16BIT) { 502 conf->word_length = 16; 503 conf->command = CMD_2BYTES; 504 } else if (fmt & AFMT_24BIT) { 505 conf->word_length = 24; 506 conf->command = CMD_3BYTES; 507 } else { 508 device_printf(sc->dev, "Unknown format\n"); 509 return (-1); 510 } 511 512 return (0); 513 } 514 515 static int 516 ssi_start(struct sc_pcminfo *scp) 517 { 518 struct sc_info *sc; 519 int reg; 520 521 sc = scp->sc; 522 523 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) { 524 device_printf(sc->dev, "Can't configure sDMA\n"); 525 return (-1); 526 } 527 528 /* Enable DMA interrupt */ 529 reg = (SIER_TDMAE); 530 WRITE4(sc, SSI_SIER, reg); 531 532 sdma_start(sc->sdma_channel); 533 534 return (0); 535 } 536 537 static int 538 ssi_stop(struct sc_pcminfo *scp) 539 { 540 struct sc_info *sc; 541 int reg; 542 543 sc = scp->sc; 544 545 reg = READ4(sc, SSI_SIER); 546 reg &= ~(SIER_TDMAE); 547 WRITE4(sc, SSI_SIER, reg); 548 549 sdma_stop(sc->sdma_channel); 550 551 bzero(sc->buf_base, sc->dma_size); 552 553 return (0); 554 } 555 556 static int 557 ssichan_trigger(kobj_t obj, void *data, int go) 558 { 559 struct sc_pcminfo *scp; 560 struct sc_chinfo *ch; 561 struct sc_info *sc; 562 563 ch = data; 564 scp = ch->parent; 565 sc = scp->sc; 566 567 snd_mtxlock(sc->lock); 568 569 switch (go) { 570 case PCMTRIG_START: 571 #if 0 572 device_printf(scp->dev, "trigger start\n"); 573 #endif 574 ch->run = 1; 575 576 ssi_start(scp); 577 578 break; 579 580 case PCMTRIG_STOP: 581 case PCMTRIG_ABORT: 582 #if 0 583 device_printf(scp->dev, "trigger stop or abort\n"); 584 #endif 585 ch->run = 0; 586 587 ssi_stop(scp); 588 589 break; 590 } 591 592 snd_mtxunlock(sc->lock); 593 594 return (0); 595 } 596 597 static uint32_t 598 ssichan_getptr(kobj_t obj, void *data) 599 { 600 struct sc_pcminfo *scp; 601 struct sc_chinfo *ch; 602 struct sc_info *sc; 603 604 ch = data; 605 scp = ch->parent; 606 sc = scp->sc; 607 608 return (sc->pos); 609 } 610 611 static uint32_t ssi_pfmt[] = { 612 SND_FORMAT(AFMT_S24_LE, 2, 0), 613 0 614 }; 615 616 static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0}; 617 618 static struct pcmchan_caps * 619 ssichan_getcaps(kobj_t obj, void *data) 620 { 621 622 return (&ssi_pcaps); 623 } 624 625 static kobj_method_t ssichan_methods[] = { 626 KOBJMETHOD(channel_init, ssichan_init), 627 KOBJMETHOD(channel_free, ssichan_free), 628 KOBJMETHOD(channel_setformat, ssichan_setformat), 629 KOBJMETHOD(channel_setspeed, ssichan_setspeed), 630 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize), 631 KOBJMETHOD(channel_trigger, ssichan_trigger), 632 KOBJMETHOD(channel_getptr, ssichan_getptr), 633 KOBJMETHOD(channel_getcaps, ssichan_getcaps), 634 KOBJMETHOD_END 635 }; 636 CHANNEL_DECLARE(ssichan); 637 638 static int 639 ssi_probe(device_t dev) 640 { 641 642 if (!ofw_bus_status_okay(dev)) 643 return (ENXIO); 644 645 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi")) 646 return (ENXIO); 647 648 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)"); 649 return (BUS_PROBE_DEFAULT); 650 } 651 652 static void 653 ssi_intr(void *arg) 654 { 655 struct sc_pcminfo *scp; 656 struct sc_chinfo *ch; 657 struct sc_info *sc; 658 659 scp = arg; 660 sc = scp->sc; 661 ch = &scp->chan[0]; 662 663 /* We don't use SSI interrupt */ 664 #if 0 665 device_printf(sc->dev, "SSI Intr 0x%08x\n", 666 READ4(sc, SSI_SISR)); 667 #endif 668 } 669 670 static void 671 setup_ssi(struct sc_info *sc) 672 { 673 int reg; 674 675 reg = READ4(sc, SSI_STCCR); 676 reg &= ~(WL3_WL0_M << WL3_WL0_S); 677 reg |= (0xb << WL3_WL0_S); /* 24 bit */ 678 reg &= ~(DC4_DC0_M << DC4_DC0_S); 679 reg |= (1 << DC4_DC0_S); /* 2 words per frame */ 680 reg &= ~(STCCR_DIV2); /* Divide by 1 */ 681 reg &= ~(STCCR_PSR); /* Divide by 1 */ 682 reg &= ~(PM7_PM0_M << PM7_PM0_S); 683 reg |= (1 << PM7_PM0_S); /* Divide by 2 */ 684 WRITE4(sc, SSI_STCCR, reg); 685 686 reg = READ4(sc, SSI_SFCSR); 687 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S); 688 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */ 689 WRITE4(sc, SSI_SFCSR, reg); 690 691 reg = READ4(sc, SSI_STCR); 692 reg |= (STCR_TFEN0); 693 reg &= ~(STCR_TFEN1); 694 reg &= ~(STCR_TSHFD); /* MSB */ 695 reg |= (STCR_TXBIT0); 696 reg |= (STCR_TXDIR | STCR_TFDIR); 697 reg |= (STCR_TSCKP); /* falling edge */ 698 reg |= (STCR_TFSI); 699 reg &= ~(STCR_TFSI); /* active high frame sync */ 700 reg &= ~(STCR_TFSL); 701 reg |= STCR_TEFS; 702 WRITE4(sc, SSI_STCR, reg); 703 704 reg = READ4(sc, SSI_SCR); 705 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */ 706 reg |= (SCR_SSIEN | SCR_TE); 707 reg |= (SCR_NET); 708 reg |= (SCR_SYN); 709 WRITE4(sc, SSI_SCR, reg); 710 } 711 712 static void 713 ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 714 { 715 bus_addr_t *addr; 716 717 if (err) 718 return; 719 720 addr = (bus_addr_t*)arg; 721 *addr = segs[0].ds_addr; 722 } 723 724 static int 725 ssi_attach(device_t dev) 726 { 727 char status[SND_STATUSLEN]; 728 struct sc_pcminfo *scp; 729 struct sc_info *sc; 730 int err; 731 732 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 733 sc->dev = dev; 734 sc->sr = &rate_map[0]; 735 sc->pos = 0; 736 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO); 737 738 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc"); 739 if (sc->lock == NULL) { 740 device_printf(dev, "Can't create mtx\n"); 741 return (ENXIO); 742 } 743 744 if (bus_alloc_resources(dev, ssi_spec, sc->res)) { 745 device_printf(dev, "could not allocate resources\n"); 746 return (ENXIO); 747 } 748 749 /* Memory interface */ 750 sc->bst = rman_get_bustag(sc->res[0]); 751 sc->bsh = rman_get_bushandle(sc->res[0]); 752 753 /* SDMA */ 754 if (find_sdma_controller(sc)) { 755 device_printf(dev, "could not find active SDMA\n"); 756 return (ENXIO); 757 } 758 759 /* Setup PCM */ 760 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 761 scp->sc = sc; 762 scp->dev = dev; 763 764 /* 765 * Maximum possible DMA buffer. 766 * Will be used partially to match 24 bit word. 767 */ 768 sc->dma_size = 131072; 769 770 /* 771 * Must use dma_size boundary as modulo feature required. 772 * Modulo feature allows setup circular buffer. 773 */ 774 775 err = bus_dma_tag_create( 776 bus_get_dma_tag(sc->dev), 777 4, sc->dma_size, /* alignment, boundary */ 778 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 779 BUS_SPACE_MAXADDR, /* highaddr */ 780 NULL, NULL, /* filter, filterarg */ 781 sc->dma_size, 1, /* maxsize, nsegments */ 782 sc->dma_size, 0, /* maxsegsize, flags */ 783 NULL, NULL, /* lockfunc, lockarg */ 784 &sc->dma_tag); 785 786 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base, 787 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map); 788 if (err) { 789 device_printf(dev, "cannot allocate framebuffer\n"); 790 return (ENXIO); 791 } 792 793 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base, 794 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT); 795 if (err) { 796 device_printf(dev, "cannot load DMA map\n"); 797 return (ENXIO); 798 } 799 800 bzero(sc->buf_base, sc->dma_size); 801 802 /* Setup interrupt handler */ 803 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV, 804 NULL, ssi_intr, scp, &sc->ih); 805 if (err) { 806 device_printf(dev, "Unable to alloc interrupt resource.\n"); 807 return (ENXIO); 808 } 809 810 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 811 812 err = pcm_register(dev, scp, 1, 0); 813 if (err) { 814 device_printf(dev, "Can't register pcm.\n"); 815 return (ENXIO); 816 } 817 818 scp->chnum = 0; 819 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp); 820 scp->chnum++; 821 822 snprintf(status, SND_STATUSLEN, "at simplebus"); 823 pcm_setstatus(dev, status); 824 825 mixer_init(dev, &ssimixer_class, scp); 826 setup_ssi(sc); 827 828 imx_ccm_ssi_configure(dev); 829 830 sc->sdma_channel = sdma_alloc(); 831 if (sc->sdma_channel < 0) { 832 device_printf(sc->dev, "Can't get sDMA channel\n"); 833 return (1); 834 } 835 836 return (0); 837 } 838 839 static device_method_t ssi_pcm_methods[] = { 840 DEVMETHOD(device_probe, ssi_probe), 841 DEVMETHOD(device_attach, ssi_attach), 842 { 0, 0 } 843 }; 844 845 static driver_t ssi_pcm_driver = { 846 "pcm", 847 ssi_pcm_methods, 848 PCM_SOFTC_SIZE, 849 }; 850 851 DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0); 852 MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 853 MODULE_VERSION(ssi, 1); 854