1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * i.MX6 Synchronous Serial Interface (SSI) 29 * 30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual, 31 * Rev. 1, 04/2013 32 */ 33 34 #include <sys/cdefs.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/chip.h> 47 #include <mixer_if.h> 48 49 #include <dev/ofw/openfirm.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <machine/bus.h> 54 #include <machine/cpu.h> 55 #include <machine/intr.h> 56 57 #include <arm/freescale/imx/imx6_sdma.h> 58 #include <arm/freescale/imx/imx6_anatopvar.h> 59 #include <arm/freescale/imx/imx_ccmvar.h> 60 61 #define READ4(_sc, _reg) \ 62 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 63 #define WRITE4(_sc, _reg, _val) \ 64 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 65 66 #define SSI_NCHANNELS 1 67 #define DMAS_TOTAL 8 68 69 /* i.MX6 SSI registers */ 70 71 #define SSI_STX0 0x00 /* Transmit Data Register n */ 72 #define SSI_STX1 0x04 /* Transmit Data Register n */ 73 #define SSI_SRX0 0x08 /* Receive Data Register n */ 74 #define SSI_SRX1 0x0C /* Receive Data Register n */ 75 #define SSI_SCR 0x10 /* Control Register */ 76 #define SCR_I2S_MODE_S 5 /* I2S Mode Select. */ 77 #define SCR_I2S_MODE_M 0x3 78 #define SCR_SYN (1 << 4) 79 #define SCR_NET (1 << 3) /* Network mode */ 80 #define SCR_RE (1 << 2) /* Receive Enable. */ 81 #define SCR_TE (1 << 1) /* Transmit Enable. */ 82 #define SCR_SSIEN (1 << 0) /* SSI Enable */ 83 #define SSI_SISR 0x14 /* Interrupt Status Register */ 84 #define SSI_SIER 0x18 /* Interrupt Enable Register */ 85 #define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */ 86 #define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */ 87 #define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */ 88 #define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */ 89 #define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */ 90 #define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */ 91 #define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */ 92 #define SSI_STCR 0x1C /* Transmit Configuration Register */ 93 #define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */ 94 #define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */ 95 #define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */ 96 #define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */ 97 #define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */ 98 #define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */ 99 #define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */ 100 #define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */ 101 #define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */ 102 #define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */ 103 #define SSI_SRCR 0x20 /* Receive Configuration Register */ 104 #define SSI_STCCR 0x24 /* Transmit Clock Control Register */ 105 #define STCCR_DIV2 (1 << 18) /* Divide By 2. */ 106 #define STCCR_PSR (1 << 17) /* Divide clock by 8. */ 107 #define WL3_WL0_S 13 108 #define WL3_WL0_M 0xf 109 #define DC4_DC0_S 8 110 #define DC4_DC0_M 0x1f 111 #define PM7_PM0_S 0 112 #define PM7_PM0_M 0xff 113 #define SSI_SRCCR 0x28 /* Receive Clock Control Register */ 114 #define SSI_SFCSR 0x2C /* FIFO Control/Status Register */ 115 #define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */ 116 #define SFCSR_RFWM1_M 0xf 117 #define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */ 118 #define SFCSR_TFWM1_M 0xf 119 #define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */ 120 #define SFCSR_RFWM0_M 0xf 121 #define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */ 122 #define SFCSR_TFWM0_M 0xf 123 #define SSI_SACNT 0x38 /* AC97 Control Register */ 124 #define SSI_SACADD 0x3C /* AC97 Command Address Register */ 125 #define SSI_SACDAT 0x40 /* AC97 Command Data Register */ 126 #define SSI_SATAG 0x44 /* AC97 Tag Register */ 127 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */ 128 #define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */ 129 #define SSI_SACCST 0x50 /* AC97 Channel Status Register */ 130 #define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */ 131 #define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */ 132 133 static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio"); 134 135 uint32_t ssi_dma_intr(void *arg, int chn); 136 137 struct ssi_rate { 138 uint32_t speed; 139 uint32_t mfi; /* PLL4 Multiplication Factor Integer */ 140 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */ 141 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */ 142 /* More dividers to configure can be added here */ 143 }; 144 145 static struct ssi_rate rate_map[] = { 146 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */ 147 /* TODO: add more frequences */ 148 { 0, 0 }, 149 }; 150 151 /* 152 * i.MX6 example bit clock formula 153 * 154 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz = 155 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1) 156 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 157 * | | | | | | | | | | | 158 * Fref ------/ | | | | | | | | | | 159 * PLL4 div select -/ | | | | | | | | | 160 * PLL4 num --------------/ | | | | | | | | 161 * PLL4 denom -------------------/ | | | | | | | 162 * PLL4 post div ---------------------/ | | | | | | 163 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | | 164 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | | 165 * SSI PM7_PM0_S ---------------------------------/ | | | 166 * SSI Fixed divider ---------------------------------/ | | 167 * SSI DIV2 ----------------------------------------------/ | 168 * SSI PSR (prescaler /1 or /8) ------------------------------/ 169 * 170 * MCLK (Master clock) depends on DAC, usually BCLK * 4 171 */ 172 173 struct sc_info { 174 struct resource *res[2]; 175 bus_space_tag_t bst; 176 bus_space_handle_t bsh; 177 device_t dev; 178 struct mtx *lock; 179 void *ih; 180 int pos; 181 int dma_size; 182 bus_dma_tag_t dma_tag; 183 bus_dmamap_t dma_map; 184 bus_addr_t buf_base_phys; 185 uint32_t *buf_base; 186 struct sdma_conf *conf; 187 struct ssi_rate *sr; 188 struct sdma_softc *sdma_sc; 189 uint32_t sdma_ev_rx; 190 uint32_t sdma_ev_tx; 191 int sdma_channel; 192 }; 193 194 /* Channel registers */ 195 struct sc_chinfo { 196 struct snd_dbuf *buffer; 197 struct pcm_channel *channel; 198 struct sc_pcminfo *parent; 199 200 /* Channel information */ 201 uint32_t dir; 202 uint32_t format; 203 204 /* Flags */ 205 uint32_t run; 206 }; 207 208 /* PCM device private data */ 209 struct sc_pcminfo { 210 device_t dev; 211 uint32_t (*ih)(struct sc_pcminfo *scp); 212 uint32_t chnum; 213 struct sc_chinfo chan[SSI_NCHANNELS]; 214 struct sc_info *sc; 215 }; 216 217 static struct resource_spec ssi_spec[] = { 218 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 219 { SYS_RES_IRQ, 0, RF_ACTIVE }, 220 { -1, 0 } 221 }; 222 223 static int setup_dma(struct sc_pcminfo *scp); 224 static void setup_ssi(struct sc_info *); 225 static void ssi_configure_clock(struct sc_info *); 226 227 /* 228 * Mixer interface. 229 */ 230 231 static int 232 ssimixer_init(struct snd_mixer *m) 233 { 234 struct sc_pcminfo *scp; 235 struct sc_info *sc; 236 int mask; 237 238 scp = mix_getdevinfo(m); 239 sc = scp->sc; 240 241 if (sc == NULL) 242 return -1; 243 244 mask = SOUND_MASK_PCM; 245 mask |= SOUND_MASK_VOLUME; 246 247 snd_mtxlock(sc->lock); 248 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); 249 mix_setdevs(m, mask); 250 snd_mtxunlock(sc->lock); 251 252 return (0); 253 } 254 255 static int 256 ssimixer_set(struct snd_mixer *m, unsigned dev, 257 unsigned left, unsigned right) 258 { 259 struct sc_pcminfo *scp; 260 261 scp = mix_getdevinfo(m); 262 263 /* Here we can configure hardware volume on our DAC */ 264 265 #if 1 266 device_printf(scp->dev, "ssimixer_set() %d %d\n", 267 left, right); 268 #endif 269 270 return (0); 271 } 272 273 static kobj_method_t ssimixer_methods[] = { 274 KOBJMETHOD(mixer_init, ssimixer_init), 275 KOBJMETHOD(mixer_set, ssimixer_set), 276 KOBJMETHOD_END 277 }; 278 MIXER_DECLARE(ssimixer); 279 280 /* 281 * Channel interface. 282 */ 283 284 static void * 285 ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 286 struct pcm_channel *c, int dir) 287 { 288 struct sc_pcminfo *scp; 289 struct sc_chinfo *ch; 290 struct sc_info *sc; 291 292 scp = (struct sc_pcminfo *)devinfo; 293 sc = scp->sc; 294 295 snd_mtxlock(sc->lock); 296 ch = &scp->chan[0]; 297 ch->dir = dir; 298 ch->run = 0; 299 ch->buffer = b; 300 ch->channel = c; 301 ch->parent = scp; 302 snd_mtxunlock(sc->lock); 303 304 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) { 305 device_printf(scp->dev, "Can't setup sndbuf.\n"); 306 return NULL; 307 } 308 309 return ch; 310 } 311 312 static int 313 ssichan_free(kobj_t obj, void *data) 314 { 315 struct sc_chinfo *ch = data; 316 struct sc_pcminfo *scp = ch->parent; 317 struct sc_info *sc = scp->sc; 318 319 #if 0 320 device_printf(scp->dev, "ssichan_free()\n"); 321 #endif 322 323 snd_mtxlock(sc->lock); 324 /* TODO: free channel buffer */ 325 snd_mtxunlock(sc->lock); 326 327 return (0); 328 } 329 330 static int 331 ssichan_setformat(kobj_t obj, void *data, uint32_t format) 332 { 333 struct sc_chinfo *ch = data; 334 335 ch->format = format; 336 337 return (0); 338 } 339 340 static uint32_t 341 ssichan_setspeed(kobj_t obj, void *data, uint32_t speed) 342 { 343 struct sc_pcminfo *scp; 344 struct sc_chinfo *ch; 345 struct ssi_rate *sr; 346 struct sc_info *sc; 347 int threshold; 348 int i; 349 350 ch = data; 351 scp = ch->parent; 352 sc = scp->sc; 353 354 sr = NULL; 355 356 /* First look for equal frequency. */ 357 for (i = 0; rate_map[i].speed != 0; i++) { 358 if (rate_map[i].speed == speed) 359 sr = &rate_map[i]; 360 } 361 362 /* If no match, just find nearest. */ 363 if (sr == NULL) { 364 for (i = 0; rate_map[i].speed != 0; i++) { 365 sr = &rate_map[i]; 366 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ? 367 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0); 368 if (speed < threshold) 369 break; 370 } 371 } 372 373 sc->sr = sr; 374 375 ssi_configure_clock(sc); 376 377 return (sr->speed); 378 } 379 380 static void 381 ssi_configure_clock(struct sc_info *sc) 382 { 383 struct ssi_rate *sr; 384 385 sr = sc->sr; 386 387 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd); 388 389 /* Configure other dividers here, if any */ 390 } 391 392 static uint32_t 393 ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 394 { 395 struct sc_chinfo *ch = data; 396 struct sc_pcminfo *scp = ch->parent; 397 struct sc_info *sc = scp->sc; 398 399 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize); 400 401 setup_dma(scp); 402 403 return (sndbuf_getblksz(ch->buffer)); 404 } 405 406 uint32_t 407 ssi_dma_intr(void *arg, int chn) 408 { 409 struct sc_pcminfo *scp; 410 struct sdma_conf *conf; 411 struct sc_chinfo *ch; 412 struct sc_info *sc; 413 int bufsize; 414 415 scp = arg; 416 ch = &scp->chan[0]; 417 sc = scp->sc; 418 conf = sc->conf; 419 420 bufsize = sndbuf_getsize(ch->buffer); 421 422 sc->pos += conf->period; 423 if (sc->pos >= bufsize) 424 sc->pos -= bufsize; 425 426 if (ch->run) 427 chn_intr(ch->channel); 428 429 return (0); 430 } 431 432 static int 433 find_sdma_controller(struct sc_info *sc) 434 { 435 struct sdma_softc *sdma_sc; 436 phandle_t node; 437 device_t sdma_dev; 438 pcell_t dts_value[DMAS_TOTAL]; 439 int len; 440 441 if ((node = ofw_bus_get_node(sc->dev)) == -1) 442 return (ENXIO); 443 444 if ((len = OF_getproplen(node, "dmas")) <= 0) 445 return (ENXIO); 446 447 if (len != sizeof(dts_value)) { 448 device_printf(sc->dev, 449 "\"dmas\" property length is invalid: %d (expected %d)", 450 len, sizeof(dts_value)); 451 return (ENXIO); 452 } 453 454 OF_getencprop(node, "dmas", dts_value, sizeof(dts_value)); 455 456 sc->sdma_ev_rx = dts_value[1]; 457 sc->sdma_ev_tx = dts_value[5]; 458 459 sdma_sc = NULL; 460 461 sdma_dev = devclass_get_device(devclass_find("sdma"), 0); 462 if (sdma_dev) 463 sdma_sc = device_get_softc(sdma_dev); 464 465 if (sdma_sc == NULL) { 466 device_printf(sc->dev, "No sDMA found. Can't operate\n"); 467 return (ENXIO); 468 } 469 470 sc->sdma_sc = sdma_sc; 471 472 return (0); 473 }; 474 475 static int 476 setup_dma(struct sc_pcminfo *scp) 477 { 478 struct sdma_conf *conf; 479 struct sc_chinfo *ch; 480 struct sc_info *sc; 481 int fmt; 482 483 ch = &scp->chan[0]; 484 sc = scp->sc; 485 conf = sc->conf; 486 487 conf->ih = ssi_dma_intr; 488 conf->ih_user = scp; 489 conf->saddr = sc->buf_base_phys; 490 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0; 491 conf->event = sc->sdma_ev_tx; /* SDMA TX event */ 492 conf->period = sndbuf_getblksz(ch->buffer); 493 conf->num_bd = sndbuf_getblkcnt(ch->buffer); 494 495 /* 496 * Word Length 497 * Can be 32, 24, 16 or 8 for sDMA. 498 * 499 * SSI supports 24 at max. 500 */ 501 502 fmt = sndbuf_getfmt(ch->buffer); 503 504 if (fmt & AFMT_16BIT) { 505 conf->word_length = 16; 506 conf->command = CMD_2BYTES; 507 } else if (fmt & AFMT_24BIT) { 508 conf->word_length = 24; 509 conf->command = CMD_3BYTES; 510 } else { 511 device_printf(sc->dev, "Unknown format\n"); 512 return (-1); 513 } 514 515 return (0); 516 } 517 518 static int 519 ssi_start(struct sc_pcminfo *scp) 520 { 521 struct sc_info *sc; 522 int reg; 523 524 sc = scp->sc; 525 526 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) { 527 device_printf(sc->dev, "Can't configure sDMA\n"); 528 return (-1); 529 } 530 531 /* Enable DMA interrupt */ 532 reg = (SIER_TDMAE); 533 WRITE4(sc, SSI_SIER, reg); 534 535 sdma_start(sc->sdma_channel); 536 537 return (0); 538 } 539 540 static int 541 ssi_stop(struct sc_pcminfo *scp) 542 { 543 struct sc_info *sc; 544 int reg; 545 546 sc = scp->sc; 547 548 reg = READ4(sc, SSI_SIER); 549 reg &= ~(SIER_TDMAE); 550 WRITE4(sc, SSI_SIER, reg); 551 552 sdma_stop(sc->sdma_channel); 553 554 bzero(sc->buf_base, sc->dma_size); 555 556 return (0); 557 } 558 559 static int 560 ssichan_trigger(kobj_t obj, void *data, int go) 561 { 562 struct sc_pcminfo *scp; 563 struct sc_chinfo *ch; 564 struct sc_info *sc; 565 566 ch = data; 567 scp = ch->parent; 568 sc = scp->sc; 569 570 snd_mtxlock(sc->lock); 571 572 switch (go) { 573 case PCMTRIG_START: 574 #if 0 575 device_printf(scp->dev, "trigger start\n"); 576 #endif 577 ch->run = 1; 578 579 ssi_start(scp); 580 581 break; 582 583 case PCMTRIG_STOP: 584 case PCMTRIG_ABORT: 585 #if 0 586 device_printf(scp->dev, "trigger stop or abort\n"); 587 #endif 588 ch->run = 0; 589 590 ssi_stop(scp); 591 592 break; 593 } 594 595 snd_mtxunlock(sc->lock); 596 597 return (0); 598 } 599 600 static uint32_t 601 ssichan_getptr(kobj_t obj, void *data) 602 { 603 struct sc_pcminfo *scp; 604 struct sc_chinfo *ch; 605 struct sc_info *sc; 606 607 ch = data; 608 scp = ch->parent; 609 sc = scp->sc; 610 611 return (sc->pos); 612 } 613 614 static uint32_t ssi_pfmt[] = { 615 SND_FORMAT(AFMT_S24_LE, 2, 0), 616 0 617 }; 618 619 static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0}; 620 621 static struct pcmchan_caps * 622 ssichan_getcaps(kobj_t obj, void *data) 623 { 624 625 return (&ssi_pcaps); 626 } 627 628 static kobj_method_t ssichan_methods[] = { 629 KOBJMETHOD(channel_init, ssichan_init), 630 KOBJMETHOD(channel_free, ssichan_free), 631 KOBJMETHOD(channel_setformat, ssichan_setformat), 632 KOBJMETHOD(channel_setspeed, ssichan_setspeed), 633 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize), 634 KOBJMETHOD(channel_trigger, ssichan_trigger), 635 KOBJMETHOD(channel_getptr, ssichan_getptr), 636 KOBJMETHOD(channel_getcaps, ssichan_getcaps), 637 KOBJMETHOD_END 638 }; 639 CHANNEL_DECLARE(ssichan); 640 641 static int 642 ssi_probe(device_t dev) 643 { 644 645 if (!ofw_bus_status_okay(dev)) 646 return (ENXIO); 647 648 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi")) 649 return (ENXIO); 650 651 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)"); 652 return (BUS_PROBE_DEFAULT); 653 } 654 655 static void 656 ssi_intr(void *arg) 657 { 658 #if 0 659 struct sc_pcminfo *scp; 660 struct sc_info *sc; 661 662 scp = arg; 663 sc = scp->sc; 664 #endif 665 666 /* We don't use SSI interrupt */ 667 #if 0 668 device_printf(scp->sc->dev, "SSI Intr 0x%08x\n", 669 READ4(sc, SSI_SISR)); 670 #endif 671 } 672 673 static void 674 setup_ssi(struct sc_info *sc) 675 { 676 int reg; 677 678 reg = READ4(sc, SSI_STCCR); 679 reg &= ~(WL3_WL0_M << WL3_WL0_S); 680 reg |= (0xb << WL3_WL0_S); /* 24 bit */ 681 reg &= ~(DC4_DC0_M << DC4_DC0_S); 682 reg |= (1 << DC4_DC0_S); /* 2 words per frame */ 683 reg &= ~(STCCR_DIV2); /* Divide by 1 */ 684 reg &= ~(STCCR_PSR); /* Divide by 1 */ 685 reg &= ~(PM7_PM0_M << PM7_PM0_S); 686 reg |= (1 << PM7_PM0_S); /* Divide by 2 */ 687 WRITE4(sc, SSI_STCCR, reg); 688 689 reg = READ4(sc, SSI_SFCSR); 690 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S); 691 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */ 692 WRITE4(sc, SSI_SFCSR, reg); 693 694 reg = READ4(sc, SSI_STCR); 695 reg |= (STCR_TFEN0); 696 reg &= ~(STCR_TFEN1); 697 reg &= ~(STCR_TSHFD); /* MSB */ 698 reg |= (STCR_TXBIT0); 699 reg |= (STCR_TXDIR | STCR_TFDIR); 700 reg |= (STCR_TSCKP); /* falling edge */ 701 reg |= (STCR_TFSI); 702 reg &= ~(STCR_TFSI); /* active high frame sync */ 703 reg &= ~(STCR_TFSL); 704 reg |= STCR_TEFS; 705 WRITE4(sc, SSI_STCR, reg); 706 707 reg = READ4(sc, SSI_SCR); 708 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */ 709 reg |= (SCR_SSIEN | SCR_TE); 710 reg |= (SCR_NET); 711 reg |= (SCR_SYN); 712 WRITE4(sc, SSI_SCR, reg); 713 } 714 715 static void 716 ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 717 { 718 bus_addr_t *addr; 719 720 if (err) 721 return; 722 723 addr = (bus_addr_t*)arg; 724 *addr = segs[0].ds_addr; 725 } 726 727 static int 728 ssi_attach(device_t dev) 729 { 730 char status[SND_STATUSLEN]; 731 struct sc_pcminfo *scp; 732 struct sc_info *sc; 733 int err; 734 735 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 736 sc->dev = dev; 737 sc->sr = &rate_map[0]; 738 sc->pos = 0; 739 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO); 740 741 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc"); 742 if (sc->lock == NULL) { 743 device_printf(dev, "Can't create mtx\n"); 744 return (ENXIO); 745 } 746 747 if (bus_alloc_resources(dev, ssi_spec, sc->res)) { 748 device_printf(dev, "could not allocate resources\n"); 749 return (ENXIO); 750 } 751 752 /* Memory interface */ 753 sc->bst = rman_get_bustag(sc->res[0]); 754 sc->bsh = rman_get_bushandle(sc->res[0]); 755 756 /* SDMA */ 757 if (find_sdma_controller(sc)) { 758 device_printf(dev, "could not find active SDMA\n"); 759 return (ENXIO); 760 } 761 762 /* Setup PCM */ 763 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 764 scp->sc = sc; 765 scp->dev = dev; 766 767 /* 768 * Maximum possible DMA buffer. 769 * Will be used partially to match 24 bit word. 770 */ 771 sc->dma_size = 131072; 772 773 /* 774 * Must use dma_size boundary as modulo feature required. 775 * Modulo feature allows setup circular buffer. 776 */ 777 778 err = bus_dma_tag_create( 779 bus_get_dma_tag(sc->dev), 780 4, sc->dma_size, /* alignment, boundary */ 781 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 782 BUS_SPACE_MAXADDR, /* highaddr */ 783 NULL, NULL, /* filter, filterarg */ 784 sc->dma_size, 1, /* maxsize, nsegments */ 785 sc->dma_size, 0, /* maxsegsize, flags */ 786 NULL, NULL, /* lockfunc, lockarg */ 787 &sc->dma_tag); 788 789 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base, 790 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map); 791 if (err) { 792 device_printf(dev, "cannot allocate framebuffer\n"); 793 return (ENXIO); 794 } 795 796 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base, 797 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT); 798 if (err) { 799 device_printf(dev, "cannot load DMA map\n"); 800 return (ENXIO); 801 } 802 803 bzero(sc->buf_base, sc->dma_size); 804 805 /* Setup interrupt handler */ 806 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV, 807 NULL, ssi_intr, scp, &sc->ih); 808 if (err) { 809 device_printf(dev, "Unable to alloc interrupt resource.\n"); 810 return (ENXIO); 811 } 812 813 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 814 815 err = pcm_register(dev, scp, 1, 0); 816 if (err) { 817 device_printf(dev, "Can't register pcm.\n"); 818 return (ENXIO); 819 } 820 821 scp->chnum = 0; 822 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp); 823 scp->chnum++; 824 825 snprintf(status, SND_STATUSLEN, "at simplebus"); 826 pcm_setstatus(dev, status); 827 828 mixer_init(dev, &ssimixer_class, scp); 829 setup_ssi(sc); 830 831 imx_ccm_ssi_configure(dev); 832 833 sc->sdma_channel = sdma_alloc(); 834 if (sc->sdma_channel < 0) { 835 device_printf(sc->dev, "Can't get sDMA channel\n"); 836 return (1); 837 } 838 839 return (0); 840 } 841 842 static device_method_t ssi_pcm_methods[] = { 843 DEVMETHOD(device_probe, ssi_probe), 844 DEVMETHOD(device_attach, ssi_attach), 845 { 0, 0 } 846 }; 847 848 static driver_t ssi_pcm_driver = { 849 "pcm", 850 ssi_pcm_methods, 851 PCM_SOFTC_SIZE, 852 }; 853 854 DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, 0, 0); 855 MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 856 MODULE_DEPEND(ssi, sdma, 0, 0, 0); 857 MODULE_VERSION(ssi, 1); 858