1 /*- 2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Driver for imx6 Secure Non-Volatile Storage system, which really means "all 32 * the stuff that's powered by a battery when main power is off". This includes 33 * realtime clock, tamper monitor, and power-management functions. Currently 34 * this driver provides only realtime clock support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/clock.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <machine/bus.h> 44 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include "clock_if.h" 48 49 #define SNVS_LPCR 0x38 /* Control register */ 50 #define LPCR_LPCALB_VAL_SHIFT 10 /* Calibration shift */ 51 #define LPCR_LPCALB_VAL_MASK 0x1f /* Calibration mask */ 52 #define LPCR_LPCALB_EN (1u << 8) /* Calibration enable */ 53 #define LPCR_SRTC_ENV (1u << 0) /* RTC enabled/valid */ 54 55 #define SNVS_LPSRTCMR 0x50 /* Counter MSB */ 56 #define SNVS_LPSRTCLR 0x54 /* Counter LSB */ 57 58 #define RTC_RESOLUTION_US (1000000 / 32768) /* 32khz clock */ 59 60 /* 61 * The RTC is a 47-bit counter clocked at 32KHz and organized as a 32.15 62 * fixed-point binary value. Shifting by SBT_LSB bits translates between 63 * counter and sbintime values. 64 */ 65 #define RTC_BITS 47 66 #define SBT_BITS 64 67 #define SBT_LSB (SBT_BITS - RTC_BITS) 68 69 struct snvs_softc { 70 device_t dev; 71 struct resource * memres; 72 uint32_t lpcr; 73 }; 74 75 static struct ofw_compat_data compat_data[] = { 76 {"fsl,sec-v4.0-mon", true}, 77 {NULL, false} 78 }; 79 80 static inline uint32_t 81 RD4(struct snvs_softc *sc, bus_size_t offset) 82 { 83 84 return (bus_read_4(sc->memres, offset)); 85 } 86 87 static inline void 88 WR4(struct snvs_softc *sc, bus_size_t offset, uint32_t value) 89 { 90 91 bus_write_4(sc->memres, offset, value); 92 } 93 94 static void 95 snvs_rtc_enable(struct snvs_softc *sc, bool enable) 96 { 97 uint32_t enbit; 98 99 if (enable) 100 sc->lpcr |= LPCR_SRTC_ENV; 101 else 102 sc->lpcr &= ~LPCR_SRTC_ENV; 103 WR4(sc, SNVS_LPCR, sc->lpcr); 104 105 /* Wait for the hardware to achieve the requested state. */ 106 enbit = sc->lpcr & LPCR_SRTC_ENV; 107 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit) 108 continue; 109 } 110 111 static int 112 snvs_gettime(device_t dev, struct timespec *ts) 113 { 114 struct snvs_softc *sc; 115 sbintime_t counter1, counter2; 116 117 sc = device_get_softc(dev); 118 119 /* If the clock is not enabled and valid, we can't help. */ 120 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) { 121 return (EINVAL); 122 } 123 124 /* 125 * The counter is clocked asynchronously to cpu accesses; read and 126 * assemble the pieces of the counter until we get the same value twice. 127 * The counter is 47 bits, organized as a 32.15 binary fixed-point 128 * value. If we shift it up to the high order part of a 64-bit word it 129 * turns into an sbintime. 130 */ 131 do { 132 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); 133 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); 134 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); 135 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); 136 } while (counter1 != counter2); 137 138 *ts = sbttots(counter1); 139 140 clock_dbgprint_ts(sc->dev, CLOCK_DBG_READ, ts); 141 142 return (0); 143 } 144 145 static int 146 snvs_settime(device_t dev, struct timespec *ts) 147 { 148 struct snvs_softc *sc; 149 sbintime_t sbt; 150 151 sc = device_get_softc(dev); 152 153 /* 154 * The hardware format is the same as sbt (with fewer fractional bits), 155 * so first convert the time to sbt. It takes two clock cycles for the 156 * counter to start after setting the enable bit, so add two SBT_LSBs to 157 * what we're about to set. 158 */ 159 sbt = tstosbt(*ts); 160 sbt += 2 << SBT_LSB; 161 snvs_rtc_enable(sc, false); 162 WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32))); 163 WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB))); 164 snvs_rtc_enable(sc, true); 165 166 clock_dbgprint_ts(sc->dev, CLOCK_DBG_WRITE, ts); 167 168 return (0); 169 } 170 171 static int 172 snvs_probe(device_t dev) 173 { 174 175 if (!ofw_bus_status_okay(dev)) 176 return (ENXIO); 177 178 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 179 return (ENXIO); 180 181 device_set_desc(dev, "i.MX6 SNVS RTC"); 182 return (BUS_PROBE_DEFAULT); 183 } 184 185 static int 186 snvs_attach(device_t dev) 187 { 188 struct snvs_softc *sc; 189 int rid; 190 191 sc = device_get_softc(dev); 192 sc->dev = dev; 193 194 rid = 0; 195 sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, 196 RF_ACTIVE); 197 if (sc->memres == NULL) { 198 device_printf(sc->dev, "could not allocate registers\n"); 199 return (ENXIO); 200 } 201 202 clock_register(sc->dev, RTC_RESOLUTION_US); 203 204 return (0); 205 } 206 207 static int 208 snvs_detach(device_t dev) 209 { 210 struct snvs_softc *sc; 211 212 sc = device_get_softc(dev); 213 clock_unregister(sc->dev); 214 bus_release_resource(sc->dev, SYS_RES_MEMORY, 0, sc->memres); 215 return (0); 216 } 217 218 static device_method_t snvs_methods[] = { 219 DEVMETHOD(device_probe, snvs_probe), 220 DEVMETHOD(device_attach, snvs_attach), 221 DEVMETHOD(device_detach, snvs_detach), 222 223 /* clock_if methods */ 224 DEVMETHOD(clock_gettime, snvs_gettime), 225 DEVMETHOD(clock_settime, snvs_settime), 226 227 DEVMETHOD_END 228 }; 229 230 static driver_t snvs_driver = { 231 "snvs", 232 snvs_methods, 233 sizeof(struct snvs_softc), 234 }; 235 236 static devclass_t snvs_devclass; 237 238 DRIVER_MODULE(snvs, simplebus, snvs_driver, snvs_devclass, 0, 0); 239 SIMPLEBUS_PNP_INFO(compat_data); 240