1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * i.MX6 Smart Direct Memory Access Controller (sDMA) 29 * Chapter 41, i.MX 6Dual/6Quad Applications Processor Reference Manual, 30 * Rev. 1, 04/2013 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/malloc.h> 42 #include <sys/endian.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/firmware.h> 47 48 #include <vm/vm.h> 49 #include <vm/vm_extern.h> 50 #include <vm/vm_kern.h> 51 #include <vm/pmap.h> 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/intr.h> 60 61 #include <arm/freescale/imx/imx6_sdma.h> 62 63 #define MAX_BD (PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 64 65 #define READ4(_sc, _reg) \ 66 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 67 #define WRITE4(_sc, _reg, _val) \ 68 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 69 70 struct sdma_softc *sdma_sc; 71 72 static struct resource_spec sdma_spec[] = { 73 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 74 { SYS_RES_IRQ, 0, RF_ACTIVE }, 75 { -1, 0 } 76 }; 77 78 static void 79 sdma_intr(void *arg) 80 { 81 struct sdma_buffer_descriptor *bd; 82 struct sdma_channel *channel; 83 struct sdma_conf *conf; 84 struct sdma_softc *sc; 85 int pending; 86 int i; 87 int j; 88 89 sc = arg; 90 91 pending = READ4(sc, SDMAARM_INTR); 92 93 /* Ack intr */ 94 WRITE4(sc, SDMAARM_INTR, pending); 95 96 for (i = 0; i < SDMA_N_CHANNELS; i++) { 97 if ((pending & (1 << i)) == 0) 98 continue; 99 channel = &sc->channel[i]; 100 conf = channel->conf; 101 if (!conf) 102 continue; 103 for (j = 0; j < conf->num_bd; j++) { 104 bd = &channel->bd[j]; 105 bd->mode.status |= BD_DONE; 106 if (bd->mode.status & BD_RROR) 107 printf("sDMA error\n"); 108 } 109 110 conf->ih(conf->ih_user, 1); 111 112 WRITE4(sc, SDMAARM_HSTART, (1 << i)); 113 } 114 } 115 116 static int 117 sdma_probe(device_t dev) 118 { 119 120 if (!ofw_bus_status_okay(dev)) 121 return (ENXIO); 122 123 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-sdma")) 124 return (ENXIO); 125 126 device_set_desc(dev, "i.MX6 Smart Direct Memory Access Controller"); 127 return (BUS_PROBE_DEFAULT); 128 } 129 130 int 131 sdma_start(int chn) 132 { 133 struct sdma_softc *sc; 134 135 sc = sdma_sc; 136 137 WRITE4(sc, SDMAARM_HSTART, (1 << chn)); 138 139 return (0); 140 } 141 142 int 143 sdma_stop(int chn) 144 { 145 struct sdma_softc *sc; 146 147 sc = sdma_sc; 148 149 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); 150 151 return (0); 152 } 153 154 int 155 sdma_alloc(void) 156 { 157 struct sdma_channel *channel; 158 struct sdma_softc *sc; 159 int found; 160 int chn; 161 int i; 162 163 sc = sdma_sc; 164 found = 0; 165 166 /* Channel 0 can't be used */ 167 for (i = 1; i < SDMA_N_CHANNELS; i++) { 168 channel = &sc->channel[i]; 169 if (channel->in_use == 0) { 170 channel->in_use = 1; 171 found = 1; 172 break; 173 } 174 } 175 176 if (!found) 177 return (-1); 178 179 chn = i; 180 181 /* Allocate area for buffer descriptors */ 182 channel->bd = (void *)kmem_alloc_contig(PAGE_SIZE, M_ZERO, 0, ~0, 183 PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE); 184 185 return (chn); 186 } 187 188 int 189 sdma_free(int chn) 190 { 191 struct sdma_channel *channel; 192 struct sdma_softc *sc; 193 194 sc = sdma_sc; 195 196 channel = &sc->channel[chn]; 197 channel->in_use = 0; 198 199 kmem_free(kernel_arena, (vm_offset_t)channel->bd, 200 PAGE_SIZE); 201 202 return (0); 203 } 204 205 static int 206 sdma_overrides(struct sdma_softc *sc, int chn, 207 int evt, int host, int dsp) 208 { 209 int reg; 210 211 /* Ignore sDMA requests */ 212 reg = READ4(sc, SDMAARM_EVTOVR); 213 if (evt) 214 reg |= (1 << chn); 215 else 216 reg &= ~(1 << chn); 217 WRITE4(sc, SDMAARM_EVTOVR, reg); 218 219 /* Ignore enable bit (HE) */ 220 reg = READ4(sc, SDMAARM_HOSTOVR); 221 if (host) 222 reg |= (1 << chn); 223 else 224 reg &= ~(1 << chn); 225 WRITE4(sc, SDMAARM_HOSTOVR, reg); 226 227 /* Prevent sDMA channel from starting */ 228 reg = READ4(sc, SDMAARM_DSPOVR); 229 if (!dsp) 230 reg |= (1 << chn); 231 else 232 reg &= ~(1 << chn); 233 WRITE4(sc, SDMAARM_DSPOVR, reg); 234 235 return (0); 236 } 237 238 int 239 sdma_configure(int chn, struct sdma_conf *conf) 240 { 241 struct sdma_buffer_descriptor *bd0; 242 struct sdma_buffer_descriptor *bd; 243 struct sdma_context_data *context; 244 struct sdma_channel *channel; 245 struct sdma_softc *sc; 246 #if 0 247 int timeout; 248 int ret; 249 #endif 250 int i; 251 252 sc = sdma_sc; 253 254 channel = &sc->channel[chn]; 255 channel->conf = conf; 256 257 /* Ensure operation has stopped */ 258 sdma_stop(chn); 259 260 /* Set priority and enable the channel */ 261 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 262 WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn)); 263 264 sdma_overrides(sc, chn, 0, 0, 0); 265 266 if (conf->num_bd > MAX_BD) { 267 device_printf(sc->dev, "Error: too much buffer" 268 " descriptors requested\n"); 269 return (-1); 270 } 271 272 for (i = 0; i < conf->num_bd; i++) { 273 bd = &channel->bd[i]; 274 bd->mode.command = conf->command; 275 bd->mode.status = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 276 if (i == (conf->num_bd - 1)) 277 bd->mode.status |= BD_WRAP; 278 bd->mode.count = conf->period; 279 bd->buffer_addr = conf->saddr + (conf->period * i); 280 bd->ext_buffer_addr = 0; 281 } 282 283 sc->ccb[chn].base_bd_ptr = vtophys(channel->bd); 284 sc->ccb[chn].current_bd_ptr = vtophys(channel->bd); 285 286 /* 287 * Load context. 288 * 289 * i.MX6 Reference Manual: Appendix A SDMA Scripts 290 * A.3.1.7.1 (mcu_2_app) 291 */ 292 293 /* 294 * TODO: allow using other scripts 295 */ 296 context = sc->context; 297 memset(context, 0, sizeof(*context)); 298 context->channel_state.pc = sc->fw_scripts->mcu_2_app_addr; 299 300 /* 301 * Tx FIFO 0 address (r6) 302 * Event_mask (r1) 303 * Event2_mask (r0) 304 * Watermark level (r7) 305 */ 306 307 if (conf->event > 32) { 308 context->gReg[0] = (1 << (conf->event % 32)); 309 context->gReg[1] = 0; 310 } else { 311 context->gReg[0] = 0; 312 context->gReg[1] = (1 << conf->event); 313 } 314 315 context->gReg[6] = conf->daddr; 316 context->gReg[7] = conf->word_length; 317 318 bd0 = sc->bd0; 319 bd0->mode.command = C0_SETDM; 320 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 321 bd0->mode.count = sizeof(*context) / 4; 322 bd0->buffer_addr = sc->context_phys; 323 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * chn; 324 325 WRITE4(sc, SDMAARM_HSTART, 1); 326 327 #if 0 328 /* Debug purposes */ 329 330 timeout = 1000; 331 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { 332 if (timeout-- <= 0) 333 break; 334 DELAY(10); 335 }; 336 337 if (!ret) { 338 device_printf(sc->dev, "Failed to load context.\n"); 339 return (-1); 340 } 341 342 WRITE4(sc, SDMAARM_INTR, ret); 343 344 device_printf(sc->dev, "Context loaded successfully.\n"); 345 #endif 346 347 return (0); 348 } 349 350 static int 351 load_firmware(struct sdma_softc *sc) 352 { 353 const struct sdma_firmware_header *header; 354 const struct firmware *fp; 355 356 fp = firmware_get("sdma_fw"); 357 if (fp == NULL) { 358 device_printf(sc->dev, "Can't get firmware.\n"); 359 return (-1); 360 } 361 362 header = fp->data; 363 if (header->magic != FW_HEADER_MAGIC) { 364 device_printf(sc->dev, "Can't use firmware.\n"); 365 return (-1); 366 } 367 368 sc->fw_header = header; 369 sc->fw_scripts = (const void *)((const char *)header + 370 header->script_addrs_start); 371 372 return (0); 373 } 374 375 static int 376 boot_firmware(struct sdma_softc *sc) 377 { 378 struct sdma_buffer_descriptor *bd0; 379 const uint32_t *ram_code; 380 int timeout; 381 int ret; 382 int chn; 383 int sz; 384 int i; 385 386 ram_code = (const void *)((const char *)sc->fw_header + 387 sc->fw_header->ram_code_start); 388 389 /* Make sure SDMA has not started yet */ 390 WRITE4(sc, SDMAARM_MC0PTR, 0); 391 392 sz = SDMA_N_CHANNELS * sizeof(struct sdma_channel_control) + \ 393 sizeof(struct sdma_context_data); 394 sc->ccb = (void *)kmem_alloc_contig(sz, M_ZERO, 0, ~0, PAGE_SIZE, 0, 395 VM_MEMATTR_UNCACHEABLE); 396 sc->ccb_phys = vtophys(sc->ccb); 397 398 sc->context = (void *)((char *)sc->ccb + \ 399 SDMA_N_CHANNELS * sizeof(struct sdma_channel_control)); 400 sc->context_phys = vtophys(sc->context); 401 402 /* Disable all the channels */ 403 for (i = 0; i < SDMA_N_EVENTS; i++) 404 WRITE4(sc, SDMAARM_CHNENBL(i), 0); 405 406 /* All channels have priority 0 */ 407 for (i = 0; i < SDMA_N_CHANNELS; i++) 408 WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0); 409 410 /* Channel 0 is used for booting firmware */ 411 chn = 0; 412 413 sc->bd0 = (void *)kmem_alloc_contig(PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 414 0, VM_MEMATTR_UNCACHEABLE); 415 bd0 = sc->bd0; 416 sc->ccb[chn].base_bd_ptr = vtophys(bd0); 417 sc->ccb[chn].current_bd_ptr = vtophys(bd0); 418 419 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 420 421 sdma_overrides(sc, chn, 1, 0, 0); 422 423 /* XXX: not sure what is that */ 424 WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050); 425 426 WRITE4(sc, SDMAARM_CONFIG, 0); 427 WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys); 428 WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM); 429 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 430 431 bd0->mode.command = C0_SETPM; 432 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 433 bd0->mode.count = sc->fw_header->ram_code_size / 2; 434 bd0->buffer_addr = vtophys(ram_code); 435 bd0->ext_buffer_addr = sc->fw_scripts->ram_code_start_addr; 436 437 WRITE4(sc, SDMAARM_HSTART, 1); 438 439 timeout = 100; 440 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { 441 if (timeout-- <= 0) 442 break; 443 DELAY(10); 444 } 445 446 if (ret == 0) { 447 device_printf(sc->dev, "SDMA failed to boot\n"); 448 return (-1); 449 } 450 451 WRITE4(sc, SDMAARM_INTR, ret); 452 453 #if 0 454 device_printf(sc->dev, "SDMA booted successfully.\n"); 455 #endif 456 457 /* Debug is disabled */ 458 WRITE4(sc, SDMAARM_ONCE_ENB, 0); 459 460 return (0); 461 } 462 463 static int 464 sdma_attach(device_t dev) 465 { 466 struct sdma_softc *sc; 467 int err; 468 469 sc = device_get_softc(dev); 470 sc->dev = dev; 471 472 if (bus_alloc_resources(dev, sdma_spec, sc->res)) { 473 device_printf(dev, "could not allocate resources\n"); 474 return (ENXIO); 475 } 476 477 /* Memory interface */ 478 sc->bst = rman_get_bustag(sc->res[0]); 479 sc->bsh = rman_get_bushandle(sc->res[0]); 480 481 sdma_sc = sc; 482 483 /* Setup interrupt handler */ 484 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, 485 NULL, sdma_intr, sc, &sc->ih); 486 if (err) { 487 device_printf(dev, "Unable to alloc interrupt resource.\n"); 488 return (ENXIO); 489 } 490 491 if (load_firmware(sc) == -1) 492 return (ENXIO); 493 494 if (boot_firmware(sc) == -1) 495 return (ENXIO); 496 497 return (0); 498 }; 499 500 static device_method_t sdma_methods[] = { 501 /* Device interface */ 502 DEVMETHOD(device_probe, sdma_probe), 503 DEVMETHOD(device_attach, sdma_attach), 504 { 0, 0 } 505 }; 506 507 static driver_t sdma_driver = { 508 "sdma", 509 sdma_methods, 510 sizeof(struct sdma_softc), 511 }; 512 513 static devclass_t sdma_devclass; 514 515 EARLY_DRIVER_MODULE(sdma, simplebus, sdma_driver, sdma_devclass, 0, 0, 516 BUS_PASS_RESOURCE); 517