1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * i.MX6 Smart Direct Memory Access Controller (sDMA) 29 * Chapter 41, i.MX 6Dual/6Quad Applications Processor Reference Manual, 30 * Rev. 1, 04/2013 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/malloc.h> 42 #include <sys/endian.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/firmware.h> 47 48 #include <vm/vm.h> 49 #include <vm/vm_extern.h> 50 #include <vm/vm_kern.h> 51 #include <vm/pmap.h> 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/intr.h> 60 61 #include <arm/freescale/imx/imx6_sdma.h> 62 63 #define MAX_BD (PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 64 65 #define READ4(_sc, _reg) \ 66 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 67 #define WRITE4(_sc, _reg, _val) \ 68 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 69 70 struct sdma_softc *sdma_sc; 71 72 static struct resource_spec sdma_spec[] = { 73 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 74 { SYS_RES_IRQ, 0, RF_ACTIVE }, 75 { -1, 0 } 76 }; 77 78 static void 79 sdma_intr(void *arg) 80 { 81 struct sdma_buffer_descriptor *bd; 82 struct sdma_channel *channel; 83 struct sdma_conf *conf; 84 struct sdma_softc *sc; 85 int pending; 86 int i; 87 int j; 88 89 sc = arg; 90 91 pending = READ4(sc, SDMAARM_INTR); 92 93 /* Ack intr */ 94 WRITE4(sc, SDMAARM_INTR, pending); 95 96 for (i = 0; i < SDMA_N_CHANNELS; i++) { 97 if ((pending & (1 << i)) == 0) 98 continue; 99 channel = &sc->channel[i]; 100 conf = channel->conf; 101 if (!conf) 102 continue; 103 for (j = 0; j < conf->num_bd; j++) { 104 bd = &channel->bd[j]; 105 bd->mode.status |= BD_DONE; 106 if (bd->mode.status & BD_RROR) 107 printf("sDMA error\n"); 108 } 109 110 conf->ih(conf->ih_user, 1); 111 112 WRITE4(sc, SDMAARM_HSTART, (1 << i)); 113 } 114 } 115 116 static int 117 sdma_probe(device_t dev) 118 { 119 120 if (!ofw_bus_status_okay(dev)) 121 return (ENXIO); 122 123 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-sdma")) 124 return (ENXIO); 125 126 device_set_desc(dev, "i.MX6 Smart Direct Memory Access Controller"); 127 return (BUS_PROBE_DEFAULT); 128 } 129 130 int 131 sdma_start(int chn) 132 { 133 struct sdma_softc *sc; 134 135 sc = sdma_sc; 136 137 WRITE4(sc, SDMAARM_HSTART, (1 << chn)); 138 139 return (0); 140 } 141 142 int 143 sdma_stop(int chn) 144 { 145 struct sdma_softc *sc; 146 147 sc = sdma_sc; 148 149 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); 150 151 return (0); 152 } 153 154 int 155 sdma_alloc(void) 156 { 157 struct sdma_channel *channel; 158 struct sdma_softc *sc; 159 int found; 160 int chn; 161 int i; 162 163 sc = sdma_sc; 164 found = 0; 165 166 /* Channel 0 can't be used */ 167 for (i = 1; i < SDMA_N_CHANNELS; i++) { 168 channel = &sc->channel[i]; 169 if (channel->in_use == 0) { 170 channel->in_use = 1; 171 found = 1; 172 break; 173 } 174 } 175 176 if (!found) 177 return (-1); 178 179 chn = i; 180 181 /* Allocate area for buffer descriptors */ 182 channel->bd = (void *)kmem_alloc_contig(kernel_arena, 183 PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0, 184 VM_MEMATTR_UNCACHEABLE); 185 186 return (chn); 187 } 188 189 int 190 sdma_free(int chn) 191 { 192 struct sdma_channel *channel; 193 struct sdma_softc *sc; 194 195 sc = sdma_sc; 196 197 channel = &sc->channel[chn]; 198 channel->in_use = 0; 199 200 kmem_free(kernel_arena, (vm_offset_t)channel->bd, 201 PAGE_SIZE); 202 203 return (0); 204 } 205 206 static int 207 sdma_overrides(struct sdma_softc *sc, int chn, 208 int evt, int host, int dsp) 209 { 210 int reg; 211 212 /* Ignore sDMA requests */ 213 reg = READ4(sc, SDMAARM_EVTOVR); 214 if (evt) 215 reg |= (1 << chn); 216 else 217 reg &= ~(1 << chn); 218 WRITE4(sc, SDMAARM_EVTOVR, reg); 219 220 /* Ignore enable bit (HE) */ 221 reg = READ4(sc, SDMAARM_HOSTOVR); 222 if (host) 223 reg |= (1 << chn); 224 else 225 reg &= ~(1 << chn); 226 WRITE4(sc, SDMAARM_HOSTOVR, reg); 227 228 /* Prevent sDMA channel from starting */ 229 reg = READ4(sc, SDMAARM_DSPOVR); 230 if (!dsp) 231 reg |= (1 << chn); 232 else 233 reg &= ~(1 << chn); 234 WRITE4(sc, SDMAARM_DSPOVR, reg); 235 236 return (0); 237 } 238 239 int 240 sdma_configure(int chn, struct sdma_conf *conf) 241 { 242 struct sdma_buffer_descriptor *bd0; 243 struct sdma_buffer_descriptor *bd; 244 struct sdma_context_data *context; 245 struct sdma_channel *channel; 246 struct sdma_softc *sc; 247 #if 0 248 int timeout; 249 int ret; 250 #endif 251 int i; 252 253 sc = sdma_sc; 254 255 channel = &sc->channel[chn]; 256 channel->conf = conf; 257 258 /* Ensure operation has stopped */ 259 sdma_stop(chn); 260 261 /* Set priority and enable the channel */ 262 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 263 WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn)); 264 265 sdma_overrides(sc, chn, 0, 0, 0); 266 267 if (conf->num_bd > MAX_BD) { 268 device_printf(sc->dev, "Error: too much buffer" 269 " descriptors requested\n"); 270 return (-1); 271 } 272 273 for (i = 0; i < conf->num_bd; i++) { 274 bd = &channel->bd[i]; 275 bd->mode.command = conf->command; 276 bd->mode.status = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 277 if (i == (conf->num_bd - 1)) 278 bd->mode.status |= BD_WRAP; 279 bd->mode.count = conf->period; 280 bd->buffer_addr = conf->saddr + (conf->period * i); 281 bd->ext_buffer_addr = 0; 282 } 283 284 sc->ccb[chn].base_bd_ptr = vtophys(channel->bd); 285 sc->ccb[chn].current_bd_ptr = vtophys(channel->bd); 286 287 /* 288 * Load context. 289 * 290 * i.MX6 Reference Manual: Appendix A SDMA Scripts 291 * A.3.1.7.1 (mcu_2_app) 292 */ 293 294 /* 295 * TODO: allow using other scripts 296 */ 297 context = sc->context; 298 memset(context, 0, sizeof(*context)); 299 context->channel_state.pc = sc->fw_scripts->mcu_2_app_addr; 300 301 /* 302 * Tx FIFO 0 address (r6) 303 * Event_mask (r1) 304 * Event2_mask (r0) 305 * Watermark level (r7) 306 */ 307 308 if (conf->event > 32) { 309 context->gReg[0] = (1 << (conf->event % 32)); 310 context->gReg[1] = 0; 311 } else { 312 context->gReg[0] = 0; 313 context->gReg[1] = (1 << conf->event); 314 } 315 316 context->gReg[6] = conf->daddr; 317 context->gReg[7] = conf->word_length; 318 319 bd0 = sc->bd0; 320 bd0->mode.command = C0_SETDM; 321 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 322 bd0->mode.count = sizeof(*context) / 4; 323 bd0->buffer_addr = sc->context_phys; 324 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * chn; 325 326 WRITE4(sc, SDMAARM_HSTART, 1); 327 328 #if 0 329 /* Debug purposes */ 330 331 timeout = 1000; 332 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { 333 if (timeout-- <= 0) 334 break; 335 DELAY(10); 336 }; 337 338 if (!ret) { 339 device_printf(sc->dev, "Failed to load context.\n"); 340 return (-1); 341 } 342 343 WRITE4(sc, SDMAARM_INTR, ret); 344 345 device_printf(sc->dev, "Context loaded successfully.\n"); 346 #endif 347 348 return (0); 349 } 350 351 static int 352 load_firmware(struct sdma_softc *sc) 353 { 354 const struct sdma_firmware_header *header; 355 const struct firmware *fp; 356 357 fp = firmware_get("sdma_fw"); 358 if (fp == NULL) { 359 device_printf(sc->dev, "Can't get firmware.\n"); 360 return (-1); 361 } 362 363 header = fp->data; 364 if (header->magic != FW_HEADER_MAGIC) { 365 device_printf(sc->dev, "Can't use firmware.\n"); 366 return (-1); 367 } 368 369 sc->fw_header = header; 370 sc->fw_scripts = (const void *)((const char *)header + 371 header->script_addrs_start); 372 373 return (0); 374 } 375 376 static int 377 boot_firmware(struct sdma_softc *sc) 378 { 379 struct sdma_buffer_descriptor *bd0; 380 const uint32_t *ram_code; 381 int timeout; 382 int ret; 383 int chn; 384 int sz; 385 int i; 386 387 ram_code = (const void *)((const char *)sc->fw_header + 388 sc->fw_header->ram_code_start); 389 390 /* Make sure SDMA has not started yet */ 391 WRITE4(sc, SDMAARM_MC0PTR, 0); 392 393 sz = SDMA_N_CHANNELS * sizeof(struct sdma_channel_control) + \ 394 sizeof(struct sdma_context_data); 395 sc->ccb = (void *)kmem_alloc_contig(kernel_arena, 396 sz, M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE); 397 sc->ccb_phys = vtophys(sc->ccb); 398 399 sc->context = (void *)((char *)sc->ccb + \ 400 SDMA_N_CHANNELS * sizeof(struct sdma_channel_control)); 401 sc->context_phys = vtophys(sc->context); 402 403 /* Disable all the channels */ 404 for (i = 0; i < SDMA_N_EVENTS; i++) 405 WRITE4(sc, SDMAARM_CHNENBL(i), 0); 406 407 /* All channels have priority 0 */ 408 for (i = 0; i < SDMA_N_CHANNELS; i++) 409 WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0); 410 411 /* Channel 0 is used for booting firmware */ 412 chn = 0; 413 414 sc->bd0 = (void *)kmem_alloc_contig(kernel_arena, 415 PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0, 416 VM_MEMATTR_UNCACHEABLE); 417 bd0 = sc->bd0; 418 sc->ccb[chn].base_bd_ptr = vtophys(bd0); 419 sc->ccb[chn].current_bd_ptr = vtophys(bd0); 420 421 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 422 423 sdma_overrides(sc, chn, 1, 0, 0); 424 425 /* XXX: not sure what is that */ 426 WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050); 427 428 WRITE4(sc, SDMAARM_CONFIG, 0); 429 WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys); 430 WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM); 431 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 432 433 bd0->mode.command = C0_SETPM; 434 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 435 bd0->mode.count = sc->fw_header->ram_code_size / 2; 436 bd0->buffer_addr = vtophys(ram_code); 437 bd0->ext_buffer_addr = sc->fw_scripts->ram_code_start_addr; 438 439 WRITE4(sc, SDMAARM_HSTART, 1); 440 441 timeout = 100; 442 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { 443 if (timeout-- <= 0) 444 break; 445 DELAY(10); 446 } 447 448 if (ret == 0) { 449 device_printf(sc->dev, "SDMA failed to boot\n"); 450 return (-1); 451 } 452 453 WRITE4(sc, SDMAARM_INTR, ret); 454 455 #if 0 456 device_printf(sc->dev, "SDMA booted successfully.\n"); 457 #endif 458 459 /* Debug is disabled */ 460 WRITE4(sc, SDMAARM_ONCE_ENB, 0); 461 462 return (0); 463 } 464 465 static int 466 sdma_attach(device_t dev) 467 { 468 struct sdma_softc *sc; 469 int err; 470 471 sc = device_get_softc(dev); 472 sc->dev = dev; 473 474 if (bus_alloc_resources(dev, sdma_spec, sc->res)) { 475 device_printf(dev, "could not allocate resources\n"); 476 return (ENXIO); 477 } 478 479 /* Memory interface */ 480 sc->bst = rman_get_bustag(sc->res[0]); 481 sc->bsh = rman_get_bushandle(sc->res[0]); 482 483 sdma_sc = sc; 484 485 /* Setup interrupt handler */ 486 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, 487 NULL, sdma_intr, sc, &sc->ih); 488 if (err) { 489 device_printf(dev, "Unable to alloc interrupt resource.\n"); 490 return (ENXIO); 491 } 492 493 if (load_firmware(sc) == -1) 494 return (ENXIO); 495 496 if (boot_firmware(sc) == -1) 497 return (ENXIO); 498 499 return (0); 500 }; 501 502 static device_method_t sdma_methods[] = { 503 /* Device interface */ 504 DEVMETHOD(device_probe, sdma_probe), 505 DEVMETHOD(device_attach, sdma_attach), 506 { 0, 0 } 507 }; 508 509 static driver_t sdma_driver = { 510 "sdma", 511 sdma_methods, 512 sizeof(struct sdma_softc), 513 }; 514 515 static devclass_t sdma_devclass; 516 517 EARLY_DRIVER_MODULE(sdma, simplebus, sdma_driver, sdma_devclass, 0, 0, 518 BUS_PASS_RESOURCE); 519