xref: /freebsd/sys/arm/freescale/imx/imx6_mp.c (revision 4f52dfbb8d6c4d446500c5b097e3806ec219fbd4)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de>
5  * Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/smp.h>
38 
39 #include <vm/vm.h>
40 #include <vm/pmap.h>
41 
42 #include <machine/cpu.h>
43 #include <machine/smp.h>
44 #include <machine/fdt.h>
45 #include <machine/intr.h>
46 #include <machine/platform.h>
47 #include <machine/platformvar.h>
48 
49 #include <arm/freescale/imx/imx6_machdep.h>
50 
51 #define	SCU_PHYSBASE			0x00a00000
52 #define	SCU_SIZE			0x00001000
53 
54 #define	SCU_CONTROL_REG			0x00
55 #define	  SCU_CONTROL_ENABLE		  (1 << 0)
56 #define	SCU_CONFIG_REG			0x04
57 #define	  SCU_CONFIG_REG_NCPU_MASK	  0x03
58 #define	SCU_CPUPOWER_REG		0x08
59 #define	SCU_INV_TAGS_REG		0x0c
60 #define	SCU_DIAG_CONTROL		0x30
61 #define	  SCU_DIAG_DISABLE_MIGBIT	  (1 << 0)
62 #define	SCU_FILTER_START_REG		0x40
63 #define	SCU_FILTER_END_REG		0x44
64 #define	SCU_SECURE_ACCESS_REG		0x50
65 #define	SCU_NONSECURE_ACCESS_REG	0x54
66 
67 #define	SRC_PHYSBASE			0x020d8000
68 #define SRC_SIZE			0x4000
69 #define	SRC_CONTROL_REG			0x00
70 #define	SRC_CONTROL_C1ENA_SHIFT		  22	/* Bit for Core 1 enable */
71 #define	SRC_CONTROL_C1RST_SHIFT		  14	/* Bit for Core 1 reset */
72 #define	SRC_GPR0_C1FUNC			0x20	/* Register for Core 1 entry func */
73 #define	SRC_GPR1_C1ARG			0x24	/* Register for Core 1 entry arg */
74 
75 void
76 imx6_mp_setmaxid(platform_t plat)
77 {
78 	bus_space_handle_t scu;
79 	int hwcpu, ncpu;
80 	uint32_t val;
81 
82 	/* If we've already set the global vars don't bother to do it again. */
83 	if (mp_ncpus != 0)
84 		return;
85 
86 	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
87 		panic("Couldn't map the SCU\n");
88 	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
89 	hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1;
90 	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
91 
92 	ncpu = hwcpu;
93 	TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
94 	if (ncpu < 1 || ncpu > hwcpu)
95 		ncpu = hwcpu;
96 
97 	mp_ncpus = ncpu;
98 	mp_maxid = ncpu - 1;
99 }
100 
101 void
102 imx6_mp_start_ap(platform_t plat)
103 {
104 	bus_space_handle_t scu;
105 	bus_space_handle_t src;
106 
107 	uint32_t val;
108 	int i;
109 
110 	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
111 		panic("Couldn't map the SCU\n");
112 	if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
113 		panic("Couldn't map the system reset controller (SRC)\n");
114 
115 	/*
116 	 * Invalidate SCU cache tags.  The 0x0000ffff constant invalidates all
117 	 * ways on all cores 0-3.  Per the ARM docs, it's harmless to write to
118 	 * the bits for cores that are not present.
119 	 */
120 	bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
121 
122 	/*
123 	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
124 	 * Setting the "disable-migratory bit" in the undocumented SCU
125 	 * Diagnostic Control Register helps work around the problem.
126 	 */
127 	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
128 	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
129 	    val | SCU_DIAG_DISABLE_MIGBIT);
130 
131 	/*
132 	 * Enable the SCU, then clean the cache on this core.  After these two
133 	 * operations the cache tag ram in the SCU is coherent with the contents
134 	 * of the cache on this core.  The other cores aren't running yet so
135 	 * their caches can't contain valid data yet, but we've initialized
136 	 * their SCU tag ram above, so they will be coherent from startup.
137 	 */
138 	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
139 	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
140 	    val | SCU_CONTROL_ENABLE);
141 	dcache_wbinv_poc_all();
142 
143 	/*
144 	 * For each AP core, set the entry point address and argument registers,
145 	 * and set the core-enable and core-reset bits in the control register.
146 	 */
147 	val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
148 	for (i=1; i < mp_ncpus; i++) {
149 		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
150 		    pmap_kextract((vm_offset_t)mpentry));
151 		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG  + 8*i, 0);
152 
153 		val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
154 		    ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
155 
156 	}
157 	bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
158 
159 	dsb();
160 	sev();
161 
162 	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
163 	bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
164 }
165