1 /*- 2 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de> 3 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/smp.h> 36 37 #include <vm/vm.h> 38 #include <vm/pmap.h> 39 40 #include <machine/cpu.h> 41 #include <machine/smp.h> 42 #include <machine/fdt.h> 43 #include <machine/intr.h> 44 45 #define SCU_PHYSBASE 0x00a00000 46 #define SCU_SIZE 0x00001000 47 48 #define SCU_CONTROL_REG 0x00 49 #define SCU_CONTROL_ENABLE (1 << 0) 50 #define SCU_CONFIG_REG 0x04 51 #define SCU_CONFIG_REG_NCPU_MASK 0x03 52 #define SCU_CPUPOWER_REG 0x08 53 #define SCU_INV_TAGS_REG 0x0c 54 #define SCU_DIAG_CONTROL 0x30 55 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) 56 #define SCU_FILTER_START_REG 0x40 57 #define SCU_FILTER_END_REG 0x44 58 #define SCU_SECURE_ACCESS_REG 0x50 59 #define SCU_NONSECURE_ACCESS_REG 0x54 60 61 #define SRC_PHYSBASE 0x020d8000 62 #define SRC_SIZE 0x4000 63 #define SRC_CONTROL_REG 0x00 64 #define SRC_CONTROL_C1ENA_SHIFT 22 /* Bit for Core 1 enable */ 65 #define SRC_CONTROL_C1RST_SHIFT 14 /* Bit for Core 1 reset */ 66 #define SRC_GPR0_C1FUNC 0x20 /* Register for Core 1 entry func */ 67 #define SRC_GPR1_C1ARG 0x24 /* Register for Core 1 entry arg */ 68 69 void 70 platform_mp_init_secondary(void) 71 { 72 73 intr_pic_init_secondary(); 74 } 75 76 void 77 platform_mp_setmaxid(void) 78 { 79 bus_space_handle_t scu; 80 int hwcpu, ncpu; 81 uint32_t val; 82 83 /* If we've already set the global vars don't bother to do it again. */ 84 if (mp_ncpus != 0) 85 return; 86 87 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 88 panic("Couldn't map the SCU\n"); 89 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG); 90 hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1; 91 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 92 93 ncpu = hwcpu; 94 TUNABLE_INT_FETCH("hw.ncpu", &ncpu); 95 if (ncpu < 1 || ncpu > hwcpu) 96 ncpu = hwcpu; 97 98 mp_ncpus = ncpu; 99 mp_maxid = ncpu - 1; 100 } 101 102 int 103 platform_mp_probe(void) 104 { 105 106 /* I think platform_mp_setmaxid must get called first, but be safe. */ 107 if (mp_ncpus == 0) 108 platform_mp_setmaxid(); 109 110 return (mp_ncpus > 1); 111 } 112 113 void 114 platform_mp_start_ap(void) 115 { 116 bus_space_handle_t scu; 117 bus_space_handle_t src; 118 119 uint32_t val; 120 int i; 121 122 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 123 panic("Couldn't map the SCU\n"); 124 if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0) 125 panic("Couldn't map the system reset controller (SRC)\n"); 126 127 /* 128 * Invalidate SCU cache tags. The 0x0000ffff constant invalidates all 129 * ways on all cores 0-3. Per the ARM docs, it's harmless to write to 130 * the bits for cores that are not present. 131 */ 132 bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); 133 134 /* 135 * Erratum ARM/MP: 764369 (problems with cache maintenance). 136 * Setting the "disable-migratory bit" in the undocumented SCU 137 * Diagnostic Control Register helps work around the problem. 138 */ 139 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 140 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, 141 val | SCU_DIAG_DISABLE_MIGBIT); 142 143 /* 144 * Enable the SCU, then clean the cache on this core. After these two 145 * operations the cache tag ram in the SCU is coherent with the contents 146 * of the cache on this core. The other cores aren't running yet so 147 * their caches can't contain valid data yet, but we've initialized 148 * their SCU tag ram above, so they will be coherent from startup. 149 */ 150 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 151 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, 152 val | SCU_CONTROL_ENABLE); 153 dcache_wbinv_poc_all(); 154 155 /* 156 * For each AP core, set the entry point address and argument registers, 157 * and set the core-enable and core-reset bits in the control register. 158 */ 159 val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG); 160 for (i=1; i < mp_ncpus; i++) { 161 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i, 162 pmap_kextract((vm_offset_t)mpentry)); 163 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0); 164 165 val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) | 166 ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i))); 167 168 } 169 bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val); 170 171 armv7_sev(); 172 173 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 174 bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE); 175 } 176 177 void 178 platform_ipi_send(cpuset_t cpus, u_int ipi) 179 { 180 181 pic_ipi_send(cpus, ipi); 182 } 183