1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/reboot.h> 36 #include <sys/devmap.h> 37 38 #include <vm/vm.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 #include <machine/machdep.h> 43 #include <machine/platformvar.h> 44 45 #include <arm/arm/mpcore_timervar.h> 46 #include <arm/freescale/imx/imx6_anatopreg.h> 47 #include <arm/freescale/imx/imx6_anatopvar.h> 48 #include <arm/freescale/imx/imx_machdep.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/openfirm.h> 52 53 #include <arm/freescale/imx/imx6_mp.h> 54 55 #include "platform_if.h" 56 57 static uint32_t gpio1_node; 58 59 static platform_attach_t imx6_attach; 60 static platform_devmap_init_t imx6_devmap_init; 61 static platform_late_init_t imx6_late_init; 62 static platform_cpu_reset_t imx6_cpu_reset; 63 64 #ifndef INTRNG 65 /* 66 * Work around the linux workaround for imx6 erratum 006687, in which some 67 * ethernet interrupts don't go to the GPC and thus won't wake the system from 68 * Wait mode. We don't use Wait mode (which halts the GIC, leaving only GPC 69 * interrupts able to wake the system), so we don't experience the bug at all. 70 * The linux workaround is to reconfigure GPIO1_6 as the ENET interrupt by 71 * writing magic values to an undocumented IOMUX register, then letting the gpio 72 * interrupt driver notify the ethernet driver. We'll be able to do all that 73 * (even though we don't need to) once the INTRNG project is committed and the 74 * imx_gpio driver becomes an interrupt driver. Until then, this crazy little 75 * workaround watches for requests to map an interrupt 6 with the interrupt 76 * controller node referring to gpio1, and it substitutes the proper ffec 77 * interrupt number. 78 */ 79 static int 80 imx6_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt, 81 int *trig, int *pol) 82 { 83 84 if (fdt32_to_cpu(intr[0]) == 6 && 85 OF_node_from_xref(iparent) == gpio1_node) { 86 *interrupt = 150; 87 *trig = INTR_TRIGGER_CONFORM; 88 *pol = INTR_POLARITY_CONFORM; 89 return (0); 90 } 91 return (gic_decode_fdt(iparent, intr, interrupt, trig, pol)); 92 } 93 94 fdt_pic_decode_t fdt_pic_table[] = { 95 &imx6_decode_fdt, 96 NULL 97 }; 98 #endif 99 100 /* 101 * Fix FDT data related to interrupts. 102 * 103 * Driven by the needs of linux and its drivers (as always), the published FDT 104 * data for imx6 now sets the interrupt parent for most devices to the GPC 105 * interrupt controller, which is for use when the chip is in deep-sleep mode. 106 * We don't support deep sleep or have a GPC-PIC driver; we need all interrupts 107 * to be handled by the GIC. 108 * 109 * Luckily, the change to the FDT data was to assign the GPC as the interrupt 110 * parent for the soc node and letting that get inherited by all other devices 111 * (except a few that directly name GIC as their interrupt parent). So we can 112 * set the world right by just changing the interrupt-parent property of the soc 113 * node to refer to GIC instead of GPC. This will get us by until we write our 114 * own GPC driver (or until linux changes its mind and the FDT data again). 115 * 116 * We validate that we have data that looks like we expect before changing it: 117 * - SOC node exists and has GPC as its interrupt parent. 118 * - GPC node exists and has GIC as its interrupt parent. 119 * - GIC node exists and is its own interrupt parent. 120 * 121 * This applies to all models of imx6. Luckily all of them have the devices 122 * involved at the same addresses on the same buses, so we don't need any 123 * per-soc logic. We handle this at platform attach time rather than via the 124 * fdt_fixup_table, because the latter requires matching on the FDT "model" 125 * property, and this applies to all boards including those not yet invented. 126 */ 127 static void 128 fix_fdt_interrupt_data(void) 129 { 130 phandle_t gicipar, gicnode, gicxref; 131 phandle_t gpcipar, gpcnode, gpcxref; 132 phandle_t socipar, socnode; 133 int result; 134 135 socnode = OF_finddevice("/soc"); 136 if (socnode == -1) 137 return; 138 result = OF_getencprop(socnode, "interrupt-parent", &socipar, 139 sizeof(socipar)); 140 if (result <= 0) 141 return; 142 143 gicnode = OF_finddevice("/soc/interrupt-controller@00a01000"); 144 if (gicnode == -1) 145 return; 146 result = OF_getencprop(gicnode, "interrupt-parent", &gicipar, 147 sizeof(gicipar)); 148 if (result <= 0) 149 return; 150 gicxref = OF_xref_from_node(gicnode); 151 152 gpcnode = OF_finddevice("/soc/aips-bus@02000000/gpc@020dc000"); 153 if (gpcnode == -1) 154 return; 155 result = OF_getencprop(gpcnode, "interrupt-parent", &gpcipar, 156 sizeof(gpcipar)); 157 if (result <= 0) 158 return; 159 gpcxref = OF_xref_from_node(gpcnode); 160 161 if (socipar != gpcxref || gpcipar != gicxref || gicipar != gicxref) 162 return; 163 164 gicxref = cpu_to_fdt32(gicxref); 165 OF_setprop(socnode, "interrupt-parent", &gicxref, sizeof(gicxref)); 166 } 167 168 static int 169 imx6_attach(platform_t plat) 170 { 171 172 /* Fix soc interrupt-parent property. */ 173 fix_fdt_interrupt_data(); 174 175 /* Inform the MPCore timer driver that its clock is variable. */ 176 arm_tmr_change_frequency(ARM_TMR_FREQUENCY_VARIES); 177 178 return (0); 179 } 180 181 static void 182 imx6_late_init(platform_t plat) 183 { 184 const uint32_t IMX6_WDOG_SR_PHYS = 0x020bc004; 185 186 imx_wdog_init_last_reset(IMX6_WDOG_SR_PHYS); 187 188 /* Cache the gpio1 node handle for imx6_decode_fdt() workaround code. */ 189 gpio1_node = OF_node_from_xref( 190 OF_finddevice("/soc/aips-bus@02000000/gpio@0209c000")); 191 } 192 193 /* 194 * Set up static device mappings. 195 * 196 * This attempts to cover the most-used devices with 1MB section mappings, which 197 * is good for performance (uses fewer TLB entries for device access). 198 * 199 * ARMMP covers the interrupt controller, MPCore timers, global timer, and the 200 * L2 cache controller. Most of the 1MB range is unused reserved space. 201 * 202 * AIPS1/AIPS2 cover most of the on-chip devices such as uart, spi, i2c, etc. 203 * 204 * Notably not mapped right now are HDMI, GPU, and other devices below ARMMP in 205 * the memory map. When we get support for graphics it might make sense to 206 * static map some of that area. Be careful with other things in that area such 207 * as OCRAM that probably shouldn't be mapped as VM_MEMATTR_DEVICE memory. 208 */ 209 static int 210 imx6_devmap_init(platform_t plat) 211 { 212 const uint32_t IMX6_ARMMP_PHYS = 0x00a00000; 213 const uint32_t IMX6_ARMMP_SIZE = 0x00100000; 214 const uint32_t IMX6_AIPS1_PHYS = 0x02000000; 215 const uint32_t IMX6_AIPS1_SIZE = 0x00100000; 216 const uint32_t IMX6_AIPS2_PHYS = 0x02100000; 217 const uint32_t IMX6_AIPS2_SIZE = 0x00100000; 218 219 devmap_add_entry(IMX6_ARMMP_PHYS, IMX6_ARMMP_SIZE); 220 devmap_add_entry(IMX6_AIPS1_PHYS, IMX6_AIPS1_SIZE); 221 devmap_add_entry(IMX6_AIPS2_PHYS, IMX6_AIPS2_SIZE); 222 223 return (0); 224 } 225 226 static void 227 imx6_cpu_reset(platform_t plat) 228 { 229 const uint32_t IMX6_WDOG_CR_PHYS = 0x020bc000; 230 231 imx_wdog_cpu_reset(IMX6_WDOG_CR_PHYS); 232 } 233 234 /* 235 * Determine what flavor of imx6 we're running on. 236 * 237 * This code is based on the way u-boot does it. Information found on the web 238 * indicates that Freescale themselves were the original source of this logic, 239 * including the strange check for number of CPUs in the SCU configuration 240 * register, which is apparently needed on some revisions of the SOLO. 241 * 242 * According to the documentation, there is such a thing as an i.MX6 Dual 243 * (non-lite flavor). However, Freescale doesn't seem to have assigned it a 244 * number or provided any logic to handle it in their detection code. 245 * 246 * Note that the ANALOG_DIGPROG and SCU configuration registers are not 247 * documented in the chip reference manual. (SCU configuration is mentioned, 248 * but not mapped out in detail.) I think the bottom two bits of the scu config 249 * register may be ncpu-1. 250 * 251 * This hasn't been tested yet on a dual[-lite]. 252 * 253 * On a solo: 254 * digprog = 0x00610001 255 * hwsoc = 0x00000062 256 * scu config = 0x00000500 257 * On a quad: 258 * digprog = 0x00630002 259 * hwsoc = 0x00000063 260 * scu config = 0x00005503 261 */ 262 u_int 263 imx_soc_type(void) 264 { 265 uint32_t digprog, hwsoc; 266 uint32_t *pcr; 267 static u_int soctype; 268 const vm_offset_t SCU_CONFIG_PHYSADDR = 0x00a00004; 269 #define HWSOC_MX6SL 0x60 270 #define HWSOC_MX6DL 0x61 271 #define HWSOC_MX6SOLO 0x62 272 #define HWSOC_MX6Q 0x63 273 274 if (soctype != 0) 275 return (soctype); 276 277 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG_SL); 278 hwsoc = (digprog >> IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) & 279 IMX6_ANALOG_DIGPROG_SOCTYPE_MASK; 280 281 if (hwsoc != HWSOC_MX6SL) { 282 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG); 283 hwsoc = (digprog & IMX6_ANALOG_DIGPROG_SOCTYPE_MASK) >> 284 IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT; 285 /*printf("digprog = 0x%08x\n", digprog);*/ 286 if (hwsoc == HWSOC_MX6DL) { 287 pcr = devmap_ptov(SCU_CONFIG_PHYSADDR, 4); 288 if (pcr != NULL) { 289 /*printf("scu config = 0x%08x\n", *pcr);*/ 290 if ((*pcr & 0x03) == 0) { 291 hwsoc = HWSOC_MX6SOLO; 292 } 293 } 294 } 295 } 296 /* printf("hwsoc 0x%08x\n", hwsoc); */ 297 298 switch (hwsoc) { 299 case HWSOC_MX6SL: 300 soctype = IMXSOC_6SL; 301 break; 302 case HWSOC_MX6SOLO: 303 soctype = IMXSOC_6S; 304 break; 305 case HWSOC_MX6DL: 306 soctype = IMXSOC_6DL; 307 break; 308 case HWSOC_MX6Q : 309 soctype = IMXSOC_6Q; 310 break; 311 default: 312 printf("imx_soc_type: Don't understand hwsoc 0x%02x, " 313 "digprog 0x%08x; assuming IMXSOC_6Q\n", hwsoc, digprog); 314 soctype = IMXSOC_6Q; 315 break; 316 } 317 318 return (soctype); 319 } 320 321 /* 322 * Early putc routine for EARLY_PRINTF support. To use, add to kernel config: 323 * option SOCDEV_PA=0x02000000 324 * option SOCDEV_VA=0x02000000 325 * option EARLY_PRINTF 326 * Resist the temptation to change the #if 0 to #ifdef EARLY_PRINTF here. It 327 * makes sense now, but if multiple SOCs do that it will make early_putc another 328 * duplicate symbol to be eliminated on the path to a generic kernel. 329 */ 330 #if 0 331 static void 332 imx6_early_putc(int c) 333 { 334 volatile uint32_t * UART_STAT_REG = (uint32_t *)0x02020098; 335 volatile uint32_t * UART_TX_REG = (uint32_t *)0x02020040; 336 const uint32_t UART_TXRDY = (1 << 3); 337 338 while ((*UART_STAT_REG & UART_TXRDY) == 0) 339 continue; 340 *UART_TX_REG = c; 341 } 342 early_putc_t *early_putc = imx6_early_putc; 343 #endif 344 345 static platform_method_t imx6_methods[] = { 346 PLATFORMMETHOD(platform_attach, imx6_attach), 347 PLATFORMMETHOD(platform_devmap_init, imx6_devmap_init), 348 PLATFORMMETHOD(platform_late_init, imx6_late_init), 349 PLATFORMMETHOD(platform_cpu_reset, imx6_cpu_reset), 350 351 #ifdef SMP 352 PLATFORMMETHOD(platform_mp_start_ap, imx6_mp_start_ap), 353 PLATFORMMETHOD(platform_mp_setmaxid, imx6_mp_setmaxid), 354 #endif 355 356 PLATFORMMETHOD_END, 357 }; 358 359 FDT_PLATFORM_DEF2(imx6, imx6s, "i.MX6 Solo", 0, "fsl,imx6s", 0); 360 FDT_PLATFORM_DEF2(imx6, imx6d, "i.MX6 Dual", 0, "fsl,imx6dl", 0); 361 FDT_PLATFORM_DEF2(imx6, imx6q, "i.MX6 Quad", 0, "fsl,imx6q", 0); 362