1034e9ed6SIan Lepore /*- 2034e9ed6SIan Lepore * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3034e9ed6SIan Lepore * All rights reserved. 4034e9ed6SIan Lepore * 5034e9ed6SIan Lepore * Redistribution and use in source and binary forms, with or without 6034e9ed6SIan Lepore * modification, are permitted provided that the following conditions 7034e9ed6SIan Lepore * are met: 8034e9ed6SIan Lepore * 1. Redistributions of source code must retain the above copyright 9034e9ed6SIan Lepore * notice, this list of conditions and the following disclaimer. 10034e9ed6SIan Lepore * 2. Redistributions in binary form must reproduce the above copyright 11034e9ed6SIan Lepore * notice, this list of conditions and the following disclaimer in the 12034e9ed6SIan Lepore * documentation and/or other materials provided with the distribution. 13034e9ed6SIan Lepore * 14034e9ed6SIan Lepore * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15034e9ed6SIan Lepore * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16034e9ed6SIan Lepore * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17034e9ed6SIan Lepore * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18034e9ed6SIan Lepore * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19034e9ed6SIan Lepore * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20034e9ed6SIan Lepore * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21034e9ed6SIan Lepore * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22034e9ed6SIan Lepore * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23034e9ed6SIan Lepore * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24034e9ed6SIan Lepore * SUCH DAMAGE. 25034e9ed6SIan Lepore */ 26034e9ed6SIan Lepore 27034e9ed6SIan Lepore #include "opt_platform.h" 28034e9ed6SIan Lepore 29034e9ed6SIan Lepore #include <sys/cdefs.h> 30034e9ed6SIan Lepore __FBSDID("$FreeBSD$"); 31034e9ed6SIan Lepore 32034e9ed6SIan Lepore #include <sys/param.h> 33034e9ed6SIan Lepore #include <sys/systm.h> 34034e9ed6SIan Lepore #include <sys/bus.h> 35034e9ed6SIan Lepore #include <sys/reboot.h> 36034e9ed6SIan Lepore 37034e9ed6SIan Lepore #include <vm/vm.h> 38034e9ed6SIan Lepore #include <vm/pmap.h> 39*13a98c85SIan Lepore 40*13a98c85SIan Lepore #include <machine/bus.h> 41*13a98c85SIan Lepore #include <machine/devmap.h> 42*13a98c85SIan Lepore 43034e9ed6SIan Lepore #include <arm/freescale/imx/imx6_anatopreg.h> 44034e9ed6SIan Lepore #include <arm/freescale/imx/imx6_anatopvar.h> 45034e9ed6SIan Lepore #include <arm/freescale/imx/imx_machdep.h> 46034e9ed6SIan Lepore 47034e9ed6SIan Lepore /* 48034e9ed6SIan Lepore * Set up static device mappings. Note that for imx this is called from 49034e9ed6SIan Lepore * initarm_lastaddr() so that it can return the lowest address used for static 50034e9ed6SIan Lepore * device mapping, maximizing kva space. 51034e9ed6SIan Lepore * 52034e9ed6SIan Lepore * This attempts to cover the most-used devices with 1MB section mappings, which 53034e9ed6SIan Lepore * is good for performance (uses fewer TLB entries for device access). 54034e9ed6SIan Lepore * 55034e9ed6SIan Lepore * ARMMP covers the interrupt controller, MPCore timers, global timer, and the 56034e9ed6SIan Lepore * L2 cache controller. Most of the 1MB range is unused reserved space. 57034e9ed6SIan Lepore * 58034e9ed6SIan Lepore * AIPS1/AIPS2 cover most of the on-chip devices such as uart, spi, i2c, etc. 59034e9ed6SIan Lepore * 60034e9ed6SIan Lepore * Notably not mapped right now are HDMI, GPU, and other devices below ARMMP in 61034e9ed6SIan Lepore * the memory map. When we get support for graphics it might make sense to 62034e9ed6SIan Lepore * static map some of that area. Be careful with other things in that area such 63034e9ed6SIan Lepore * as OCRAM that probably shouldn't be mapped as PTE_DEVICE memory. 64034e9ed6SIan Lepore */ 65034e9ed6SIan Lepore void 66034e9ed6SIan Lepore imx_devmap_init(void) 67034e9ed6SIan Lepore { 68034e9ed6SIan Lepore const uint32_t IMX6_ARMMP_PHYS = 0x00a00000; 69034e9ed6SIan Lepore const uint32_t IMX6_ARMMP_SIZE = 0x00100000; 70034e9ed6SIan Lepore const uint32_t IMX6_AIPS1_PHYS = 0x02000000; 71034e9ed6SIan Lepore const uint32_t IMX6_AIPS1_SIZE = 0x00100000; 72034e9ed6SIan Lepore const uint32_t IMX6_AIPS2_PHYS = 0x02100000; 73034e9ed6SIan Lepore const uint32_t IMX6_AIPS2_SIZE = 0x00100000; 74034e9ed6SIan Lepore 75034e9ed6SIan Lepore imx_devmap_addentry(IMX6_ARMMP_PHYS, IMX6_ARMMP_SIZE); 76034e9ed6SIan Lepore imx_devmap_addentry(IMX6_AIPS1_PHYS, IMX6_AIPS1_SIZE); 77034e9ed6SIan Lepore imx_devmap_addentry(IMX6_AIPS2_PHYS, IMX6_AIPS2_SIZE); 78034e9ed6SIan Lepore } 79034e9ed6SIan Lepore 80034e9ed6SIan Lepore void 81034e9ed6SIan Lepore cpu_reset(void) 82034e9ed6SIan Lepore { 83034e9ed6SIan Lepore const uint32_t IMX6_WDOG_CR_PHYS = 0x020bc000; 84034e9ed6SIan Lepore 85034e9ed6SIan Lepore imx_wdog_cpu_reset(IMX6_WDOG_CR_PHYS); 86034e9ed6SIan Lepore } 87034e9ed6SIan Lepore 88034e9ed6SIan Lepore /* 89034e9ed6SIan Lepore * Determine what flavor of imx6 we're running on. 90034e9ed6SIan Lepore * 91034e9ed6SIan Lepore * This code is based on the way u-boot does it. Information found on the web 92034e9ed6SIan Lepore * indicates that Freescale themselves were the original source of this logic, 93034e9ed6SIan Lepore * including the strange check for number of CPUs in the SCU configuration 94034e9ed6SIan Lepore * register, which is apparently needed on some revisions of the SOLO. 95034e9ed6SIan Lepore * 96034e9ed6SIan Lepore * According to the documentation, there is such a thing as an i.MX6 Dual 97034e9ed6SIan Lepore * (non-lite flavor). However, Freescale doesn't seem to have assigned it a 98034e9ed6SIan Lepore * number or provided any logic to handle it in their detection code. 99034e9ed6SIan Lepore * 100034e9ed6SIan Lepore * Note that the ANALOG_DIGPROG and SCU configuration registers are not 101034e9ed6SIan Lepore * documented in the chip reference manual. (SCU configuration is mentioned, 102034e9ed6SIan Lepore * but not mapped out in detail.) I think the bottom two bits of the scu config 103034e9ed6SIan Lepore * register may be ncpu-1. 104034e9ed6SIan Lepore * 105034e9ed6SIan Lepore * This hasn't been tested yet on a dual[-lite]. 106034e9ed6SIan Lepore * 107034e9ed6SIan Lepore * On a solo: 108034e9ed6SIan Lepore * digprog = 0x00610001 109034e9ed6SIan Lepore * hwsoc = 0x00000062 110034e9ed6SIan Lepore * scu config = 0x00000500 111034e9ed6SIan Lepore * On a quad: 112034e9ed6SIan Lepore * digprog = 0x00630002 113034e9ed6SIan Lepore * hwsoc = 0x00000063 114034e9ed6SIan Lepore * scu config = 0x00005503 115034e9ed6SIan Lepore */ 116034e9ed6SIan Lepore u_int imx_soc_type() 117034e9ed6SIan Lepore { 118034e9ed6SIan Lepore uint32_t digprog, hwsoc; 119034e9ed6SIan Lepore uint32_t *pcr; 120034e9ed6SIan Lepore const uint32_t HWSOC_MX6SL = 0x60; 121034e9ed6SIan Lepore const uint32_t HWSOC_MX6DL = 0x61; 122034e9ed6SIan Lepore const uint32_t HWSOC_MX6SOLO = 0x62; 123034e9ed6SIan Lepore const uint32_t HWSOC_MX6Q = 0x63; 124034e9ed6SIan Lepore const vm_offset_t SCU_CONFIG_PHYSADDR = 0x00a00004; 125034e9ed6SIan Lepore 126034e9ed6SIan Lepore digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG_SL); 127034e9ed6SIan Lepore hwsoc = (digprog >> IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) & 128034e9ed6SIan Lepore IMX6_ANALOG_DIGPROG_SOCTYPE_MASK; 129034e9ed6SIan Lepore 130034e9ed6SIan Lepore if (hwsoc != HWSOC_MX6SL) { 131034e9ed6SIan Lepore digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG); 132034e9ed6SIan Lepore hwsoc = (digprog & IMX6_ANALOG_DIGPROG_SOCTYPE_MASK) >> 133034e9ed6SIan Lepore IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT; 134034e9ed6SIan Lepore /*printf("digprog = 0x%08x\n", digprog);*/ 135034e9ed6SIan Lepore if (hwsoc == HWSOC_MX6DL) { 136*13a98c85SIan Lepore pcr = arm_devmap_ptov(SCU_CONFIG_PHYSADDR, 4); 137*13a98c85SIan Lepore if (pcr != NULL) { 138034e9ed6SIan Lepore /*printf("scu config = 0x%08x\n", *pcr);*/ 139034e9ed6SIan Lepore if ((*pcr & 0x03) == 0) { 140034e9ed6SIan Lepore hwsoc = HWSOC_MX6SOLO; 141034e9ed6SIan Lepore } 142034e9ed6SIan Lepore } 143034e9ed6SIan Lepore } 144034e9ed6SIan Lepore } 145034e9ed6SIan Lepore /* printf("hwsoc 0x%08x\n", hwsoc); */ 146034e9ed6SIan Lepore 147034e9ed6SIan Lepore switch (hwsoc) { 148034e9ed6SIan Lepore case HWSOC_MX6SL: 149034e9ed6SIan Lepore return (IMXSOC_6SL); 150034e9ed6SIan Lepore case HWSOC_MX6SOLO: 151034e9ed6SIan Lepore return (IMXSOC_6S); 152034e9ed6SIan Lepore case HWSOC_MX6DL: 153034e9ed6SIan Lepore return (IMXSOC_6DL); 154034e9ed6SIan Lepore case HWSOC_MX6Q : 155034e9ed6SIan Lepore return (IMXSOC_6Q); 156034e9ed6SIan Lepore default: 157034e9ed6SIan Lepore printf("imx_soc_type: Don't understand hwsoc 0x%02x, " 158034e9ed6SIan Lepore "digprog 0x%08x; assuming IMXSOC_6Q\n", hwsoc, digprog); 159034e9ed6SIan Lepore break; 160034e9ed6SIan Lepore } 161034e9ed6SIan Lepore 162034e9ed6SIan Lepore return (IMXSOC_6Q); 163034e9ed6SIan Lepore } 164034e9ed6SIan Lepore 165