xref: /freebsd/sys/arm/freescale/imx/imx6_ccmreg.h (revision 49b49cda41feabe3439f7318e8bf40e3896c7bf4)
1 /*-
2  * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  */
28 
29 #ifndef	IMX6_CCMREG_H
30 #define	IMX6_CCMREG_H
31 
32 #define	CCM_CACCR			0x010
33 #define	CCM_CBCDR			0x014
34 #define	    CBCDR_MMDC_CH1_AXI_PODF_SHIFT	3
35 #define	    CBCDR_MMDC_CH1_AXI_PODF_MASK	(7 << 3)
36 #define	CCM_CSCMR1			0x01C
37 #define	  SSI1_CLK_SEL_S		  10
38 #define	  SSI2_CLK_SEL_S		  12
39 #define	  SSI3_CLK_SEL_S		  14
40 #define	  SSI_CLK_SEL_M			  0x3
41 #define	  SSI_CLK_SEL_508_PFD		  0
42 #define	  SSI_CLK_SEL_454_PFD		  1
43 #define	  SSI_CLK_SEL_PLL4		  2
44 #define	CCM_CSCMR2			0x020
45 #define	  CSCMR2_LDB_DI0_IPU_DIV_SHIFT	  10
46 #define	CCM_CS1CDR			0x028
47 #define	  SSI1_CLK_PODF_SHIFT		  0
48 #define	  SSI1_CLK_PRED_SHIFT		  6
49 #define	  SSI3_CLK_PODF_SHIFT		  16
50 #define	  SSI3_CLK_PRED_SHIFT		  22
51 #define	  SSI_CLK_PODF_MASK		  0x3f
52 #define	  SSI_CLK_PRED_MASK		  0x7
53 #define	CCM_CS2CDR			0x02C
54 #define	  SSI2_CLK_PODF_SHIFT		  0
55 #define	  SSI2_CLK_PRED_SHIFT		  6
56 #define	  LDB_DI0_CLK_SEL_SHIFT		  9
57 #define	  LDB_DI0_CLK_SEL_MASK		  (3 << LDB_DI0_CLK_SEL_SHIFT)
58 #define	CCM_CHSCCDR			0x034
59 #define	  CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
60 #define	  CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT	6
61 #define	  CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
62 #define	  CHSCCDR_IPU1_DI0_PODF_SHIFT		3
63 #define	  CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
64 #define	  CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT	0
65 #define	  CHSCCDR_CLK_SEL_LDB_DI0		3
66 #define	  CHSCCDR_PODF_DIVIDE_BY_3		2
67 #define	  CHSCCDR_IPU_PRE_CLK_540M_PFD		5
68 #define	CCM_CSCDR2			0x038
69 #define	CCM_CLPCR			0x054
70 #define	  CCM_CLPCR_LPM_MASK		  0x03
71 #define	  CCM_CLPCR_LPM_RUN		  0x00
72 #define	  CCM_CLPCR_LPM_WAIT		  0x01
73 #define	  CCM_CLPCR_LPM_STOP		  0x02
74 #define	CCM_CGPR			0x064
75 #define	  CCM_CGPR_INT_MEM_CLK_LPM	  (1 << 17)
76 #define	CCM_CCGR0			0x068
77 #define		CCGR0_AIPS_TZ1			(0x3 << 0)
78 #define		CCGR0_AIPS_TZ2			(0x3 << 2)
79 #define		CCGR0_ABPHDMA			(0x3 << 4)
80 #define	CCM_CCGR1			0x06C
81 #define		CCGR1_ENET			(0x3 << 10)
82 #define		CCGR1_GPT			(0x3 << 20)
83 #define	CCM_CCGR2			0x070
84 #define		CCGR2_HDMI_TX			(0x3 << 0)
85 #define		CCGR2_HDMI_TX_ISFR		(0x3 << 4)
86 #define		CCGR2_I2C1			(0x3 << 6)
87 #define		CCGR2_I2C2			(0x3 << 8)
88 #define		CCGR2_I2C3			(0x3 << 10)
89 #define		CCGR2_IIM			(0x3 << 12)
90 #define		CCGR2_IOMUX_IPT			(0x3 << 14)
91 #define		CCGR2_IPMUX1			(0x3 << 16)
92 #define		CCGR2_IPMUX2			(0x3 << 18)
93 #define		CCGR2_IPMUX3			(0x3 << 20)
94 #define		CCGR2_IPSYNC_IP2APB_TZASC1	(0x3 << 22)
95 #define		CCGR2_IPSYNC_IP2APB_TZASC2	(0x3 << 24)
96 #define		CCGR2_IPSYNC_VDOA		(0x3 << 26)
97 #define	CCM_CCGR3			0x074
98 #define		CCGR3_IPU1_IPU			(0x3 << 0)
99 #define		CCGR3_IPU1_DI0			(0x3 << 2)
100 #define		CCGR3_IPU1_DI1			(0x3 << 4)
101 #define		CCGR3_IPU2_IPU			(0x3 << 6)
102 #define		CCGR3_IPU2_DI0			(0x3 << 8)
103 #define		CCGR3_IPU2_DI1			(0x3 << 10)
104 #define		CCGR3_LDB_DI0			(0x3 << 12)
105 #define		CCGR3_LDB_DI1			(0x3 << 14)
106 #define		CCGR3_MMDC_CORE_ACLK_FAST	(0x3 << 20)
107 #define		CCGR3_CG11			(0x3 << 22)
108 #define		CCGR3_MMDC_CORE_IPG		(0x3 << 24)
109 #define		CCGR3_CG13			(0x3 << 26)
110 #define		CCGR3_OCRAM			(0x3 << 28)
111 #define	CCM_CCGR4			0x078
112 #define		CCGR4_PL301_MX6QFAST1_S133	(0x3 << 8)
113 #define		CCGR4_PL301_MX6QPER1_BCH	(0x3 << 12)
114 #define		CCGR4_PL301_MX6QPER2_MAIN	(0x3 << 14)
115 #define	CCM_CCGR5			0x07C
116 #define		CCGR5_SDMA			(0x3 << 6)
117 #define		CCGR5_SSI1			(0x3 << 18)
118 #define		CCGR5_SSI2			(0x3 << 20)
119 #define		CCGR5_SSI3			(0x3 << 22)
120 #define		CCGR5_UART			(0x3 << 24)
121 #define		CCGR5_UART_SERIAL		(0x3 << 26)
122 #define	CCM_CCGR6			0x080
123 #define		CCGR6_USBOH3			(0x3 << 0)
124 #define		CCGR6_USDHC1			(0x3 << 2)
125 #define		CCGR6_USDHC2			(0x3 << 4)
126 #define		CCGR6_USDHC3			(0x3 << 6)
127 #define		CCGR6_USDHC4			(0x3 << 8)
128 #define	CCM_CMEOR			0x088
129 
130 #endif
131