1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. 33 * Also, temperature montoring and cpu frequency control. It was Freescale who 34 * kitchen-sinked this device, not us. :) 35 * 36 * We don't really do anything with analog PLLs, but the registers for 37 * controlling them belong to the same block as the power regulator registers. 38 * Since the newbus hierarchy makes it hard for anyone other than us to get at 39 * them, we just export a couple public functions to allow the imx6 CCM clock 40 * driver to read and write those registers. 41 * 42 * We also don't do anything about power regulation yet, but when the need 43 * arises, this would be the place for that code to live. 44 * 45 * I have no idea where the "anatop" name comes from. It's in the standard DTS 46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes 47 * from Freescale, but it's not in the SoC manual. 48 * 49 * Note that temperature values throughout this code are handled in two types of 50 * units. Items with '_cnt' in the name use the hardware temperature count 51 * units (higher counts are lower temperatures). Items with '_val' in the name 52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl 53 * handlers (dK is the standard unit for temperature in sysctl). 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/callout.h> 59 #include <sys/kernel.h> 60 #include <sys/limits.h> 61 #include <sys/sysctl.h> 62 #include <sys/module.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include <machine/bus.h> 70 #include <machine/fdt.h> 71 72 #include <arm/arm/mpcore_timervar.h> 73 #include <arm/freescale/fsl_ocotpreg.h> 74 #include <arm/freescale/fsl_ocotpvar.h> 75 #include <arm/freescale/imx/imx6_anatopreg.h> 76 #include <arm/freescale/imx/imx6_anatopvar.h> 77 78 static SYSCTL_NODE(_hw, OID_AUTO, imx6, CTLFLAG_RW, NULL, "i.MX6 container"); 79 80 static struct resource_spec imx6_anatop_spec[] = { 81 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 82 { SYS_RES_IRQ, 0, RF_ACTIVE }, 83 { -1, 0 } 84 }; 85 #define MEMRES 0 86 #define IRQRES 1 87 88 struct imx6_anatop_softc { 89 device_t dev; 90 struct resource *res[2]; 91 struct intr_config_hook 92 intr_setup_hook; 93 uint32_t cpu_curmhz; 94 uint32_t cpu_curmv; 95 uint32_t cpu_minmhz; 96 uint32_t cpu_minmv; 97 uint32_t cpu_maxmhz; 98 uint32_t cpu_maxmv; 99 uint32_t cpu_maxmhz_hw; 100 boolean_t cpu_overclock_enable; 101 boolean_t cpu_init_done; 102 uint32_t refosc_mhz; 103 void *temp_intrhand; 104 uint32_t temp_high_val; 105 uint32_t temp_high_cnt; 106 uint32_t temp_last_cnt; 107 uint32_t temp_room_cnt; 108 struct callout temp_throttle_callout; 109 sbintime_t temp_throttle_delay; 110 uint32_t temp_throttle_reset_cnt; 111 uint32_t temp_throttle_trigger_cnt; 112 uint32_t temp_throttle_val; 113 }; 114 115 static struct imx6_anatop_softc *imx6_anatop_sc; 116 117 /* 118 * Table of "operating points". 119 * These are combinations of frequency and voltage blessed by Freescale. 120 */ 121 static struct oppt { 122 uint32_t mhz; 123 uint32_t mv; 124 } imx6_oppt_table[] = { 125 /* { 396, 925}, XXX: need functional ccm code for this speed */ 126 { 792, 1150}, 127 { 852, 1225}, 128 { 996, 1225}, 129 {1200, 1275}, 130 }; 131 132 /* 133 * Table of CPU max frequencies. This is used to translate the max frequency 134 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 135 * up in the operating points table. 136 */ 137 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; 138 139 #define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */ 140 141 uint32_t 142 imx6_anatop_read_4(bus_size_t offset) 143 { 144 145 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); 146 147 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); 148 } 149 150 void 151 imx6_anatop_write_4(bus_size_t offset, uint32_t value) 152 { 153 154 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); 155 156 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); 157 } 158 159 static void 160 vdd_set(struct imx6_anatop_softc *sc, int mv) 161 { 162 int newtarg, oldtarg; 163 uint32_t delay, pmureg; 164 static boolean_t init_done = false; 165 166 /* 167 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM 168 * can't be more than 50mV above or 200mV below them. For now to keep 169 * things simple we set all three to the same value. 170 */ 171 172 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); 173 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; 174 175 /* Convert mV to target value. Clamp target to valid range. */ 176 if (mv < 725) 177 newtarg = 0x00; 178 else if (mv > 1450) 179 newtarg = 0x1F; 180 else 181 newtarg = (mv - 700) / 25; 182 183 /* 184 * The first time through the 3 voltages might not be equal so use a 185 * long conservative delay. After that we need to delay 3uS for every 186 * 25mV step upward. No need to delay at all when lowering. 187 */ 188 if (init_done) { 189 if (newtarg == oldtarg) 190 return; 191 else if (newtarg > oldtarg) 192 delay = (newtarg - oldtarg) * 3; 193 else 194 delay = 0; 195 } else { 196 delay = 700 / 25 * 3; 197 init_done = true; 198 } 199 200 /* 201 * Make the change and wait for it to take effect. 202 */ 203 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | 204 IMX6_ANALOG_PMU_REG1_TARG_MASK | 205 IMX6_ANALOG_PMU_REG2_TARG_MASK); 206 207 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; 208 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; 209 pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; 210 211 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); 212 DELAY(delay); 213 sc->cpu_curmv = newtarg * 25 + 700; 214 } 215 216 static inline uint32_t 217 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t div) 218 { 219 220 return (sc->refosc_mhz * (div / 2)); 221 } 222 223 static inline uint32_t 224 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 225 { 226 227 return (cpu_mhz / (sc->refosc_mhz / 2)); 228 } 229 230 static inline uint32_t 231 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 232 { 233 234 return (cpufreq_mhz_from_div(sc, cpufreq_mhz_to_div(sc, cpu_mhz))); 235 } 236 237 static struct oppt * 238 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) 239 { 240 int d, diff, i, nearest; 241 242 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) 243 cpu_newmhz = sc->cpu_maxmhz_hw; 244 245 diff = INT_MAX; 246 nearest = 0; 247 for (i = 0; i < nitems(imx6_oppt_table); ++i) { 248 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); 249 if (diff > d) { 250 diff = d; 251 nearest = i; 252 } 253 } 254 return (&imx6_oppt_table[nearest]); 255 } 256 257 static void 258 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) 259 { 260 uint32_t timeout, wrk32; 261 262 /* If increasing the frequency, we must first increase the voltage. */ 263 if (op->mhz > sc->cpu_curmhz) { 264 vdd_set(sc, op->mv); 265 } 266 267 /* 268 * I can't find a documented procedure for changing the ARM PLL divisor, 269 * but some trial and error came up with this: 270 * - Set the bypass clock source to REF_CLK_24M (source #0). 271 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. 272 * - Change the divisor. 273 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. 274 * - Turn off bypass mode; cpu should now be running at the new speed. 275 */ 276 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 277 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); 278 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, 279 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 280 281 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); 282 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 283 wrk32 |= cpufreq_mhz_to_div(sc, op->mhz); 284 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); 285 286 timeout = 10000; 287 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 288 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) 289 if (--timeout == 0) 290 panic("imx6_set_cpu_clock(): PLL never locked"); 291 292 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 293 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 294 295 /* If lowering the frequency, it is now safe to lower the voltage. */ 296 if (op->mhz < sc->cpu_curmhz) 297 vdd_set(sc, op->mv); 298 sc->cpu_curmhz = op->mhz; 299 300 /* Tell the mpcore timer that its frequency has changed. */ 301 arm_tmr_change_frequency( 302 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); 303 } 304 305 static int 306 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) 307 { 308 struct imx6_anatop_softc *sc; 309 struct oppt * op; 310 uint32_t temp; 311 int err; 312 313 sc = arg1; 314 315 temp = sc->cpu_minmhz; 316 err = sysctl_handle_int(oidp, &temp, 0, req); 317 if (err != 0 || req->newptr == NULL) 318 return (err); 319 320 op = cpufreq_nearest_oppt(sc, temp); 321 if (op->mhz > sc->cpu_maxmhz) 322 return (ERANGE); 323 else if (op->mhz == sc->cpu_minmhz) 324 return (0); 325 326 /* 327 * Value changed, update softc. If the new min is higher than the 328 * current speed, raise the current speed to match. 329 */ 330 sc->cpu_minmhz = op->mhz; 331 if (sc->cpu_minmhz > sc->cpu_curmhz) { 332 cpufreq_set_clock(sc, op); 333 } 334 return (err); 335 } 336 337 static int 338 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) 339 { 340 struct imx6_anatop_softc *sc; 341 struct oppt * op; 342 uint32_t temp; 343 int err; 344 345 sc = arg1; 346 347 temp = sc->cpu_maxmhz; 348 err = sysctl_handle_int(oidp, &temp, 0, req); 349 if (err != 0 || req->newptr == NULL) 350 return (err); 351 352 op = cpufreq_nearest_oppt(sc, temp); 353 if (op->mhz < sc->cpu_minmhz) 354 return (ERANGE); 355 else if (op->mhz == sc->cpu_maxmhz) 356 return (0); 357 358 /* 359 * Value changed, update softc and hardware. The hardware update is 360 * unconditional. We always try to run at max speed, so any change of 361 * the max means we need to change the current speed too, regardless of 362 * whether it is higher or lower than the old max. 363 */ 364 sc->cpu_maxmhz = op->mhz; 365 cpufreq_set_clock(sc, op); 366 367 return (err); 368 } 369 370 static void 371 cpufreq_initialize(struct imx6_anatop_softc *sc) 372 { 373 uint32_t cfg3speed; 374 struct oppt * op; 375 376 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 377 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, 378 "CPU frequency"); 379 380 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 381 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 382 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); 383 384 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 385 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 386 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); 387 388 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 389 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, 390 "Maximum CPU frequency allowed by hardware"); 391 392 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 393 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, 394 &sc->cpu_overclock_enable, 0, 395 "Allow setting CPU frequency higher than cpu_maxmhz_hw"); 396 397 /* 398 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm 399 * (even though in the real world it will always be 24mhz). Oh wait a 400 * sec, I never wrote imx6_ccm. 401 */ 402 sc->refosc_mhz = 24; 403 404 /* 405 * Get the maximum speed this cpu can be set to. The values in the 406 * OCOTP CFG3 register are not documented in the reference manual. 407 * The following info was in an archived email found via web search: 408 * - 2b'11: 1200000000Hz; 409 * - 2b'10: 996000000Hz; 410 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 411 * - 2b'00: 792000000Hz; 412 * The default hardware max speed can be overridden by a tunable. 413 */ 414 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & 415 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; 416 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; 417 sc->cpu_maxmhz = sc->cpu_maxmhz_hw; 418 419 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); 420 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); 421 sc->cpu_minmhz = op->mhz; 422 sc->cpu_minmv = op->mv; 423 424 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); 425 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); 426 sc->cpu_maxmhz = op->mhz; 427 sc->cpu_maxmv = op->mv; 428 429 /* 430 * Set the CPU to maximum speed. 431 * 432 * We won't have thermal throttling until interrupts are enabled, but we 433 * want to run at full speed through all the device init stuff. This 434 * basically assumes that a single core can't overheat before interrupts 435 * are enabled; empirical testing shows that to be a safe assumption. 436 */ 437 cpufreq_set_clock(sc, op); 438 } 439 440 static inline uint32_t 441 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) 442 { 443 444 return (((sc->temp_high_val - (count - sc->temp_high_cnt) * 445 (sc->temp_high_val - 250) / 446 (sc->temp_room_cnt - sc->temp_high_cnt)))); 447 } 448 449 static inline uint32_t 450 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) 451 { 452 453 return ((sc->temp_room_cnt - sc->temp_high_cnt) * 454 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + 455 sc->temp_high_cnt); 456 } 457 458 static void 459 temp_update_count(struct imx6_anatop_softc *sc) 460 { 461 uint32_t val; 462 463 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); 464 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) 465 return; 466 sc->temp_last_cnt = 467 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> 468 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; 469 } 470 471 static int 472 temp_sysctl_handler(SYSCTL_HANDLER_ARGS) 473 { 474 struct imx6_anatop_softc *sc = arg1; 475 uint32_t t; 476 477 temp_update_count(sc); 478 479 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; 480 481 return (sysctl_handle_int(oidp, &t, 0, req)); 482 } 483 484 static int 485 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) 486 { 487 struct imx6_anatop_softc *sc = arg1; 488 int err; 489 uint32_t temp; 490 491 temp = sc->temp_throttle_val + TZ_ZEROC; 492 err = sysctl_handle_int(oidp, &temp, 0, req); 493 if (temp < TZ_ZEROC) 494 return (ERANGE); 495 temp -= TZ_ZEROC; 496 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) 497 return (err); 498 499 /* Value changed, update counts in softc and hardware. */ 500 sc->temp_throttle_val = temp; 501 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); 502 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); 503 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, 504 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); 505 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, 506 (sc->temp_throttle_trigger_cnt << 507 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); 508 return (err); 509 } 510 511 static void 512 tempmon_gofast(struct imx6_anatop_softc *sc) 513 { 514 515 if (sc->cpu_curmhz < sc->cpu_maxmhz) { 516 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); 517 } 518 } 519 520 static void 521 tempmon_goslow(struct imx6_anatop_softc *sc) 522 { 523 524 if (sc->cpu_curmhz > sc->cpu_minmhz) { 525 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); 526 } 527 } 528 529 static int 530 tempmon_intr(void *arg) 531 { 532 struct imx6_anatop_softc *sc = arg; 533 534 /* 535 * XXX Note that this code doesn't currently run (for some mysterious 536 * reason we just never get an interrupt), so the real monitoring is 537 * done by tempmon_throttle_check(). 538 */ 539 tempmon_goslow(sc); 540 /* XXX Schedule callout to speed back up eventually. */ 541 return (FILTER_HANDLED); 542 } 543 544 static void 545 tempmon_throttle_check(void *arg) 546 { 547 struct imx6_anatop_softc *sc = arg; 548 549 /* Lower counts are higher temperatures. */ 550 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) 551 tempmon_goslow(sc); 552 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) 553 tempmon_gofast(sc); 554 555 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 556 0, tempmon_throttle_check, sc, 0); 557 558 } 559 560 static void 561 initialize_tempmon(struct imx6_anatop_softc *sc) 562 { 563 uint32_t cal; 564 565 /* 566 * Fetch calibration data: a sensor count at room temperature (25C), 567 * a sensor count at a high temperature, and that temperature 568 */ 569 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); 570 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; 571 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; 572 sc->temp_high_val = (cal & 0x000000FF) * 10; 573 574 /* 575 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and 576 * reset back to max cpu freq at 5C below the trigger. 577 */ 578 sc->temp_throttle_val = sc->temp_high_val - 100; 579 sc->temp_throttle_trigger_cnt = 580 temp_to_count(sc, sc->temp_throttle_val); 581 sc->temp_throttle_reset_cnt = 582 temp_to_count(sc, sc->temp_throttle_val - 50); 583 584 /* 585 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set 586 * the throttle count, and begin making measurements. 587 */ 588 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); 589 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, 590 (sc->temp_throttle_trigger_cnt << 591 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | 592 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); 593 594 /* 595 * XXX Note that the alarm-interrupt feature isn't working yet, so 596 * we'll use a callout handler to check at 10Hz. Make sure we have an 597 * initial temperature reading before starting up the callouts so we 598 * don't get a bogus reading of zero. 599 */ 600 while (sc->temp_last_cnt == 0) 601 temp_update_count(sc); 602 sc->temp_throttle_delay = 100 * SBT_1MS; 603 callout_init(&sc->temp_throttle_callout, 0); 604 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 605 0, tempmon_throttle_check, sc, 0); 606 607 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 608 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0, 609 temp_sysctl_handler, "IK", "Current die temperature"); 610 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 611 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc, 612 0, temp_throttle_sysctl_handler, "IK", 613 "Throttle CPU when exceeding this temperature"); 614 } 615 616 static void 617 intr_setup(void *arg) 618 { 619 struct imx6_anatop_softc *sc; 620 621 sc = arg; 622 bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, 623 tempmon_intr, NULL, sc, &sc->temp_intrhand); 624 config_intrhook_disestablish(&sc->intr_setup_hook); 625 } 626 627 static void 628 imx6_anatop_new_pass(device_t dev) 629 { 630 struct imx6_anatop_softc *sc; 631 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; 632 633 /* 634 * We attach during BUS_PASS_BUS (because some day we will be a 635 * simplebus that has regulator devices as children), but some of our 636 * init work cannot be done until BUS_PASS_CPU (we rely on other devices 637 * that attach on the CPU pass). 638 */ 639 sc = device_get_softc(dev); 640 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { 641 sc->cpu_init_done = true; 642 cpufreq_initialize(sc); 643 initialize_tempmon(sc); 644 if (bootverbose) { 645 device_printf(sc->dev, "CPU %uMHz @ %umV\n", 646 sc->cpu_curmhz, sc->cpu_curmv); 647 } 648 } 649 bus_generic_new_pass(dev); 650 } 651 652 static int 653 imx6_anatop_detach(device_t dev) 654 { 655 656 /* This device can never detach. */ 657 return (EBUSY); 658 } 659 660 static int 661 imx6_anatop_attach(device_t dev) 662 { 663 struct imx6_anatop_softc *sc; 664 int err; 665 666 sc = device_get_softc(dev); 667 sc->dev = dev; 668 669 /* Allocate bus_space resources. */ 670 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { 671 device_printf(dev, "Cannot allocate resources\n"); 672 err = ENXIO; 673 goto out; 674 } 675 676 sc->intr_setup_hook.ich_func = intr_setup; 677 sc->intr_setup_hook.ich_arg = sc; 678 config_intrhook_establish(&sc->intr_setup_hook); 679 680 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), 681 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 682 OID_AUTO, "cpu_voltage", CTLFLAG_RD, 683 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); 684 685 imx6_anatop_sc = sc; 686 687 /* 688 * Other code seen on the net sets this SELFBIASOFF flag around the same 689 * time the temperature sensor is set up, although it's unclear how the 690 * two are related (if at all). 691 */ 692 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, 693 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); 694 695 /* 696 * Some day, when we're ready to deal with the actual anatop regulators 697 * that are described in fdt data as children of this "bus", this would 698 * be the place to invoke a simplebus helper routine to instantiate the 699 * children from the fdt data. 700 */ 701 702 err = 0; 703 704 out: 705 706 if (err != 0) { 707 bus_release_resources(dev, imx6_anatop_spec, sc->res); 708 } 709 710 return (err); 711 } 712 713 uint32_t 714 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 715 { 716 int reg; 717 718 /* 719 * Audio PLL (PLL4). 720 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) 721 */ 722 723 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); 724 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ 725 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 726 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 727 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); 728 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); 729 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); 730 731 return (0); 732 } 733 734 static int 735 imx6_anatop_probe(device_t dev) 736 { 737 738 if (!ofw_bus_status_okay(dev)) 739 return (ENXIO); 740 741 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) 742 return (ENXIO); 743 744 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); 745 746 return (BUS_PROBE_DEFAULT); 747 } 748 749 uint32_t 750 imx6_get_cpu_clock() 751 { 752 uint32_t div; 753 754 div = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 755 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 756 return (cpufreq_mhz_from_div(imx6_anatop_sc, div)); 757 } 758 759 static device_method_t imx6_anatop_methods[] = { 760 /* Device interface */ 761 DEVMETHOD(device_probe, imx6_anatop_probe), 762 DEVMETHOD(device_attach, imx6_anatop_attach), 763 DEVMETHOD(device_detach, imx6_anatop_detach), 764 765 /* Bus interface */ 766 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), 767 768 DEVMETHOD_END 769 }; 770 771 static driver_t imx6_anatop_driver = { 772 "imx6_anatop", 773 imx6_anatop_methods, 774 sizeof(struct imx6_anatop_softc) 775 }; 776 777 static devclass_t imx6_anatop_devclass; 778 779 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 780 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 781 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 782 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 783 784