1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. 33 * Also, temperature montoring and cpu frequency control. It was Freescale who 34 * kitchen-sinked this device, not us. :) 35 * 36 * We don't really do anything with analog PLLs, but the registers for 37 * controlling them belong to the same block as the power regulator registers. 38 * Since the newbus hierarchy makes it hard for anyone other than us to get at 39 * them, we just export a couple public functions to allow the imx6 CCM clock 40 * driver to read and write those registers. 41 * 42 * We also don't do anything about power regulation yet, but when the need 43 * arises, this would be the place for that code to live. 44 * 45 * I have no idea where the "anatop" name comes from. It's in the standard DTS 46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes 47 * from Freescale, but it's not in the SoC manual. 48 * 49 * Note that temperature values throughout this code are handled in two types of 50 * units. Items with '_cnt' in the name use the hardware temperature count 51 * units (higher counts are lower temperatures). Items with '_val' in the name 52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl 53 * handlers (dK is the standard unit for temperature in sysctl). 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/callout.h> 59 #include <sys/kernel.h> 60 #include <sys/limits.h> 61 #include <sys/sysctl.h> 62 #include <sys/module.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include <machine/bus.h> 70 71 #include <arm/arm/mpcore_timervar.h> 72 #include <arm/freescale/fsl_ocotpreg.h> 73 #include <arm/freescale/fsl_ocotpvar.h> 74 #include <arm/freescale/imx/imx6_anatopreg.h> 75 #include <arm/freescale/imx/imx6_anatopvar.h> 76 77 static SYSCTL_NODE(_hw, OID_AUTO, imx6, CTLFLAG_RW, NULL, "i.MX6 container"); 78 79 static struct resource_spec imx6_anatop_spec[] = { 80 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 81 { SYS_RES_IRQ, 0, RF_ACTIVE }, 82 { -1, 0 } 83 }; 84 #define MEMRES 0 85 #define IRQRES 1 86 87 struct imx6_anatop_softc { 88 device_t dev; 89 struct resource *res[2]; 90 struct intr_config_hook 91 intr_setup_hook; 92 uint32_t cpu_curmhz; 93 uint32_t cpu_curmv; 94 uint32_t cpu_minmhz; 95 uint32_t cpu_minmv; 96 uint32_t cpu_maxmhz; 97 uint32_t cpu_maxmv; 98 uint32_t cpu_maxmhz_hw; 99 boolean_t cpu_overclock_enable; 100 boolean_t cpu_init_done; 101 uint32_t refosc_mhz; 102 void *temp_intrhand; 103 uint32_t temp_high_val; 104 uint32_t temp_high_cnt; 105 uint32_t temp_last_cnt; 106 uint32_t temp_room_cnt; 107 struct callout temp_throttle_callout; 108 sbintime_t temp_throttle_delay; 109 uint32_t temp_throttle_reset_cnt; 110 uint32_t temp_throttle_trigger_cnt; 111 uint32_t temp_throttle_val; 112 }; 113 114 static struct imx6_anatop_softc *imx6_anatop_sc; 115 116 /* 117 * Table of "operating points". 118 * These are combinations of frequency and voltage blessed by Freescale. 119 */ 120 static struct oppt { 121 uint32_t mhz; 122 uint32_t mv; 123 } imx6_oppt_table[] = { 124 /* { 396, 925}, XXX: need functional ccm code for this speed */ 125 { 792, 1150}, 126 { 852, 1225}, 127 { 996, 1225}, 128 {1200, 1275}, 129 }; 130 131 /* 132 * Table of CPU max frequencies. This is used to translate the max frequency 133 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 134 * up in the operating points table. 135 */ 136 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; 137 138 #define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */ 139 140 uint32_t 141 imx6_anatop_read_4(bus_size_t offset) 142 { 143 144 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); 145 146 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); 147 } 148 149 void 150 imx6_anatop_write_4(bus_size_t offset, uint32_t value) 151 { 152 153 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); 154 155 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); 156 } 157 158 static void 159 vdd_set(struct imx6_anatop_softc *sc, int mv) 160 { 161 int newtarg, oldtarg; 162 uint32_t delay, pmureg; 163 static boolean_t init_done = false; 164 165 /* 166 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM 167 * can't be more than 50mV above or 200mV below them. For now to keep 168 * things simple we set all three to the same value. 169 */ 170 171 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); 172 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; 173 174 /* Convert mV to target value. Clamp target to valid range. */ 175 if (mv < 725) 176 newtarg = 0x00; 177 else if (mv > 1450) 178 newtarg = 0x1F; 179 else 180 newtarg = (mv - 700) / 25; 181 182 /* 183 * The first time through the 3 voltages might not be equal so use a 184 * long conservative delay. After that we need to delay 3uS for every 185 * 25mV step upward. No need to delay at all when lowering. 186 */ 187 if (init_done) { 188 if (newtarg == oldtarg) 189 return; 190 else if (newtarg > oldtarg) 191 delay = (newtarg - oldtarg) * 3; 192 else 193 delay = 0; 194 } else { 195 delay = 700 / 25 * 3; 196 init_done = true; 197 } 198 199 /* 200 * Make the change and wait for it to take effect. 201 */ 202 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | 203 IMX6_ANALOG_PMU_REG1_TARG_MASK | 204 IMX6_ANALOG_PMU_REG2_TARG_MASK); 205 206 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; 207 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; 208 pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; 209 210 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); 211 DELAY(delay); 212 sc->cpu_curmv = newtarg * 25 + 700; 213 } 214 215 static inline uint32_t 216 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t div) 217 { 218 219 return (sc->refosc_mhz * (div / 2)); 220 } 221 222 static inline uint32_t 223 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 224 { 225 226 return (cpu_mhz / (sc->refosc_mhz / 2)); 227 } 228 229 static inline uint32_t 230 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 231 { 232 233 return (cpufreq_mhz_from_div(sc, cpufreq_mhz_to_div(sc, cpu_mhz))); 234 } 235 236 static struct oppt * 237 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) 238 { 239 int d, diff, i, nearest; 240 241 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) 242 cpu_newmhz = sc->cpu_maxmhz_hw; 243 244 diff = INT_MAX; 245 nearest = 0; 246 for (i = 0; i < nitems(imx6_oppt_table); ++i) { 247 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); 248 if (diff > d) { 249 diff = d; 250 nearest = i; 251 } 252 } 253 return (&imx6_oppt_table[nearest]); 254 } 255 256 static void 257 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) 258 { 259 uint32_t timeout, wrk32; 260 261 /* If increasing the frequency, we must first increase the voltage. */ 262 if (op->mhz > sc->cpu_curmhz) { 263 vdd_set(sc, op->mv); 264 } 265 266 /* 267 * I can't find a documented procedure for changing the ARM PLL divisor, 268 * but some trial and error came up with this: 269 * - Set the bypass clock source to REF_CLK_24M (source #0). 270 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. 271 * - Change the divisor. 272 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. 273 * - Turn off bypass mode; cpu should now be running at the new speed. 274 */ 275 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 276 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); 277 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, 278 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 279 280 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); 281 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 282 wrk32 |= cpufreq_mhz_to_div(sc, op->mhz); 283 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); 284 285 timeout = 10000; 286 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 287 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) 288 if (--timeout == 0) 289 panic("imx6_set_cpu_clock(): PLL never locked"); 290 291 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 292 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 293 294 /* If lowering the frequency, it is now safe to lower the voltage. */ 295 if (op->mhz < sc->cpu_curmhz) 296 vdd_set(sc, op->mv); 297 sc->cpu_curmhz = op->mhz; 298 299 /* Tell the mpcore timer that its frequency has changed. */ 300 arm_tmr_change_frequency( 301 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); 302 } 303 304 static int 305 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) 306 { 307 struct imx6_anatop_softc *sc; 308 struct oppt * op; 309 uint32_t temp; 310 int err; 311 312 sc = arg1; 313 314 temp = sc->cpu_minmhz; 315 err = sysctl_handle_int(oidp, &temp, 0, req); 316 if (err != 0 || req->newptr == NULL) 317 return (err); 318 319 op = cpufreq_nearest_oppt(sc, temp); 320 if (op->mhz > sc->cpu_maxmhz) 321 return (ERANGE); 322 else if (op->mhz == sc->cpu_minmhz) 323 return (0); 324 325 /* 326 * Value changed, update softc. If the new min is higher than the 327 * current speed, raise the current speed to match. 328 */ 329 sc->cpu_minmhz = op->mhz; 330 if (sc->cpu_minmhz > sc->cpu_curmhz) { 331 cpufreq_set_clock(sc, op); 332 } 333 return (err); 334 } 335 336 static int 337 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) 338 { 339 struct imx6_anatop_softc *sc; 340 struct oppt * op; 341 uint32_t temp; 342 int err; 343 344 sc = arg1; 345 346 temp = sc->cpu_maxmhz; 347 err = sysctl_handle_int(oidp, &temp, 0, req); 348 if (err != 0 || req->newptr == NULL) 349 return (err); 350 351 op = cpufreq_nearest_oppt(sc, temp); 352 if (op->mhz < sc->cpu_minmhz) 353 return (ERANGE); 354 else if (op->mhz == sc->cpu_maxmhz) 355 return (0); 356 357 /* 358 * Value changed, update softc and hardware. The hardware update is 359 * unconditional. We always try to run at max speed, so any change of 360 * the max means we need to change the current speed too, regardless of 361 * whether it is higher or lower than the old max. 362 */ 363 sc->cpu_maxmhz = op->mhz; 364 cpufreq_set_clock(sc, op); 365 366 return (err); 367 } 368 369 static void 370 cpufreq_initialize(struct imx6_anatop_softc *sc) 371 { 372 uint32_t cfg3speed; 373 struct oppt * op; 374 375 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 376 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, 377 "CPU frequency"); 378 379 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 380 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 381 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); 382 383 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 384 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 385 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); 386 387 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 388 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, 389 "Maximum CPU frequency allowed by hardware"); 390 391 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 392 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, 393 &sc->cpu_overclock_enable, 0, 394 "Allow setting CPU frequency higher than cpu_maxmhz_hw"); 395 396 /* 397 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm 398 * (even though in the real world it will always be 24mhz). Oh wait a 399 * sec, I never wrote imx6_ccm. 400 */ 401 sc->refosc_mhz = 24; 402 403 /* 404 * Get the maximum speed this cpu can be set to. The values in the 405 * OCOTP CFG3 register are not documented in the reference manual. 406 * The following info was in an archived email found via web search: 407 * - 2b'11: 1200000000Hz; 408 * - 2b'10: 996000000Hz; 409 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 410 * - 2b'00: 792000000Hz; 411 * The default hardware max speed can be overridden by a tunable. 412 */ 413 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & 414 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; 415 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; 416 sc->cpu_maxmhz = sc->cpu_maxmhz_hw; 417 418 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); 419 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); 420 sc->cpu_minmhz = op->mhz; 421 sc->cpu_minmv = op->mv; 422 423 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); 424 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); 425 sc->cpu_maxmhz = op->mhz; 426 sc->cpu_maxmv = op->mv; 427 428 /* 429 * Set the CPU to maximum speed. 430 * 431 * We won't have thermal throttling until interrupts are enabled, but we 432 * want to run at full speed through all the device init stuff. This 433 * basically assumes that a single core can't overheat before interrupts 434 * are enabled; empirical testing shows that to be a safe assumption. 435 */ 436 cpufreq_set_clock(sc, op); 437 } 438 439 static inline uint32_t 440 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) 441 { 442 443 return (((sc->temp_high_val - (count - sc->temp_high_cnt) * 444 (sc->temp_high_val - 250) / 445 (sc->temp_room_cnt - sc->temp_high_cnt)))); 446 } 447 448 static inline uint32_t 449 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) 450 { 451 452 return ((sc->temp_room_cnt - sc->temp_high_cnt) * 453 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + 454 sc->temp_high_cnt); 455 } 456 457 static void 458 temp_update_count(struct imx6_anatop_softc *sc) 459 { 460 uint32_t val; 461 462 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); 463 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) 464 return; 465 sc->temp_last_cnt = 466 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> 467 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; 468 } 469 470 static int 471 temp_sysctl_handler(SYSCTL_HANDLER_ARGS) 472 { 473 struct imx6_anatop_softc *sc = arg1; 474 uint32_t t; 475 476 temp_update_count(sc); 477 478 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; 479 480 return (sysctl_handle_int(oidp, &t, 0, req)); 481 } 482 483 static int 484 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) 485 { 486 struct imx6_anatop_softc *sc = arg1; 487 int err; 488 uint32_t temp; 489 490 temp = sc->temp_throttle_val + TZ_ZEROC; 491 err = sysctl_handle_int(oidp, &temp, 0, req); 492 if (temp < TZ_ZEROC) 493 return (ERANGE); 494 temp -= TZ_ZEROC; 495 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) 496 return (err); 497 498 /* Value changed, update counts in softc and hardware. */ 499 sc->temp_throttle_val = temp; 500 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); 501 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); 502 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, 503 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); 504 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, 505 (sc->temp_throttle_trigger_cnt << 506 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); 507 return (err); 508 } 509 510 static void 511 tempmon_gofast(struct imx6_anatop_softc *sc) 512 { 513 514 if (sc->cpu_curmhz < sc->cpu_maxmhz) { 515 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); 516 } 517 } 518 519 static void 520 tempmon_goslow(struct imx6_anatop_softc *sc) 521 { 522 523 if (sc->cpu_curmhz > sc->cpu_minmhz) { 524 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); 525 } 526 } 527 528 static int 529 tempmon_intr(void *arg) 530 { 531 struct imx6_anatop_softc *sc = arg; 532 533 /* 534 * XXX Note that this code doesn't currently run (for some mysterious 535 * reason we just never get an interrupt), so the real monitoring is 536 * done by tempmon_throttle_check(). 537 */ 538 tempmon_goslow(sc); 539 /* XXX Schedule callout to speed back up eventually. */ 540 return (FILTER_HANDLED); 541 } 542 543 static void 544 tempmon_throttle_check(void *arg) 545 { 546 struct imx6_anatop_softc *sc = arg; 547 548 /* Lower counts are higher temperatures. */ 549 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) 550 tempmon_goslow(sc); 551 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) 552 tempmon_gofast(sc); 553 554 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 555 0, tempmon_throttle_check, sc, 0); 556 557 } 558 559 static void 560 initialize_tempmon(struct imx6_anatop_softc *sc) 561 { 562 uint32_t cal; 563 564 /* 565 * Fetch calibration data: a sensor count at room temperature (25C), 566 * a sensor count at a high temperature, and that temperature 567 */ 568 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); 569 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; 570 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; 571 sc->temp_high_val = (cal & 0x000000FF) * 10; 572 573 /* 574 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and 575 * reset back to max cpu freq at 5C below the trigger. 576 */ 577 sc->temp_throttle_val = sc->temp_high_val - 100; 578 sc->temp_throttle_trigger_cnt = 579 temp_to_count(sc, sc->temp_throttle_val); 580 sc->temp_throttle_reset_cnt = 581 temp_to_count(sc, sc->temp_throttle_val - 50); 582 583 /* 584 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set 585 * the throttle count, and begin making measurements. 586 */ 587 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); 588 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, 589 (sc->temp_throttle_trigger_cnt << 590 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | 591 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); 592 593 /* 594 * XXX Note that the alarm-interrupt feature isn't working yet, so 595 * we'll use a callout handler to check at 10Hz. Make sure we have an 596 * initial temperature reading before starting up the callouts so we 597 * don't get a bogus reading of zero. 598 */ 599 while (sc->temp_last_cnt == 0) 600 temp_update_count(sc); 601 sc->temp_throttle_delay = 100 * SBT_1MS; 602 callout_init(&sc->temp_throttle_callout, 0); 603 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 604 0, tempmon_throttle_check, sc, 0); 605 606 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 607 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0, 608 temp_sysctl_handler, "IK", "Current die temperature"); 609 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6), 610 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc, 611 0, temp_throttle_sysctl_handler, "IK", 612 "Throttle CPU when exceeding this temperature"); 613 } 614 615 static void 616 intr_setup(void *arg) 617 { 618 struct imx6_anatop_softc *sc; 619 620 sc = arg; 621 bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, 622 tempmon_intr, NULL, sc, &sc->temp_intrhand); 623 config_intrhook_disestablish(&sc->intr_setup_hook); 624 } 625 626 static void 627 imx6_anatop_new_pass(device_t dev) 628 { 629 struct imx6_anatop_softc *sc; 630 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; 631 632 /* 633 * We attach during BUS_PASS_BUS (because some day we will be a 634 * simplebus that has regulator devices as children), but some of our 635 * init work cannot be done until BUS_PASS_CPU (we rely on other devices 636 * that attach on the CPU pass). 637 */ 638 sc = device_get_softc(dev); 639 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { 640 sc->cpu_init_done = true; 641 cpufreq_initialize(sc); 642 initialize_tempmon(sc); 643 if (bootverbose) { 644 device_printf(sc->dev, "CPU %uMHz @ %umV\n", 645 sc->cpu_curmhz, sc->cpu_curmv); 646 } 647 } 648 bus_generic_new_pass(dev); 649 } 650 651 static int 652 imx6_anatop_detach(device_t dev) 653 { 654 655 /* This device can never detach. */ 656 return (EBUSY); 657 } 658 659 static int 660 imx6_anatop_attach(device_t dev) 661 { 662 struct imx6_anatop_softc *sc; 663 int err; 664 665 sc = device_get_softc(dev); 666 sc->dev = dev; 667 668 /* Allocate bus_space resources. */ 669 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { 670 device_printf(dev, "Cannot allocate resources\n"); 671 err = ENXIO; 672 goto out; 673 } 674 675 sc->intr_setup_hook.ich_func = intr_setup; 676 sc->intr_setup_hook.ich_arg = sc; 677 config_intrhook_establish(&sc->intr_setup_hook); 678 679 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), 680 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 681 OID_AUTO, "cpu_voltage", CTLFLAG_RD, 682 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); 683 684 imx6_anatop_sc = sc; 685 686 /* 687 * Other code seen on the net sets this SELFBIASOFF flag around the same 688 * time the temperature sensor is set up, although it's unclear how the 689 * two are related (if at all). 690 */ 691 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, 692 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); 693 694 /* 695 * Some day, when we're ready to deal with the actual anatop regulators 696 * that are described in fdt data as children of this "bus", this would 697 * be the place to invoke a simplebus helper routine to instantiate the 698 * children from the fdt data. 699 */ 700 701 err = 0; 702 703 out: 704 705 if (err != 0) { 706 bus_release_resources(dev, imx6_anatop_spec, sc->res); 707 } 708 709 return (err); 710 } 711 712 uint32_t 713 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 714 { 715 int reg; 716 717 /* 718 * Audio PLL (PLL4). 719 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) 720 */ 721 722 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); 723 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ 724 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 725 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 726 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); 727 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); 728 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); 729 730 return (0); 731 } 732 733 static int 734 imx6_anatop_probe(device_t dev) 735 { 736 737 if (!ofw_bus_status_okay(dev)) 738 return (ENXIO); 739 740 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) 741 return (ENXIO); 742 743 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); 744 745 return (BUS_PROBE_DEFAULT); 746 } 747 748 uint32_t 749 imx6_get_cpu_clock() 750 { 751 uint32_t div; 752 753 div = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 754 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 755 return (cpufreq_mhz_from_div(imx6_anatop_sc, div)); 756 } 757 758 static device_method_t imx6_anatop_methods[] = { 759 /* Device interface */ 760 DEVMETHOD(device_probe, imx6_anatop_probe), 761 DEVMETHOD(device_attach, imx6_anatop_attach), 762 DEVMETHOD(device_detach, imx6_anatop_detach), 763 764 /* Bus interface */ 765 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), 766 767 DEVMETHOD_END 768 }; 769 770 static driver_t imx6_anatop_driver = { 771 "imx6_anatop", 772 imx6_anatop_methods, 773 sizeof(struct imx6_anatop_softc) 774 }; 775 776 static devclass_t imx6_anatop_devclass; 777 778 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 779 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 780 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 781 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 782 783