1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. 33 * Also, temperature montoring and cpu frequency control. It was Freescale who 34 * kitchen-sinked this device, not us. :) 35 * 36 * We don't really do anything with analog PLLs, but the registers for 37 * controlling them belong to the same block as the power regulator registers. 38 * Since the newbus hierarchy makes it hard for anyone other than us to get at 39 * them, we just export a couple public functions to allow the imx6 CCM clock 40 * driver to read and write those registers. 41 * 42 * We also don't do anything about power regulation yet, but when the need 43 * arises, this would be the place for that code to live. 44 * 45 * I have no idea where the "anatop" name comes from. It's in the standard DTS 46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes 47 * from Freescale, but it's not in the SoC manual. 48 * 49 * Note that temperature values throughout this code are handled in two types of 50 * units. Items with '_cnt' in the name use the hardware temperature count 51 * units (higher counts are lower temperatures). Items with '_val' in the name 52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl 53 * handlers (dK is the standard unit for temperature in sysctl). 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/callout.h> 59 #include <sys/kernel.h> 60 #include <sys/limits.h> 61 #include <sys/sysctl.h> 62 #include <sys/module.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include <machine/bus.h> 70 71 #include <arm/arm/mpcore_timervar.h> 72 #include <arm/freescale/fsl_ocotpreg.h> 73 #include <arm/freescale/fsl_ocotpvar.h> 74 #include <arm/freescale/imx/imx_ccmvar.h> 75 #include <arm/freescale/imx/imx_machdep.h> 76 #include <arm/freescale/imx/imx6_anatopreg.h> 77 #include <arm/freescale/imx/imx6_anatopvar.h> 78 79 static struct resource_spec imx6_anatop_spec[] = { 80 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 81 { SYS_RES_IRQ, 0, RF_ACTIVE }, 82 { -1, 0 } 83 }; 84 #define MEMRES 0 85 #define IRQRES 1 86 87 struct imx6_anatop_softc { 88 device_t dev; 89 struct resource *res[2]; 90 struct intr_config_hook 91 intr_setup_hook; 92 uint32_t cpu_curmhz; 93 uint32_t cpu_curmv; 94 uint32_t cpu_minmhz; 95 uint32_t cpu_minmv; 96 uint32_t cpu_maxmhz; 97 uint32_t cpu_maxmv; 98 uint32_t cpu_maxmhz_hw; 99 boolean_t cpu_overclock_enable; 100 boolean_t cpu_init_done; 101 uint32_t refosc_mhz; 102 void *temp_intrhand; 103 uint32_t temp_high_val; 104 uint32_t temp_high_cnt; 105 uint32_t temp_last_cnt; 106 uint32_t temp_room_cnt; 107 struct callout temp_throttle_callout; 108 sbintime_t temp_throttle_delay; 109 uint32_t temp_throttle_reset_cnt; 110 uint32_t temp_throttle_trigger_cnt; 111 uint32_t temp_throttle_val; 112 }; 113 114 static struct imx6_anatop_softc *imx6_anatop_sc; 115 116 /* 117 * Table of "operating points". 118 * These are combinations of frequency and voltage blessed by Freescale. 119 * While the datasheet says the ARM voltage can be as low as 925mV at 120 * 396MHz, it also says that the ARM and SOC voltages can't differ by 121 * more than 200mV, and the minimum SOC voltage is 1150mV, so that 122 * dictates the 950mV entry in this table. 123 */ 124 static struct oppt { 125 uint32_t mhz; 126 uint32_t mv; 127 } imx6_oppt_table[] = { 128 { 396, 950}, 129 { 792, 1150}, 130 { 852, 1225}, 131 { 996, 1225}, 132 {1200, 1275}, 133 }; 134 135 /* 136 * Table of CPU max frequencies. This is used to translate the max frequency 137 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 138 * up in the operating points table. 139 */ 140 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; 141 142 #define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */ 143 144 uint32_t 145 imx6_anatop_read_4(bus_size_t offset) 146 { 147 148 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); 149 150 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); 151 } 152 153 void 154 imx6_anatop_write_4(bus_size_t offset, uint32_t value) 155 { 156 157 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); 158 159 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); 160 } 161 162 static void 163 vdd_set(struct imx6_anatop_softc *sc, int mv) 164 { 165 int newtarg, newtargSoc, oldtarg; 166 uint32_t delay, pmureg; 167 static boolean_t init_done = false; 168 169 /* 170 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM 171 * can't be more than 50mV above or 200mV below them. We keep them the 172 * same except in the case of the lowest operating point, which is 173 * handled as a special case below. 174 */ 175 176 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); 177 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; 178 179 /* Convert mV to target value. Clamp target to valid range. */ 180 if (mv < 725) 181 newtarg = 0x00; 182 else if (mv > 1450) 183 newtarg = 0x1F; 184 else 185 newtarg = (mv - 700) / 25; 186 187 /* 188 * The SOC voltage can't go below 1150mV, and thus because of the 200mV 189 * rule, the ARM voltage can't go below 950mV. The 950 is encoded in 190 * our oppt table, here we handle the SOC 1150 rule as a special case. 191 * (1150-700/25=18). 192 */ 193 newtargSoc = (newtarg < 18) ? 18 : newtarg; 194 195 /* 196 * The first time through the 3 voltages might not be equal so use a 197 * long conservative delay. After that we need to delay 3uS for every 198 * 25mV step upward; we actually delay 6uS because empirically, it works 199 * and the 3uS per step recommended by the docs doesn't (3uS fails when 200 * going from 400->1200, but works for smaller changes). 201 */ 202 if (init_done) { 203 if (newtarg == oldtarg) 204 return; 205 else if (newtarg > oldtarg) 206 delay = (newtarg - oldtarg) * 6; 207 else 208 delay = 0; 209 } else { 210 delay = (700 / 25) * 6; 211 init_done = true; 212 } 213 214 /* 215 * Make the change and wait for it to take effect. 216 */ 217 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | 218 IMX6_ANALOG_PMU_REG1_TARG_MASK | 219 IMX6_ANALOG_PMU_REG2_TARG_MASK); 220 221 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; 222 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; 223 pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; 224 225 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); 226 DELAY(delay); 227 sc->cpu_curmv = newtarg * 25 + 700; 228 } 229 230 static inline uint32_t 231 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv, 232 uint32_t plldiv) 233 { 234 235 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1)); 236 } 237 238 static inline void 239 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz, 240 uint32_t *corediv, uint32_t *plldiv) 241 { 242 243 *corediv = (cpu_mhz < 650) ? 1 : 0; 244 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2); 245 } 246 247 static inline uint32_t 248 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 249 { 250 uint32_t corediv, plldiv; 251 252 cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv); 253 return (cpufreq_mhz_from_div(sc, corediv, plldiv)); 254 } 255 256 static struct oppt * 257 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) 258 { 259 int d, diff, i, nearest; 260 261 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) 262 cpu_newmhz = sc->cpu_maxmhz_hw; 263 264 diff = INT_MAX; 265 nearest = 0; 266 for (i = 0; i < nitems(imx6_oppt_table); ++i) { 267 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); 268 if (diff > d) { 269 diff = d; 270 nearest = i; 271 } 272 } 273 return (&imx6_oppt_table[nearest]); 274 } 275 276 static void 277 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) 278 { 279 uint32_t corediv, plldiv, timeout, wrk32; 280 281 /* If increasing the frequency, we must first increase the voltage. */ 282 if (op->mhz > sc->cpu_curmhz) { 283 vdd_set(sc, op->mv); 284 } 285 286 /* 287 * I can't find a documented procedure for changing the ARM PLL divisor, 288 * but some trial and error came up with this: 289 * - Set the bypass clock source to REF_CLK_24M (source #0). 290 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. 291 * - Change the divisor. 292 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. 293 * - Turn off bypass mode; cpu should now be running at the new speed. 294 */ 295 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); 296 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 297 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); 298 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, 299 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 300 301 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); 302 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 303 wrk32 |= plldiv; 304 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); 305 306 timeout = 10000; 307 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 308 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) 309 if (--timeout == 0) 310 panic("imx6_set_cpu_clock(): PLL never locked"); 311 312 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 313 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 314 imx_ccm_set_cacrr(corediv); 315 316 /* If lowering the frequency, it is now safe to lower the voltage. */ 317 if (op->mhz < sc->cpu_curmhz) 318 vdd_set(sc, op->mv); 319 sc->cpu_curmhz = op->mhz; 320 321 /* Tell the mpcore timer that its frequency has changed. */ 322 arm_tmr_change_frequency( 323 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); 324 } 325 326 static int 327 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) 328 { 329 struct imx6_anatop_softc *sc; 330 struct oppt * op; 331 uint32_t temp; 332 int err; 333 334 sc = arg1; 335 336 temp = sc->cpu_minmhz; 337 err = sysctl_handle_int(oidp, &temp, 0, req); 338 if (err != 0 || req->newptr == NULL) 339 return (err); 340 341 op = cpufreq_nearest_oppt(sc, temp); 342 if (op->mhz > sc->cpu_maxmhz) 343 return (ERANGE); 344 else if (op->mhz == sc->cpu_minmhz) 345 return (0); 346 347 /* 348 * Value changed, update softc. If the new min is higher than the 349 * current speed, raise the current speed to match. 350 */ 351 sc->cpu_minmhz = op->mhz; 352 if (sc->cpu_minmhz > sc->cpu_curmhz) { 353 cpufreq_set_clock(sc, op); 354 } 355 return (err); 356 } 357 358 static int 359 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) 360 { 361 struct imx6_anatop_softc *sc; 362 struct oppt * op; 363 uint32_t temp; 364 int err; 365 366 sc = arg1; 367 368 temp = sc->cpu_maxmhz; 369 err = sysctl_handle_int(oidp, &temp, 0, req); 370 if (err != 0 || req->newptr == NULL) 371 return (err); 372 373 op = cpufreq_nearest_oppt(sc, temp); 374 if (op->mhz < sc->cpu_minmhz) 375 return (ERANGE); 376 else if (op->mhz == sc->cpu_maxmhz) 377 return (0); 378 379 /* 380 * Value changed, update softc and hardware. The hardware update is 381 * unconditional. We always try to run at max speed, so any change of 382 * the max means we need to change the current speed too, regardless of 383 * whether it is higher or lower than the old max. 384 */ 385 sc->cpu_maxmhz = op->mhz; 386 cpufreq_set_clock(sc, op); 387 388 return (err); 389 } 390 391 static void 392 cpufreq_initialize(struct imx6_anatop_softc *sc) 393 { 394 uint32_t cfg3speed; 395 struct oppt * op; 396 397 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 398 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, 399 "CPU frequency"); 400 401 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 402 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 403 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); 404 405 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 406 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 407 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); 408 409 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 410 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, 411 "Maximum CPU frequency allowed by hardware"); 412 413 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 414 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, 415 &sc->cpu_overclock_enable, 0, 416 "Allow setting CPU frequency higher than cpu_maxmhz_hw"); 417 418 /* 419 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm 420 * (even though in the real world it will always be 24mhz). Oh wait a 421 * sec, I never wrote imx6_ccm. 422 */ 423 sc->refosc_mhz = 24; 424 425 /* 426 * Get the maximum speed this cpu can be set to. The values in the 427 * OCOTP CFG3 register are not documented in the reference manual. 428 * The following info was in an archived email found via web search: 429 * - 2b'11: 1200000000Hz; 430 * - 2b'10: 996000000Hz; 431 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 432 * - 2b'00: 792000000Hz; 433 * The default hardware max speed can be overridden by a tunable. 434 */ 435 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & 436 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; 437 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; 438 sc->cpu_maxmhz = sc->cpu_maxmhz_hw; 439 440 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); 441 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); 442 sc->cpu_minmhz = op->mhz; 443 sc->cpu_minmv = op->mv; 444 445 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); 446 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); 447 sc->cpu_maxmhz = op->mhz; 448 sc->cpu_maxmv = op->mv; 449 450 /* 451 * Set the CPU to maximum speed. 452 * 453 * We won't have thermal throttling until interrupts are enabled, but we 454 * want to run at full speed through all the device init stuff. This 455 * basically assumes that a single core can't overheat before interrupts 456 * are enabled; empirical testing shows that to be a safe assumption. 457 */ 458 cpufreq_set_clock(sc, op); 459 } 460 461 static inline uint32_t 462 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) 463 { 464 465 return (((sc->temp_high_val - (count - sc->temp_high_cnt) * 466 (sc->temp_high_val - 250) / 467 (sc->temp_room_cnt - sc->temp_high_cnt)))); 468 } 469 470 static inline uint32_t 471 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) 472 { 473 474 return ((sc->temp_room_cnt - sc->temp_high_cnt) * 475 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + 476 sc->temp_high_cnt); 477 } 478 479 static void 480 temp_update_count(struct imx6_anatop_softc *sc) 481 { 482 uint32_t val; 483 484 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); 485 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) 486 return; 487 sc->temp_last_cnt = 488 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> 489 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; 490 } 491 492 static int 493 temp_sysctl_handler(SYSCTL_HANDLER_ARGS) 494 { 495 struct imx6_anatop_softc *sc = arg1; 496 uint32_t t; 497 498 temp_update_count(sc); 499 500 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; 501 502 return (sysctl_handle_int(oidp, &t, 0, req)); 503 } 504 505 static int 506 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) 507 { 508 struct imx6_anatop_softc *sc = arg1; 509 int err; 510 uint32_t temp; 511 512 temp = sc->temp_throttle_val + TZ_ZEROC; 513 err = sysctl_handle_int(oidp, &temp, 0, req); 514 if (temp < TZ_ZEROC) 515 return (ERANGE); 516 temp -= TZ_ZEROC; 517 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) 518 return (err); 519 520 /* Value changed, update counts in softc and hardware. */ 521 sc->temp_throttle_val = temp; 522 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); 523 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); 524 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, 525 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); 526 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, 527 (sc->temp_throttle_trigger_cnt << 528 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); 529 return (err); 530 } 531 532 static void 533 tempmon_gofast(struct imx6_anatop_softc *sc) 534 { 535 536 if (sc->cpu_curmhz < sc->cpu_maxmhz) { 537 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); 538 } 539 } 540 541 static void 542 tempmon_goslow(struct imx6_anatop_softc *sc) 543 { 544 545 if (sc->cpu_curmhz > sc->cpu_minmhz) { 546 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); 547 } 548 } 549 550 static int 551 tempmon_intr(void *arg) 552 { 553 struct imx6_anatop_softc *sc = arg; 554 555 /* 556 * XXX Note that this code doesn't currently run (for some mysterious 557 * reason we just never get an interrupt), so the real monitoring is 558 * done by tempmon_throttle_check(). 559 */ 560 tempmon_goslow(sc); 561 /* XXX Schedule callout to speed back up eventually. */ 562 return (FILTER_HANDLED); 563 } 564 565 static void 566 tempmon_throttle_check(void *arg) 567 { 568 struct imx6_anatop_softc *sc = arg; 569 570 /* Lower counts are higher temperatures. */ 571 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) 572 tempmon_goslow(sc); 573 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) 574 tempmon_gofast(sc); 575 576 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 577 0, tempmon_throttle_check, sc, 0); 578 579 } 580 581 static void 582 initialize_tempmon(struct imx6_anatop_softc *sc) 583 { 584 uint32_t cal; 585 586 /* 587 * Fetch calibration data: a sensor count at room temperature (25C), 588 * a sensor count at a high temperature, and that temperature 589 */ 590 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); 591 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; 592 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; 593 sc->temp_high_val = (cal & 0x000000FF) * 10; 594 595 /* 596 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and 597 * reset back to max cpu freq at 5C below the trigger. 598 */ 599 sc->temp_throttle_val = sc->temp_high_val - 100; 600 sc->temp_throttle_trigger_cnt = 601 temp_to_count(sc, sc->temp_throttle_val); 602 sc->temp_throttle_reset_cnt = 603 temp_to_count(sc, sc->temp_throttle_val - 50); 604 605 /* 606 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set 607 * the throttle count, and begin making measurements. 608 */ 609 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); 610 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, 611 (sc->temp_throttle_trigger_cnt << 612 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | 613 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); 614 615 /* 616 * XXX Note that the alarm-interrupt feature isn't working yet, so 617 * we'll use a callout handler to check at 10Hz. Make sure we have an 618 * initial temperature reading before starting up the callouts so we 619 * don't get a bogus reading of zero. 620 */ 621 while (sc->temp_last_cnt == 0) 622 temp_update_count(sc); 623 sc->temp_throttle_delay = 100 * SBT_1MS; 624 callout_init(&sc->temp_throttle_callout, 0); 625 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 626 0, tempmon_throttle_check, sc, 0); 627 628 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 629 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0, 630 temp_sysctl_handler, "IK", "Current die temperature"); 631 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 632 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc, 633 0, temp_throttle_sysctl_handler, "IK", 634 "Throttle CPU when exceeding this temperature"); 635 } 636 637 static void 638 intr_setup(void *arg) 639 { 640 struct imx6_anatop_softc *sc; 641 642 sc = arg; 643 bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, 644 tempmon_intr, NULL, sc, &sc->temp_intrhand); 645 config_intrhook_disestablish(&sc->intr_setup_hook); 646 } 647 648 static void 649 imx6_anatop_new_pass(device_t dev) 650 { 651 struct imx6_anatop_softc *sc; 652 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; 653 654 /* 655 * We attach during BUS_PASS_BUS (because some day we will be a 656 * simplebus that has regulator devices as children), but some of our 657 * init work cannot be done until BUS_PASS_CPU (we rely on other devices 658 * that attach on the CPU pass). 659 */ 660 sc = device_get_softc(dev); 661 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { 662 sc->cpu_init_done = true; 663 cpufreq_initialize(sc); 664 initialize_tempmon(sc); 665 if (bootverbose) { 666 device_printf(sc->dev, "CPU %uMHz @ %umV\n", 667 sc->cpu_curmhz, sc->cpu_curmv); 668 } 669 } 670 bus_generic_new_pass(dev); 671 } 672 673 static int 674 imx6_anatop_detach(device_t dev) 675 { 676 677 /* This device can never detach. */ 678 return (EBUSY); 679 } 680 681 static int 682 imx6_anatop_attach(device_t dev) 683 { 684 struct imx6_anatop_softc *sc; 685 int err; 686 687 sc = device_get_softc(dev); 688 sc->dev = dev; 689 690 /* Allocate bus_space resources. */ 691 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { 692 device_printf(dev, "Cannot allocate resources\n"); 693 err = ENXIO; 694 goto out; 695 } 696 697 sc->intr_setup_hook.ich_func = intr_setup; 698 sc->intr_setup_hook.ich_arg = sc; 699 config_intrhook_establish(&sc->intr_setup_hook); 700 701 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), 702 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 703 OID_AUTO, "cpu_voltage", CTLFLAG_RD, 704 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); 705 706 imx6_anatop_sc = sc; 707 708 /* 709 * Other code seen on the net sets this SELFBIASOFF flag around the same 710 * time the temperature sensor is set up, although it's unclear how the 711 * two are related (if at all). 712 */ 713 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, 714 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); 715 716 /* 717 * Some day, when we're ready to deal with the actual anatop regulators 718 * that are described in fdt data as children of this "bus", this would 719 * be the place to invoke a simplebus helper routine to instantiate the 720 * children from the fdt data. 721 */ 722 723 err = 0; 724 725 out: 726 727 if (err != 0) { 728 bus_release_resources(dev, imx6_anatop_spec, sc->res); 729 } 730 731 return (err); 732 } 733 734 uint32_t 735 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 736 { 737 int reg; 738 739 /* 740 * Audio PLL (PLL4). 741 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) 742 */ 743 744 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); 745 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ 746 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 747 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 748 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); 749 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); 750 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); 751 752 return (0); 753 } 754 755 static int 756 imx6_anatop_probe(device_t dev) 757 { 758 759 if (!ofw_bus_status_okay(dev)) 760 return (ENXIO); 761 762 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) 763 return (ENXIO); 764 765 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); 766 767 return (BUS_PROBE_DEFAULT); 768 } 769 770 uint32_t 771 imx6_get_cpu_clock() 772 { 773 uint32_t corediv, plldiv; 774 775 corediv = imx_ccm_get_cacrr(); 776 plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 777 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 778 return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv)); 779 } 780 781 static device_method_t imx6_anatop_methods[] = { 782 /* Device interface */ 783 DEVMETHOD(device_probe, imx6_anatop_probe), 784 DEVMETHOD(device_attach, imx6_anatop_attach), 785 DEVMETHOD(device_detach, imx6_anatop_detach), 786 787 /* Bus interface */ 788 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), 789 790 DEVMETHOD_END 791 }; 792 793 static driver_t imx6_anatop_driver = { 794 "imx6_anatop", 795 imx6_anatop_methods, 796 sizeof(struct imx6_anatop_softc) 797 }; 798 799 static devclass_t imx6_anatop_devclass; 800 801 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 802 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 803 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 804 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 805 806