1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. 33 * Also, temperature montoring and cpu frequency control. It was Freescale who 34 * kitchen-sinked this device, not us. :) 35 * 36 * We don't really do anything with analog PLLs, but the registers for 37 * controlling them belong to the same block as the power regulator registers. 38 * Since the newbus hierarchy makes it hard for anyone other than us to get at 39 * them, we just export a couple public functions to allow the imx6 CCM clock 40 * driver to read and write those registers. 41 * 42 * We also don't do anything about power regulation yet, but when the need 43 * arises, this would be the place for that code to live. 44 * 45 * I have no idea where the "anatop" name comes from. It's in the standard DTS 46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes 47 * from Freescale, but it's not in the SoC manual. 48 * 49 * Note that temperature values throughout this code are handled in two types of 50 * units. Items with '_cnt' in the name use the hardware temperature count 51 * units (higher counts are lower temperatures). Items with '_val' in the name 52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl 53 * handlers (dK is the standard unit for temperature in sysctl). 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/callout.h> 59 #include <sys/kernel.h> 60 #include <sys/limits.h> 61 #include <sys/sysctl.h> 62 #include <sys/module.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include <machine/bus.h> 70 71 #include <arm/arm/mpcore_timervar.h> 72 #include <arm/freescale/fsl_ocotpreg.h> 73 #include <arm/freescale/fsl_ocotpvar.h> 74 #include <arm/freescale/imx/imx_ccmvar.h> 75 #include <arm/freescale/imx/imx_machdep.h> 76 #include <arm/freescale/imx/imx6_anatopreg.h> 77 #include <arm/freescale/imx/imx6_anatopvar.h> 78 79 static struct resource_spec imx6_anatop_spec[] = { 80 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 81 { -1, 0 } 82 }; 83 #define MEMRES 0 84 #define IRQRES 1 85 86 struct imx6_anatop_softc { 87 device_t dev; 88 struct resource *res[2]; 89 struct intr_config_hook 90 intr_setup_hook; 91 uint32_t cpu_curmhz; 92 uint32_t cpu_curmv; 93 uint32_t cpu_minmhz; 94 uint32_t cpu_minmv; 95 uint32_t cpu_maxmhz; 96 uint32_t cpu_maxmv; 97 uint32_t cpu_maxmhz_hw; 98 boolean_t cpu_overclock_enable; 99 boolean_t cpu_init_done; 100 uint32_t refosc_mhz; 101 void *temp_intrhand; 102 uint32_t temp_high_val; 103 uint32_t temp_high_cnt; 104 uint32_t temp_last_cnt; 105 uint32_t temp_room_cnt; 106 struct callout temp_throttle_callout; 107 sbintime_t temp_throttle_delay; 108 uint32_t temp_throttle_reset_cnt; 109 uint32_t temp_throttle_trigger_cnt; 110 uint32_t temp_throttle_val; 111 }; 112 113 static struct imx6_anatop_softc *imx6_anatop_sc; 114 115 /* 116 * Table of "operating points". 117 * These are combinations of frequency and voltage blessed by Freescale. 118 * While the datasheet says the ARM voltage can be as low as 925mV at 119 * 396MHz, it also says that the ARM and SOC voltages can't differ by 120 * more than 200mV, and the minimum SOC voltage is 1150mV, so that 121 * dictates the 950mV entry in this table. 122 */ 123 static struct oppt { 124 uint32_t mhz; 125 uint32_t mv; 126 } imx6_oppt_table[] = { 127 { 396, 950}, 128 { 792, 1150}, 129 { 852, 1225}, 130 { 996, 1225}, 131 {1200, 1275}, 132 }; 133 134 /* 135 * Table of CPU max frequencies. This is used to translate the max frequency 136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 137 * up in the operating points table. 138 */ 139 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; 140 141 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celcius offset. */ 142 143 uint32_t 144 imx6_anatop_read_4(bus_size_t offset) 145 { 146 147 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); 148 149 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); 150 } 151 152 void 153 imx6_anatop_write_4(bus_size_t offset, uint32_t value) 154 { 155 156 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); 157 158 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); 159 } 160 161 static void 162 vdd_set(struct imx6_anatop_softc *sc, int mv) 163 { 164 int newtarg, newtargSoc, oldtarg; 165 uint32_t delay, pmureg; 166 static boolean_t init_done = false; 167 168 /* 169 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM 170 * can't be more than 50mV above or 200mV below them. We keep them the 171 * same except in the case of the lowest operating point, which is 172 * handled as a special case below. 173 */ 174 175 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); 176 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; 177 178 /* Convert mV to target value. Clamp target to valid range. */ 179 if (mv < 725) 180 newtarg = 0x00; 181 else if (mv > 1450) 182 newtarg = 0x1F; 183 else 184 newtarg = (mv - 700) / 25; 185 186 /* 187 * The SOC voltage can't go below 1150mV, and thus because of the 200mV 188 * rule, the ARM voltage can't go below 950mV. The 950 is encoded in 189 * our oppt table, here we handle the SOC 1150 rule as a special case. 190 * (1150-700/25=18). 191 */ 192 newtargSoc = (newtarg < 18) ? 18 : newtarg; 193 194 /* 195 * The first time through the 3 voltages might not be equal so use a 196 * long conservative delay. After that we need to delay 3uS for every 197 * 25mV step upward; we actually delay 6uS because empirically, it works 198 * and the 3uS per step recommended by the docs doesn't (3uS fails when 199 * going from 400->1200, but works for smaller changes). 200 */ 201 if (init_done) { 202 if (newtarg == oldtarg) 203 return; 204 else if (newtarg > oldtarg) 205 delay = (newtarg - oldtarg) * 6; 206 else 207 delay = 0; 208 } else { 209 delay = (700 / 25) * 6; 210 init_done = true; 211 } 212 213 /* 214 * Make the change and wait for it to take effect. 215 */ 216 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | 217 IMX6_ANALOG_PMU_REG1_TARG_MASK | 218 IMX6_ANALOG_PMU_REG2_TARG_MASK); 219 220 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; 221 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; 222 pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; 223 224 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); 225 DELAY(delay); 226 sc->cpu_curmv = newtarg * 25 + 700; 227 } 228 229 static inline uint32_t 230 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv, 231 uint32_t plldiv) 232 { 233 234 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1)); 235 } 236 237 static inline void 238 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz, 239 uint32_t *corediv, uint32_t *plldiv) 240 { 241 242 *corediv = (cpu_mhz < 650) ? 1 : 0; 243 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2); 244 } 245 246 static inline uint32_t 247 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 248 { 249 uint32_t corediv, plldiv; 250 251 cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv); 252 return (cpufreq_mhz_from_div(sc, corediv, plldiv)); 253 } 254 255 static struct oppt * 256 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) 257 { 258 int d, diff, i, nearest; 259 260 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) 261 cpu_newmhz = sc->cpu_maxmhz_hw; 262 263 diff = INT_MAX; 264 nearest = 0; 265 for (i = 0; i < nitems(imx6_oppt_table); ++i) { 266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); 267 if (diff > d) { 268 diff = d; 269 nearest = i; 270 } 271 } 272 return (&imx6_oppt_table[nearest]); 273 } 274 275 static void 276 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) 277 { 278 uint32_t corediv, plldiv, timeout, wrk32; 279 280 /* If increasing the frequency, we must first increase the voltage. */ 281 if (op->mhz > sc->cpu_curmhz) { 282 vdd_set(sc, op->mv); 283 } 284 285 /* 286 * I can't find a documented procedure for changing the ARM PLL divisor, 287 * but some trial and error came up with this: 288 * - Set the bypass clock source to REF_CLK_24M (source #0). 289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. 290 * - Change the divisor. 291 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. 292 * - Turn off bypass mode; cpu should now be running at the new speed. 293 */ 294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); 295 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 296 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); 297 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, 298 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 299 300 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); 301 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 302 wrk32 |= plldiv; 303 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); 304 305 timeout = 10000; 306 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 307 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) 308 if (--timeout == 0) 309 panic("imx6_set_cpu_clock(): PLL never locked"); 310 311 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 312 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 313 imx_ccm_set_cacrr(corediv); 314 315 /* If lowering the frequency, it is now safe to lower the voltage. */ 316 if (op->mhz < sc->cpu_curmhz) 317 vdd_set(sc, op->mv); 318 sc->cpu_curmhz = op->mhz; 319 320 /* Tell the mpcore timer that its frequency has changed. */ 321 arm_tmr_change_frequency( 322 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); 323 } 324 325 static int 326 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) 327 { 328 struct imx6_anatop_softc *sc; 329 struct oppt * op; 330 uint32_t temp; 331 int err; 332 333 sc = arg1; 334 335 temp = sc->cpu_minmhz; 336 err = sysctl_handle_int(oidp, &temp, 0, req); 337 if (err != 0 || req->newptr == NULL) 338 return (err); 339 340 op = cpufreq_nearest_oppt(sc, temp); 341 if (op->mhz > sc->cpu_maxmhz) 342 return (ERANGE); 343 else if (op->mhz == sc->cpu_minmhz) 344 return (0); 345 346 /* 347 * Value changed, update softc. If the new min is higher than the 348 * current speed, raise the current speed to match. 349 */ 350 sc->cpu_minmhz = op->mhz; 351 if (sc->cpu_minmhz > sc->cpu_curmhz) { 352 cpufreq_set_clock(sc, op); 353 } 354 return (err); 355 } 356 357 static int 358 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) 359 { 360 struct imx6_anatop_softc *sc; 361 struct oppt * op; 362 uint32_t temp; 363 int err; 364 365 sc = arg1; 366 367 temp = sc->cpu_maxmhz; 368 err = sysctl_handle_int(oidp, &temp, 0, req); 369 if (err != 0 || req->newptr == NULL) 370 return (err); 371 372 op = cpufreq_nearest_oppt(sc, temp); 373 if (op->mhz < sc->cpu_minmhz) 374 return (ERANGE); 375 else if (op->mhz == sc->cpu_maxmhz) 376 return (0); 377 378 /* 379 * Value changed, update softc and hardware. The hardware update is 380 * unconditional. We always try to run at max speed, so any change of 381 * the max means we need to change the current speed too, regardless of 382 * whether it is higher or lower than the old max. 383 */ 384 sc->cpu_maxmhz = op->mhz; 385 cpufreq_set_clock(sc, op); 386 387 return (err); 388 } 389 390 static void 391 cpufreq_initialize(struct imx6_anatop_softc *sc) 392 { 393 uint32_t cfg3speed; 394 struct oppt * op; 395 396 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 397 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, 398 "CPU frequency"); 399 400 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 401 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 402 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); 403 404 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 405 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 406 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); 407 408 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 409 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, 410 "Maximum CPU frequency allowed by hardware"); 411 412 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 413 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, 414 &sc->cpu_overclock_enable, 0, 415 "Allow setting CPU frequency higher than cpu_maxmhz_hw"); 416 417 /* 418 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm 419 * (even though in the real world it will always be 24mhz). Oh wait a 420 * sec, I never wrote imx6_ccm. 421 */ 422 sc->refosc_mhz = 24; 423 424 /* 425 * Get the maximum speed this cpu can be set to. The values in the 426 * OCOTP CFG3 register are not documented in the reference manual. 427 * The following info was in an archived email found via web search: 428 * - 2b'11: 1200000000Hz; 429 * - 2b'10: 996000000Hz; 430 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 431 * - 2b'00: 792000000Hz; 432 * The default hardware max speed can be overridden by a tunable. 433 */ 434 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & 435 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; 436 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; 437 sc->cpu_maxmhz = sc->cpu_maxmhz_hw; 438 439 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); 440 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); 441 sc->cpu_minmhz = op->mhz; 442 sc->cpu_minmv = op->mv; 443 444 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); 445 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); 446 sc->cpu_maxmhz = op->mhz; 447 sc->cpu_maxmv = op->mv; 448 449 /* 450 * Set the CPU to maximum speed. 451 * 452 * We won't have thermal throttling until interrupts are enabled, but we 453 * want to run at full speed through all the device init stuff. This 454 * basically assumes that a single core can't overheat before interrupts 455 * are enabled; empirical testing shows that to be a safe assumption. 456 */ 457 cpufreq_set_clock(sc, op); 458 } 459 460 static inline uint32_t 461 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) 462 { 463 464 return (((sc->temp_high_val - (count - sc->temp_high_cnt) * 465 (sc->temp_high_val - 250) / 466 (sc->temp_room_cnt - sc->temp_high_cnt)))); 467 } 468 469 static inline uint32_t 470 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) 471 { 472 473 return ((sc->temp_room_cnt - sc->temp_high_cnt) * 474 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + 475 sc->temp_high_cnt); 476 } 477 478 static void 479 temp_update_count(struct imx6_anatop_softc *sc) 480 { 481 uint32_t val; 482 483 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); 484 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) 485 return; 486 sc->temp_last_cnt = 487 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> 488 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; 489 } 490 491 static int 492 temp_sysctl_handler(SYSCTL_HANDLER_ARGS) 493 { 494 struct imx6_anatop_softc *sc = arg1; 495 uint32_t t; 496 497 temp_update_count(sc); 498 499 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; 500 501 return (sysctl_handle_int(oidp, &t, 0, req)); 502 } 503 504 static int 505 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) 506 { 507 struct imx6_anatop_softc *sc = arg1; 508 int err; 509 uint32_t temp; 510 511 temp = sc->temp_throttle_val + TZ_ZEROC; 512 err = sysctl_handle_int(oidp, &temp, 0, req); 513 if (temp < TZ_ZEROC) 514 return (ERANGE); 515 temp -= TZ_ZEROC; 516 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) 517 return (err); 518 519 /* Value changed, update counts in softc and hardware. */ 520 sc->temp_throttle_val = temp; 521 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); 522 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); 523 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, 524 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); 525 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, 526 (sc->temp_throttle_trigger_cnt << 527 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); 528 return (err); 529 } 530 531 static void 532 tempmon_gofast(struct imx6_anatop_softc *sc) 533 { 534 535 if (sc->cpu_curmhz < sc->cpu_maxmhz) { 536 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); 537 } 538 } 539 540 static void 541 tempmon_goslow(struct imx6_anatop_softc *sc) 542 { 543 544 if (sc->cpu_curmhz > sc->cpu_minmhz) { 545 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); 546 } 547 } 548 549 static int 550 tempmon_intr(void *arg) 551 { 552 struct imx6_anatop_softc *sc = arg; 553 554 /* 555 * XXX Note that this code doesn't currently run (for some mysterious 556 * reason we just never get an interrupt), so the real monitoring is 557 * done by tempmon_throttle_check(). 558 */ 559 tempmon_goslow(sc); 560 /* XXX Schedule callout to speed back up eventually. */ 561 return (FILTER_HANDLED); 562 } 563 564 static void 565 tempmon_throttle_check(void *arg) 566 { 567 struct imx6_anatop_softc *sc = arg; 568 569 /* Lower counts are higher temperatures. */ 570 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) 571 tempmon_goslow(sc); 572 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) 573 tempmon_gofast(sc); 574 575 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 576 0, tempmon_throttle_check, sc, 0); 577 578 } 579 580 static void 581 initialize_tempmon(struct imx6_anatop_softc *sc) 582 { 583 uint32_t cal; 584 585 /* 586 * Fetch calibration data: a sensor count at room temperature (25C), 587 * a sensor count at a high temperature, and that temperature 588 */ 589 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); 590 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; 591 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; 592 sc->temp_high_val = (cal & 0x000000FF) * 10; 593 594 /* 595 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and 596 * reset back to max cpu freq at 5C below the trigger. 597 */ 598 sc->temp_throttle_val = sc->temp_high_val - 100; 599 sc->temp_throttle_trigger_cnt = 600 temp_to_count(sc, sc->temp_throttle_val); 601 sc->temp_throttle_reset_cnt = 602 temp_to_count(sc, sc->temp_throttle_val - 50); 603 604 /* 605 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set 606 * the throttle count, and begin making measurements. 607 */ 608 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); 609 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, 610 (sc->temp_throttle_trigger_cnt << 611 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | 612 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); 613 614 /* 615 * XXX Note that the alarm-interrupt feature isn't working yet, so 616 * we'll use a callout handler to check at 10Hz. Make sure we have an 617 * initial temperature reading before starting up the callouts so we 618 * don't get a bogus reading of zero. 619 */ 620 while (sc->temp_last_cnt == 0) 621 temp_update_count(sc); 622 sc->temp_throttle_delay = 100 * SBT_1MS; 623 callout_init(&sc->temp_throttle_callout, 0); 624 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 625 0, tempmon_throttle_check, sc, 0); 626 627 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 628 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0, 629 temp_sysctl_handler, "IK", "Current die temperature"); 630 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 631 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc, 632 0, temp_throttle_sysctl_handler, "IK", 633 "Throttle CPU when exceeding this temperature"); 634 } 635 636 static void 637 intr_setup(void *arg) 638 { 639 int rid; 640 struct imx6_anatop_softc *sc; 641 642 sc = arg; 643 rid = 0; 644 sc->res[IRQRES] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, 645 RF_ACTIVE); 646 if (sc->res[IRQRES] != NULL) { 647 bus_setup_intr(sc->dev, sc->res[IRQRES], 648 INTR_TYPE_MISC | INTR_MPSAFE, tempmon_intr, NULL, sc, 649 &sc->temp_intrhand); 650 } else { 651 device_printf(sc->dev, "Cannot allocate IRQ resource\n"); 652 } 653 config_intrhook_disestablish(&sc->intr_setup_hook); 654 } 655 656 static void 657 imx6_anatop_new_pass(device_t dev) 658 { 659 struct imx6_anatop_softc *sc; 660 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; 661 662 /* 663 * We attach during BUS_PASS_BUS (because some day we will be a 664 * simplebus that has regulator devices as children), but some of our 665 * init work cannot be done until BUS_PASS_CPU (we rely on other devices 666 * that attach on the CPU pass). 667 */ 668 sc = device_get_softc(dev); 669 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { 670 sc->cpu_init_done = true; 671 cpufreq_initialize(sc); 672 initialize_tempmon(sc); 673 if (bootverbose) { 674 device_printf(sc->dev, "CPU %uMHz @ %umV\n", 675 sc->cpu_curmhz, sc->cpu_curmv); 676 } 677 } 678 bus_generic_new_pass(dev); 679 } 680 681 static int 682 imx6_anatop_detach(device_t dev) 683 { 684 685 /* This device can never detach. */ 686 return (EBUSY); 687 } 688 689 static int 690 imx6_anatop_attach(device_t dev) 691 { 692 struct imx6_anatop_softc *sc; 693 int err; 694 695 sc = device_get_softc(dev); 696 sc->dev = dev; 697 698 /* Allocate bus_space resources. */ 699 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { 700 device_printf(dev, "Cannot allocate resources\n"); 701 err = ENXIO; 702 goto out; 703 } 704 705 sc->intr_setup_hook.ich_func = intr_setup; 706 sc->intr_setup_hook.ich_arg = sc; 707 config_intrhook_establish(&sc->intr_setup_hook); 708 709 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), 710 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 711 OID_AUTO, "cpu_voltage", CTLFLAG_RD, 712 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); 713 714 imx6_anatop_sc = sc; 715 716 /* 717 * Other code seen on the net sets this SELFBIASOFF flag around the same 718 * time the temperature sensor is set up, although it's unclear how the 719 * two are related (if at all). 720 */ 721 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, 722 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); 723 724 /* 725 * Some day, when we're ready to deal with the actual anatop regulators 726 * that are described in fdt data as children of this "bus", this would 727 * be the place to invoke a simplebus helper routine to instantiate the 728 * children from the fdt data. 729 */ 730 731 err = 0; 732 733 out: 734 735 if (err != 0) { 736 bus_release_resources(dev, imx6_anatop_spec, sc->res); 737 } 738 739 return (err); 740 } 741 742 uint32_t 743 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 744 { 745 int reg; 746 747 /* 748 * Audio PLL (PLL4). 749 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) 750 */ 751 752 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); 753 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ 754 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 755 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 756 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); 757 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); 758 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); 759 760 return (0); 761 } 762 763 static int 764 imx6_anatop_probe(device_t dev) 765 { 766 767 if (!ofw_bus_status_okay(dev)) 768 return (ENXIO); 769 770 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) 771 return (ENXIO); 772 773 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); 774 775 return (BUS_PROBE_DEFAULT); 776 } 777 778 uint32_t 779 imx6_get_cpu_clock() 780 { 781 uint32_t corediv, plldiv; 782 783 corediv = imx_ccm_get_cacrr(); 784 plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 785 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 786 return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv)); 787 } 788 789 static device_method_t imx6_anatop_methods[] = { 790 /* Device interface */ 791 DEVMETHOD(device_probe, imx6_anatop_probe), 792 DEVMETHOD(device_attach, imx6_anatop_attach), 793 DEVMETHOD(device_detach, imx6_anatop_detach), 794 795 /* Bus interface */ 796 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), 797 798 DEVMETHOD_END 799 }; 800 801 static driver_t imx6_anatop_driver = { 802 "imx6_anatop", 803 imx6_anatop_methods, 804 sizeof(struct imx6_anatop_softc) 805 }; 806 807 static devclass_t imx6_anatop_devclass; 808 809 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 810 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 811 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 812 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 813 814