1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2020 Dr Robert Harvey Crowston <crowston@protonmail.com> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 * $FreeBSD$ 20 * 21 */ 22 23 /* 24 * BCM2838-compatible PCI-express controller. 25 * 26 * Broadcom likes to give the same chip lots of different names. The name of 27 * this driver is taken from the Raspberry Pi 4 Broadcom 2838 chip. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/intr.h> 42 #include <sys/mutex.h> 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/pci/pci_host_generic.h> 49 #include <dev/pci/pci_host_generic_fdt.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcib_private.h> 53 54 #include <machine/bus.h> 55 #include <machine/intr.h> 56 57 #include "pcib_if.h" 58 #include "msi_if.h" 59 60 extern struct bus_space memmap_bus; 61 62 #define BUS_SPACE_3G_MAXADDR 0xc0000000 63 #define PCI_ID_VAL3 0x43c 64 #define CLASS_SHIFT 0x10 65 #define SUBCLASS_SHIFT 0x8 66 67 #define REG_CONTROLLER_HW_REV 0x406c 68 #define REG_BRIDGE_CTRL 0x9210 69 #define BRIDGE_DISABLE_FLAG 0x1 70 #define BRIDGE_RESET_FLAG 0x2 71 #define REG_BRIDGE_SERDES_MODE 0x4204 72 #define REG_BRIDGE_CONFIG 0x4008 73 #define REG_BRIDGE_MEM_WINDOW_LOW 0x4034 74 #define REG_BRIDGE_MEM_WINDOW_HIGH 0x4038 75 #define REG_BRIDGE_MEM_WINDOW_1 0x403c 76 #define REG_BRIDGE_GISB_WINDOW 0x402c 77 #define REG_BRIDGE_STATE 0x4068 78 #define REG_BRIDGE_LINK_STATE 0x00bc 79 #define REG_BRIDGE_BUS_WINDOW_LOW 0x400c 80 #define REG_BRIDGE_BUS_WINDOW_HIGH 0x4010 81 #define REG_BRIDGE_CPU_WINDOW_LOW 0x4070 82 #define REG_BRIDGE_CPU_WINDOW_START_HIGH 0x4080 83 #define REG_BRIDGE_CPU_WINDOW_END_HIGH 0x4084 84 85 #define REG_MSI_ADDR_LOW 0x4044 86 #define REG_MSI_ADDR_HIGH 0x4048 87 #define REG_MSI_CONFIG 0x404c 88 #define REG_MSI_CLR 0x4508 89 #define REG_MSI_MASK_CLR 0x4514 90 #define REG_MSI_RAISED 0x4500 91 #define REG_MSI_EOI 0x4060 92 #define NUM_MSI 32 93 94 #define REG_EP_CONFIG_CHOICE 0x9000 95 #define REG_EP_CONFIG_DATA 0x8000 96 97 /* 98 * These values were obtained from runtime inspection of a Linux system using a 99 * JTAG. The very limited documentation I have obtained from Broadcom does not 100 * explain how to compute them. 101 */ 102 #define REG_VALUE_4GB_WINDOW 0x11 103 #define REG_VALUE_4GB_CONFIG 0x88003000 104 #define REG_VALUE_MSI_CONFIG 0xffe06540 105 106 struct bcm_pcib_irqsrc { 107 struct intr_irqsrc isrc; 108 u_int irq; 109 bool allocated; 110 }; 111 112 struct bcm_pcib_softc { 113 struct generic_pcie_fdt_softc base; 114 device_t dev; 115 struct mtx config_mtx; 116 struct mtx msi_mtx; 117 struct resource *msi_irq_res; 118 void *msi_intr_cookie; 119 struct bcm_pcib_irqsrc *msi_isrcs; 120 pci_addr_t msi_addr; 121 }; 122 123 static struct ofw_compat_data compat_data[] = { 124 {"brcm,bcm2711-pcie", 1}, 125 {"brcm,bcm7211-pcie", 1}, 126 {"brcm,bcm7445-pcie", 1}, 127 128 {NULL, 0} 129 }; 130 131 static int 132 bcm_pcib_probe(device_t dev) 133 { 134 135 if (!ofw_bus_status_okay(dev)) 136 return (ENXIO); 137 138 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 139 return (ENXIO); 140 141 device_set_desc(dev, 142 "BCM2838-compatible PCI-express controller"); 143 return (BUS_PROBE_DEFAULT); 144 } 145 146 static void 147 bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val) 148 { 149 150 bus_space_write_4(sc->base.base.bst, sc->base.base.bsh, reg, 151 htole32(val)); 152 } 153 154 static uint32_t 155 bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg) 156 { 157 158 return (le32toh(bus_space_read_4(sc->base.base.bst, sc->base.base.bsh, 159 reg))); 160 } 161 162 static void 163 bcm_pcib_reset_controller(struct bcm_pcib_softc *sc) 164 { 165 uint32_t val; 166 167 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 168 val = val | BRIDGE_RESET_FLAG | BRIDGE_DISABLE_FLAG; 169 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 170 171 DELAY(100); 172 173 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 174 val = val & ~BRIDGE_RESET_FLAG; 175 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 176 177 DELAY(100); 178 179 bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0); 180 181 DELAY(100); 182 } 183 184 static void 185 bcm_pcib_enable_controller(struct bcm_pcib_softc *sc) 186 { 187 uint32_t val; 188 189 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 190 val = val & ~BRIDGE_DISABLE_FLAG; 191 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 192 193 DELAY(100); 194 } 195 196 static int 197 bcm_pcib_check_ranges(device_t dev) 198 { 199 struct bcm_pcib_softc *sc; 200 struct pcie_range *ranges; 201 int error = 0, i; 202 203 sc = device_get_softc(dev); 204 ranges = &sc->base.base.ranges[0]; 205 206 /* The first range needs to be non-zero. */ 207 if (ranges[0].size == 0) { 208 device_printf(dev, "error: first outbound memory range " 209 "(pci addr: 0x%jx, cpu addr: 0x%jx) has zero size.\n", 210 ranges[0].pci_base, ranges[0].phys_base); 211 error = ENXIO; 212 } 213 214 /* 215 * The controller can actually handle three distinct ranges, but we 216 * only implement support for one. 217 */ 218 for (i = 1; (bootverbose || error) && i < MAX_RANGES_TUPLES; ++i) { 219 if (ranges[i].size > 0) 220 device_printf(dev, 221 "note: outbound memory range %d (pci addr: 0x%jx, " 222 "cpu addr: 0x%jx, size: 0x%jx) will be ignored.\n", 223 i, ranges[i].pci_base, ranges[i].phys_base, 224 ranges[i].size); 225 } 226 227 return (error); 228 } 229 230 static const char * 231 bcm_pcib_link_state_string(uint32_t mode) 232 { 233 234 switch(mode & PCIEM_LINK_STA_SPEED) { 235 case 0: 236 return ("not up"); 237 case 1: 238 return ("2.5 GT/s"); 239 case 2: 240 return ("5.0 GT/s"); 241 case 4: 242 return ("8.0 GT/s"); 243 default: 244 return ("unknown"); 245 } 246 } 247 248 static bus_addr_t 249 bcm_get_offset_and_prepare_config(struct bcm_pcib_softc *sc, u_int bus, 250 u_int slot, u_int func, u_int reg) 251 { 252 /* 253 * Config for an end point is only available through a narrow window for 254 * one end point at a time. We first tell the controller which end point 255 * we want, then access it through the window. 256 */ 257 uint32_t func_index; 258 259 if (bus == 0 && slot == 0 && func == 0) 260 /* 261 * Special case for root device; its config is always available 262 * through the zero-offset. 263 */ 264 return (reg); 265 266 /* Tell the controller to show us the config in question. */ 267 func_index = PCIE_ADDR_OFFSET(bus, slot, func, 0); 268 bcm_pcib_set_reg(sc, REG_EP_CONFIG_CHOICE, func_index); 269 270 return (REG_EP_CONFIG_DATA + reg); 271 } 272 273 static bool 274 bcm_pcib_is_valid_quad(struct bcm_pcib_softc *sc, u_int bus, u_int slot, 275 u_int func, u_int reg) 276 { 277 278 if ((bus < sc->base.base.bus_start) || (bus > sc->base.base.bus_end)) 279 return (false); 280 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 281 return (false); 282 283 if (bus == 0 && slot == 0 && func == 0) 284 return (true); 285 if (bus == 0) 286 /* 287 * Probing other slots and funcs on bus 0 will lock up the 288 * memory controller. 289 */ 290 return (false); 291 292 return (true); 293 } 294 295 static uint32_t 296 bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 297 int bytes) 298 { 299 struct bcm_pcib_softc *sc; 300 bus_space_handle_t h; 301 bus_space_tag_t t; 302 bus_addr_t offset; 303 uint32_t data; 304 305 sc = device_get_softc(dev); 306 if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) 307 return (~0U); 308 309 mtx_lock(&sc->config_mtx); 310 offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); 311 312 t = sc->base.base.bst; 313 h = sc->base.base.bsh; 314 315 switch (bytes) { 316 case 1: 317 data = bus_space_read_1(t, h, offset); 318 break; 319 case 2: 320 data = le16toh(bus_space_read_2(t, h, offset)); 321 break; 322 case 4: 323 data = le32toh(bus_space_read_4(t, h, offset)); 324 break; 325 default: 326 data = ~0U; 327 break; 328 } 329 330 mtx_unlock(&sc->config_mtx); 331 return (data); 332 } 333 334 static void 335 bcm_pcib_write_config(device_t dev, u_int bus, u_int slot, 336 u_int func, u_int reg, uint32_t val, int bytes) 337 { 338 struct bcm_pcib_softc *sc; 339 bus_space_handle_t h; 340 bus_space_tag_t t; 341 uint32_t offset; 342 343 sc = device_get_softc(dev); 344 if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) 345 return; 346 347 mtx_lock(&sc->config_mtx); 348 offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); 349 350 t = sc->base.base.bst; 351 h = sc->base.base.bsh; 352 353 switch (bytes) { 354 case 1: 355 bus_space_write_1(t, h, offset, val); 356 break; 357 case 2: 358 bus_space_write_2(t, h, offset, htole16(val)); 359 break; 360 case 4: 361 bus_space_write_4(t, h, offset, htole32(val)); 362 break; 363 default: 364 break; 365 } 366 367 mtx_unlock(&sc->config_mtx); 368 } 369 370 static void 371 bcm_pcib_msi_intr_process(struct bcm_pcib_softc *sc, uint32_t interrupt_bitmap, 372 struct trapframe *tf) 373 { 374 struct bcm_pcib_irqsrc *irqsrc; 375 uint32_t bit, irq; 376 377 while ((bit = ffs(interrupt_bitmap))) { 378 irq = bit - 1; 379 380 /* Acknowledge interrupt. */ 381 bcm_pcib_set_reg(sc, REG_MSI_CLR, 1 << irq); 382 383 /* Send EOI. */ 384 bcm_pcib_set_reg(sc, REG_MSI_EOI, 1); 385 386 /* Despatch to handler. */ 387 irqsrc = &sc->msi_isrcs[irq]; 388 if (intr_isrc_dispatch(&irqsrc->isrc, tf)) 389 device_printf(sc->dev, 390 "note: unexpected interrupt (%d) triggered.\n", 391 irq); 392 393 /* Done with this interrupt. */ 394 interrupt_bitmap = interrupt_bitmap & ~(1 << irq); 395 } 396 } 397 398 static int 399 bcm_pcib_msi_intr(void *arg) 400 { 401 struct bcm_pcib_softc *sc; 402 struct trapframe *tf; 403 uint32_t interrupt_bitmap; 404 405 sc = (struct bcm_pcib_softc *) arg; 406 tf = curthread->td_intr_frame; 407 408 while ((interrupt_bitmap = bcm_pcib_read_reg(sc, REG_MSI_RAISED))) 409 bcm_pcib_msi_intr_process(sc, interrupt_bitmap, tf); 410 411 return (FILTER_HANDLED); 412 } 413 414 static int 415 bcm_pcib_alloc_msi(device_t dev, device_t child, int count, int maxcount, 416 device_t *pic, struct intr_irqsrc **srcs) 417 { 418 struct bcm_pcib_softc *sc; 419 int first_int, i; 420 421 sc = device_get_softc(dev); 422 mtx_lock(&sc->msi_mtx); 423 424 /* Find a continguous region of free message-signalled interrupts. */ 425 for (first_int = 0; first_int + count < NUM_MSI; ) { 426 for (i = first_int; i < first_int + count; ++i) { 427 if (sc->msi_isrcs[i].allocated) 428 goto next; 429 } 430 goto found; 431 next: 432 first_int = i + 1; 433 } 434 435 /* No appropriate region available. */ 436 mtx_unlock(&sc->msi_mtx); 437 device_printf(dev, "warning: failed to allocate %d MSI messages.\n", 438 count); 439 return (ENXIO); 440 441 found: 442 /* Mark the messages as in use. */ 443 for (i = 0; i < count; ++i) { 444 sc->msi_isrcs[i + first_int].allocated = true; 445 srcs[i] = &(sc->msi_isrcs[i + first_int].isrc); 446 } 447 448 mtx_unlock(&sc->msi_mtx); 449 *pic = device_get_parent(dev); 450 451 return (0); 452 } 453 454 static int 455 bcm_pcib_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 456 uint64_t *addr, uint32_t *data) 457 { 458 struct bcm_pcib_softc *sc; 459 struct bcm_pcib_irqsrc *msi_msg; 460 461 sc = device_get_softc(dev); 462 msi_msg = (struct bcm_pcib_irqsrc *) isrc; 463 464 *addr = sc->msi_addr; 465 *data = (REG_VALUE_MSI_CONFIG & 0xffff) | msi_msg->irq; 466 return (0); 467 } 468 469 static int 470 bcm_pcib_release_msi(device_t dev, device_t child, int count, 471 struct intr_irqsrc **isrc) 472 { 473 struct bcm_pcib_softc *sc; 474 struct bcm_pcib_irqsrc *msi_isrc; 475 int i; 476 477 sc = device_get_softc(dev); 478 mtx_lock(&sc->msi_mtx); 479 480 for (i = 0; i < count; i++) { 481 msi_isrc = (struct bcm_pcib_irqsrc *) isrc[i]; 482 msi_isrc->allocated = false; 483 } 484 485 mtx_unlock(&sc->msi_mtx); 486 return (0); 487 } 488 489 static int 490 bcm_pcib_msi_attach(device_t dev) 491 { 492 struct bcm_pcib_softc *sc; 493 phandle_t node, xref; 494 char const *bcm_name; 495 int i, rid; 496 497 sc = device_get_softc(dev); 498 sc->msi_addr = 0xffffffffc; 499 500 /* Clear any pending interrupts. */ 501 bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff); 502 503 rid = 1; 504 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 505 RF_ACTIVE); 506 if (sc->msi_irq_res == NULL) { 507 device_printf(dev, "could not allocate MSI irq resource.\n"); 508 return (ENXIO); 509 } 510 511 sc->msi_isrcs = malloc(sizeof(*sc->msi_isrcs) * NUM_MSI, M_DEVBUF, 512 M_WAITOK | M_ZERO); 513 514 int error = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | 515 INTR_MPSAFE, bcm_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 516 if (error) { 517 device_printf(dev, "error: failed to setup MSI handler.\n"); 518 return (ENXIO); 519 } 520 521 bcm_name = device_get_nameunit(dev); 522 for (i = 0; i < NUM_MSI; i++) { 523 sc->msi_isrcs[i].irq = i; 524 error = intr_isrc_register(&sc->msi_isrcs[i].isrc, dev, 0, 525 "%s,%u", bcm_name, i); 526 if (error) { 527 device_printf(dev, 528 "error: failed to register interrupt %d.\n", i); 529 return (ENXIO); 530 } 531 } 532 533 node = ofw_bus_get_node(dev); 534 xref = OF_xref_from_node(node); 535 OF_device_register_xref(xref, dev); 536 537 error = intr_msi_register(dev, xref); 538 if (error) 539 return (ENXIO); 540 541 mtx_init(&sc->msi_mtx, "bcm_pcib: msi_mtx", NULL, MTX_DEF); 542 543 bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff); 544 bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1); 545 bcm_pcib_set_reg(sc, REG_MSI_ADDR_HIGH, (sc->msi_addr >> 32)); 546 bcm_pcib_set_reg(sc, REG_MSI_CONFIG, REG_VALUE_MSI_CONFIG); 547 548 return (0); 549 } 550 551 static void 552 bcm_pcib_relocate_bridge_window(device_t dev) 553 { 554 /* 555 * In principle an out-of-bounds bridge window could be automatically 556 * adjusted at resource-activation time to lie within the bus address 557 * space by pcib_grow_window(), but that is not possible because the 558 * out-of-bounds resource allocation fails at allocation time. Instead, 559 * we will just fix up the window on the controller here, before it is 560 * re-discovered by pcib_probe_windows(). 561 */ 562 563 struct bcm_pcib_softc *sc; 564 pci_addr_t base, size, new_base, new_limit; 565 uint16_t val; 566 567 sc = device_get_softc(dev); 568 569 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMBASE_1, 2); 570 base = PCI_PPBMEMBASE(0, val); 571 572 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, 2); 573 size = PCI_PPBMEMLIMIT(0, val) - base; 574 575 new_base = sc->base.base.ranges[0].pci_base; 576 val = (uint16_t) (new_base >> 16); 577 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMBASE_1, val, 2); 578 579 new_limit = new_base + size; 580 val = (uint16_t) (new_limit >> 16); 581 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, val, 2); 582 } 583 584 static uint32_t 585 encode_cpu_window_low(pci_addr_t phys_base, bus_size_t size) 586 { 587 588 return (((phys_base >> 0x10) & 0xfff0) | 589 ((phys_base + size - 1) & 0xfff00000)); 590 } 591 592 static uint32_t 593 encode_cpu_window_start_high(pci_addr_t phys_base) 594 { 595 596 return ((phys_base >> 0x20) & 0xff); 597 } 598 599 static uint32_t 600 encode_cpu_window_end_high(pci_addr_t phys_base, bus_size_t size) 601 { 602 603 return (((phys_base + size - 1) >> 0x20) & 0xff); 604 } 605 606 static int 607 bcm_pcib_attach(device_t dev) 608 { 609 struct bcm_pcib_softc *sc; 610 pci_addr_t phys_base, pci_base; 611 bus_size_t size; 612 uint32_t hardware_rev, bridge_state, link_state; 613 int error, tries; 614 615 sc = device_get_softc(dev); 616 sc->dev = dev; 617 618 error = pci_host_generic_setup_fdt(dev); 619 if (error) 620 return (error); 621 622 error = bcm_pcib_check_ranges(dev); 623 if (error) 624 return (error); 625 626 mtx_init(&sc->config_mtx, "bcm_pcib: config_mtx", NULL, MTX_DEF); 627 628 bcm_pcib_reset_controller(sc); 629 630 hardware_rev = bcm_pcib_read_reg(sc, REG_CONTROLLER_HW_REV) & 0xffff; 631 device_printf(dev, "hardware identifies as revision 0x%x.\n", 632 hardware_rev); 633 634 /* 635 * Set PCI->CPU memory window. This encodes the inbound window showing 636 * up to 4 GiB of system memory to the controller, with zero offset. 637 * Thus, from the perspective of a device on the PCI-E bus, there is a 638 * 1:1 map from PCI-E bus addresses to system memory addresses. However, 639 * a hardware limitation means that the controller can only perform DMA 640 * on the lower 3 GiB of system memory. 641 */ 642 bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_LOW, REG_VALUE_4GB_WINDOW); 643 bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_HIGH, 0); 644 bcm_pcib_set_reg(sc, REG_BRIDGE_CONFIG, REG_VALUE_4GB_CONFIG); 645 bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0); 646 bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_1, 0); 647 648 bcm_pcib_enable_controller(sc); 649 650 /* Wait for controller to start. */ 651 for(tries = 0; ; ++tries) { 652 bridge_state = bcm_pcib_read_reg(sc, REG_BRIDGE_STATE); 653 654 if ((bridge_state & 0x30) == 0x30) 655 /* Controller ready. */ 656 break; 657 658 if (tries > 100) { 659 device_printf(dev, 660 "error: controller failed to start.\n"); 661 return (ENXIO); 662 } 663 664 DELAY(1000); 665 } 666 667 link_state = bcm_pcib_read_reg(sc, REG_BRIDGE_LINK_STATE) >> 0x10; 668 if (!link_state) { 669 device_printf(dev, "error: controller started but link is not " 670 "up.\n"); 671 return (ENXIO); 672 } 673 if (bootverbose) 674 device_printf(dev, "note: reported link speed is %s.\n", 675 bcm_pcib_link_state_string(link_state)); 676 677 /* 678 * Set the CPU->PCI memory window. The map in this direction is not 1:1. 679 * Addresses seen by the CPU need to be adjusted to make sense to the 680 * controller as they pass through the window. 681 */ 682 pci_base = sc->base.base.ranges[0].pci_base; 683 phys_base = sc->base.base.ranges[0].phys_base; 684 size = sc->base.base.ranges[0].size; 685 686 bcm_pcib_set_reg(sc, REG_BRIDGE_BUS_WINDOW_LOW, pci_base & 0xffffffff); 687 bcm_pcib_set_reg(sc, REG_BRIDGE_BUS_WINDOW_HIGH, pci_base >> 32); 688 689 bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_LOW, 690 encode_cpu_window_low(phys_base, size)); 691 bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_START_HIGH, 692 encode_cpu_window_start_high(phys_base)); 693 bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_END_HIGH, 694 encode_cpu_window_end_high(phys_base, size)); 695 696 /* 697 * The controller starts up declaring itself an endpoint; readvertise it 698 * as a bridge. 699 */ 700 bcm_pcib_set_reg(sc, PCI_ID_VAL3, 701 PCIC_BRIDGE << CLASS_SHIFT | PCIS_BRIDGE_PCI << SUBCLASS_SHIFT); 702 703 bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0x2); 704 DELAY(100); 705 706 bcm_pcib_relocate_bridge_window(dev); 707 708 /* Configure interrupts. */ 709 error = bcm_pcib_msi_attach(dev); 710 if (error) 711 return (error); 712 713 /* Done. */ 714 device_add_child(dev, "pci", -1); 715 return (bus_generic_attach(dev)); 716 } 717 718 /* 719 * Device method table. 720 */ 721 static device_method_t bcm_pcib_methods[] = { 722 /* Device interface. */ 723 DEVMETHOD(device_probe, bcm_pcib_probe), 724 DEVMETHOD(device_attach, bcm_pcib_attach), 725 726 /* PCIB interface. */ 727 DEVMETHOD(pcib_read_config, bcm_pcib_read_config), 728 DEVMETHOD(pcib_write_config, bcm_pcib_write_config), 729 730 /* MSI interface. */ 731 DEVMETHOD(msi_alloc_msi, bcm_pcib_alloc_msi), 732 DEVMETHOD(msi_release_msi, bcm_pcib_release_msi), 733 DEVMETHOD(msi_map_msi, bcm_pcib_map_msi), 734 735 DEVMETHOD_END 736 }; 737 738 DEFINE_CLASS_1(pcib, bcm_pcib_driver, bcm_pcib_methods, 739 sizeof(struct bcm_pcib_softc), generic_pcie_fdt_driver); 740 741 static devclass_t bcm_pcib_devclass; 742 DRIVER_MODULE(bcm_pcib, simplebus, bcm_pcib_driver, bcm_pcib_devclass, 0, 0); 743 744