xref: /freebsd/sys/arm/broadcom/bcm2835/bcm2838_pci.c (revision 9f23cbd6cae82fd77edfad7173432fa8dccd0a95)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2020 Dr Robert Harvey Crowston <crowston@protonmail.com>
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  *
18  *
19  * $FreeBSD$
20  *
21  */
22 
23 /*
24  * BCM2838-compatible PCI-express controller.
25  *
26  * Broadcom likes to give the same chip lots of different names. The name of
27  * this driver is taken from the Raspberry Pi 4 Broadcom 2838 chip.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/proc.h>
40 #include <sys/rman.h>
41 #include <sys/intr.h>
42 #include <sys/mutex.h>
43 
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47 
48 #include <dev/pci/pci_host_generic.h>
49 #include <dev/pci/pci_host_generic_fdt.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcib_private.h>
53 
54 #include <machine/bus.h>
55 #include <machine/intr.h>
56 
57 #include "pcib_if.h"
58 #include "msi_if.h"
59 
60 #define PCI_ID_VAL3		0x43c
61 #define CLASS_SHIFT		0x10
62 #define SUBCLASS_SHIFT		0x8
63 
64 #define REG_CONTROLLER_HW_REV			0x406c
65 #define REG_BRIDGE_CTRL				0x9210
66 #define BRIDGE_DISABLE_FLAG	0x1
67 #define BRIDGE_RESET_FLAG	0x2
68 #define REG_BRIDGE_SERDES_MODE			0x4204
69 #define REG_DMA_CONFIG				0x4008
70 #define REG_DMA_WINDOW_LOW			0x4034
71 #define REG_DMA_WINDOW_HIGH			0x4038
72 #define REG_DMA_WINDOW_1			0x403c
73 #define REG_BRIDGE_GISB_WINDOW			0x402c
74 #define REG_BRIDGE_STATE			0x4068
75 #define REG_BRIDGE_LINK_STATE			0x00bc
76 #define REG_BUS_WINDOW_LOW			0x400c
77 #define REG_BUS_WINDOW_HIGH			0x4010
78 #define REG_CPU_WINDOW_LOW			0x4070
79 #define REG_CPU_WINDOW_START_HIGH		0x4080
80 #define REG_CPU_WINDOW_END_HIGH			0x4084
81 
82 #define REG_MSI_ADDR_LOW			0x4044
83 #define REG_MSI_ADDR_HIGH			0x4048
84 #define REG_MSI_CONFIG				0x404c
85 #define REG_MSI_CLR				0x4508
86 #define REG_MSI_MASK_CLR			0x4514
87 #define REG_MSI_RAISED				0x4500
88 #define REG_MSI_EOI				0x4060
89 #define NUM_MSI			32
90 
91 #define REG_EP_CONFIG_CHOICE			0x9000
92 #define REG_EP_CONFIG_DATA			0x8000
93 
94 /*
95  * The system memory controller can address up to 16 GiB of physical memory
96  * (although at time of writing the largest memory size available for purchase
97  * is 8 GiB). However, the system DMA controller is capable of accessing only a
98  * limited portion of the address space. Worse, the PCI-e controller has further
99  * constraints for DMA, and those limitations are not wholly clear to the
100  * author. NetBSD and Linux allow DMA on the lower 3 GiB of the physical memory,
101  * but experimentation shows DMA performed above 960 MiB results in data
102  * corruption with this driver. The limit of 960 MiB is taken from OpenBSD, but
103  * apparently that value was chosen for satisfying a constraint of an unrelated
104  * peripheral.
105  *
106  * Whatever the true maximum address, 960 MiB works.
107  */
108 #define DMA_HIGH_LIMIT			0x3c000000
109 #define MAX_MEMORY_LOG2			0x21
110 #define REG_VALUE_DMA_WINDOW_LOW	(MAX_MEMORY_LOG2 - 0xf)
111 #define REG_VALUE_DMA_WINDOW_HIGH	0x0
112 #define DMA_WINDOW_ENABLE		0x3000
113 #define REG_VALUE_DMA_WINDOW_CONFIG	\
114     (((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE)
115 
116 #define REG_VALUE_MSI_CONFIG	0xffe06540
117 
118 struct bcm_pcib_irqsrc {
119 	struct intr_irqsrc	isrc;
120 	u_int			irq;
121 	bool			allocated;
122 };
123 
124 struct bcm_pcib_softc {
125 	struct generic_pcie_fdt_softc	base;
126 	device_t			dev;
127 	bus_dma_tag_t			dmat;
128 	struct mtx			config_mtx;
129 	struct mtx			msi_mtx;
130 	struct resource 		*msi_irq_res;
131 	void				*msi_intr_cookie;
132 	struct bcm_pcib_irqsrc		*msi_isrcs;
133 	pci_addr_t			msi_addr;
134 };
135 
136 static struct ofw_compat_data compat_data[] = {
137 	{"brcm,bcm2711-pcie",			1},
138 	{"brcm,bcm7211-pcie",			1},
139 	{"brcm,bcm7445-pcie",			1},
140 	{NULL,					0}
141 };
142 
143 static int
144 bcm_pcib_probe(device_t dev)
145 {
146 
147 	if (!ofw_bus_status_okay(dev))
148 		return (ENXIO);
149 
150 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
151 		return (ENXIO);
152 
153 	device_set_desc(dev,
154 	    "BCM2838-compatible PCI-express controller");
155 	return (BUS_PROBE_DEFAULT);
156 }
157 
158 static bus_dma_tag_t
159 bcm_pcib_get_dma_tag(device_t dev, device_t child)
160 {
161 	struct bcm_pcib_softc *sc;
162 
163 	sc = device_get_softc(dev);
164 	return (sc->dmat);
165 }
166 
167 static void
168 bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val)
169 {
170 
171 	bus_write_4(sc->base.base.res, reg, htole32(val));
172 }
173 
174 static uint32_t
175 bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg)
176 {
177 
178 	return (le32toh(bus_read_4(sc->base.base.res, reg)));
179 }
180 
181 static void
182 bcm_pcib_reset_controller(struct bcm_pcib_softc *sc)
183 {
184 	uint32_t val;
185 
186 	val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL);
187 	val = val | BRIDGE_RESET_FLAG | BRIDGE_DISABLE_FLAG;
188 	bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val);
189 
190 	DELAY(100);
191 
192 	val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL);
193 	val = val & ~BRIDGE_RESET_FLAG;
194 	bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val);
195 
196 	DELAY(100);
197 
198 	bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0);
199 
200 	DELAY(100);
201 }
202 
203 static void
204 bcm_pcib_enable_controller(struct bcm_pcib_softc *sc)
205 {
206 	uint32_t val;
207 
208 	val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL);
209 	val = val & ~BRIDGE_DISABLE_FLAG;
210 	bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val);
211 
212 	DELAY(100);
213 }
214 
215 static int
216 bcm_pcib_check_ranges(device_t dev)
217 {
218 	struct bcm_pcib_softc *sc;
219 	struct pcie_range *ranges;
220 	int error = 0, i;
221 
222 	sc = device_get_softc(dev);
223 	ranges = &sc->base.base.ranges[0];
224 
225 	/* The first range needs to be non-zero. */
226 	if (ranges[0].size == 0) {
227 		device_printf(dev, "error: first outbound memory range "
228 		    "(pci addr: 0x%jx, cpu addr: 0x%jx) has zero size.\n",
229 		    ranges[0].pci_base, ranges[0].phys_base);
230 		error = ENXIO;
231 	}
232 
233 	/*
234 	 * The controller can actually handle three distinct ranges, but we
235 	 * only implement support for one.
236 	 */
237 	for (i = 1; (bootverbose || error) && i < MAX_RANGES_TUPLES; ++i) {
238 		if (ranges[i].size > 0)
239 			device_printf(dev,
240 			    "note: outbound memory range %d (pci addr: 0x%jx, "
241 			    "cpu addr: 0x%jx, size: 0x%jx) will be ignored.\n",
242 			    i, ranges[i].pci_base, ranges[i].phys_base,
243 			    ranges[i].size);
244 	}
245 
246 	return (error);
247 }
248 
249 static const char *
250 bcm_pcib_link_state_string(uint32_t mode)
251 {
252 
253 	switch(mode & PCIEM_LINK_STA_SPEED) {
254 	case 0:
255 		return ("not up");
256 	case 1:
257 		return ("2.5 GT/s");
258 	case 2:
259 		return ("5.0 GT/s");
260 	case 4:
261 		return ("8.0 GT/s");
262 	default:
263 		return ("unknown");
264 	}
265 }
266 
267 static bus_addr_t
268 bcm_get_offset_and_prepare_config(struct bcm_pcib_softc *sc, u_int bus,
269     u_int slot, u_int func, u_int reg)
270 {
271 	/*
272 	 * Config for an end point is only available through a narrow window for
273 	 * one end point at a time. We first tell the controller which end point
274 	 * we want, then access it through the window.
275 	 */
276 	uint32_t func_index;
277 
278 	if (bus == 0 && slot == 0 && func == 0)
279 		/*
280 		 * Special case for root device; its config is always available
281 		 * through the zero-offset.
282 		 */
283 		return (reg);
284 
285 	/* Tell the controller to show us the config in question. */
286 	func_index = PCIE_ADDR_OFFSET(bus, slot, func, 0);
287 	bcm_pcib_set_reg(sc, REG_EP_CONFIG_CHOICE, func_index);
288 
289 	return (REG_EP_CONFIG_DATA + reg);
290 }
291 
292 static bool
293 bcm_pcib_is_valid_quad(struct bcm_pcib_softc *sc, u_int bus, u_int slot,
294     u_int func, u_int reg)
295 {
296 
297 	if ((bus < sc->base.base.bus_start) || (bus > sc->base.base.bus_end))
298 		return (false);
299 	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
300 		return (false);
301 
302 	if (bus == 0 && slot == 0 && func == 0)
303 		return (true);
304 	if (bus == 0)
305 		/*
306 		 * Probing other slots and funcs on bus 0 will lock up the
307 		 * memory controller.
308 		 */
309 		return (false);
310 
311 	return (true);
312 }
313 
314 static uint32_t
315 bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
316     int bytes)
317 {
318 	struct bcm_pcib_softc *sc;
319 	bus_addr_t offset;
320 	uint32_t data;
321 
322 	sc = device_get_softc(dev);
323 	if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg))
324 		return (~0U);
325 
326 	mtx_lock(&sc->config_mtx);
327 	offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);
328 
329 	switch (bytes) {
330 	case 1:
331 		data = bus_read_1(sc->base.base.res, offset);
332 		break;
333 	case 2:
334 		data = le16toh(bus_read_2(sc->base.base.res, offset));
335 		break;
336 	case 4:
337 		data = le32toh(bus_read_4(sc->base.base.res, offset));
338 		break;
339 	default:
340 		data = ~0U;
341 		break;
342 	}
343 
344 	mtx_unlock(&sc->config_mtx);
345 	return (data);
346 }
347 
348 static void
349 bcm_pcib_write_config(device_t dev, u_int bus, u_int slot,
350     u_int func, u_int reg, uint32_t val, int bytes)
351 {
352 	struct bcm_pcib_softc *sc;
353 	uint32_t offset;
354 
355 	sc = device_get_softc(dev);
356 	if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg))
357 		return;
358 
359 	mtx_lock(&sc->config_mtx);
360 	offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);
361 
362 	switch (bytes) {
363 	case 1:
364 		bus_write_1(sc->base.base.res, offset, val);
365 		break;
366 	case 2:
367 		bus_write_2(sc->base.base.res, offset, htole16(val));
368 		break;
369 	case 4:
370 		bus_write_4(sc->base.base.res, offset, htole32(val));
371 		break;
372 	default:
373 		break;
374 	}
375 
376 	mtx_unlock(&sc->config_mtx);
377 }
378 
379 static void
380 bcm_pcib_msi_intr_process(struct bcm_pcib_softc *sc, uint32_t interrupt_bitmap,
381     struct trapframe *tf)
382 {
383 	struct bcm_pcib_irqsrc *irqsrc;
384 	uint32_t bit, irq;
385 
386 	while ((bit = ffs(interrupt_bitmap))) {
387 		irq = bit - 1;
388 
389 		/* Acknowledge interrupt. */
390 		bcm_pcib_set_reg(sc, REG_MSI_CLR, 1 << irq);
391 
392 		/* Send EOI. */
393 		bcm_pcib_set_reg(sc, REG_MSI_EOI, 1);
394 
395 		/* Despatch to handler. */
396 		irqsrc = &sc->msi_isrcs[irq];
397 		if (intr_isrc_dispatch(&irqsrc->isrc, tf))
398 			device_printf(sc->dev,
399 			    "note: unexpected interrupt (%d) triggered.\n",
400 			    irq);
401 
402 		/* Done with this interrupt. */
403 		interrupt_bitmap = interrupt_bitmap & ~(1 << irq);
404 	}
405 }
406 
407 static int
408 bcm_pcib_msi_intr(void *arg)
409 {
410 	struct bcm_pcib_softc *sc;
411 	struct trapframe *tf;
412 	uint32_t interrupt_bitmap;
413 
414 	sc = (struct bcm_pcib_softc *) arg;
415 	tf = curthread->td_intr_frame;
416 
417 	while ((interrupt_bitmap = bcm_pcib_read_reg(sc, REG_MSI_RAISED)))
418 		bcm_pcib_msi_intr_process(sc, interrupt_bitmap, tf);
419 
420 	return (FILTER_HANDLED);
421 }
422 
423 static int
424 bcm_pcib_alloc_msi(device_t dev, device_t child, int count, int maxcount,
425     device_t *pic, struct intr_irqsrc **srcs)
426 {
427 	struct bcm_pcib_softc *sc;
428 	int first_int, i;
429 
430 	sc = device_get_softc(dev);
431 	mtx_lock(&sc->msi_mtx);
432 
433 	/* Find a continguous region of free message-signalled interrupts. */
434 	for (first_int = 0; first_int + count < NUM_MSI; ) {
435 		for (i = first_int; i < first_int + count; ++i) {
436 			if (sc->msi_isrcs[i].allocated)
437 				goto next;
438 		}
439 		goto found;
440 next:
441 		first_int = i + 1;
442 	}
443 
444 	/* No appropriate region available. */
445 	mtx_unlock(&sc->msi_mtx);
446 	device_printf(dev, "warning: failed to allocate %d MSI messages.\n",
447 	    count);
448 	return (ENXIO);
449 
450 found:
451 	/* Mark the messages as in use. */
452 	for (i = 0; i < count; ++i) {
453 		sc->msi_isrcs[i + first_int].allocated = true;
454 		srcs[i] = &(sc->msi_isrcs[i + first_int].isrc);
455 	}
456 
457 	mtx_unlock(&sc->msi_mtx);
458 	*pic = device_get_parent(dev);
459 
460 	return (0);
461 }
462 
463 static int
464 bcm_pcib_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
465     uint64_t *addr, uint32_t *data)
466 {
467 	struct bcm_pcib_softc *sc;
468 	struct bcm_pcib_irqsrc *msi_msg;
469 
470 	sc = device_get_softc(dev);
471 	msi_msg = (struct bcm_pcib_irqsrc *) isrc;
472 
473 	*addr = sc->msi_addr;
474 	*data = (REG_VALUE_MSI_CONFIG & 0xffff) | msi_msg->irq;
475 	return (0);
476 }
477 
478 static int
479 bcm_pcib_release_msi(device_t dev, device_t child, int count,
480     struct intr_irqsrc **isrc)
481 {
482 	struct bcm_pcib_softc *sc;
483 	struct bcm_pcib_irqsrc *msi_isrc;
484 	int i;
485 
486 	sc = device_get_softc(dev);
487 	mtx_lock(&sc->msi_mtx);
488 
489 	for (i = 0; i < count; i++) {
490 		msi_isrc = (struct bcm_pcib_irqsrc *) isrc[i];
491 		msi_isrc->allocated = false;
492 	}
493 
494 	mtx_unlock(&sc->msi_mtx);
495 	return (0);
496 }
497 
498 static int
499 bcm_pcib_msi_attach(device_t dev)
500 {
501 	struct bcm_pcib_softc *sc;
502 	phandle_t node, xref;
503 	char const *bcm_name;
504 	int error, i, rid;
505 
506 	sc = device_get_softc(dev);
507 	sc->msi_addr = 0xffffffffc;
508 
509 	/* Clear any pending interrupts. */
510 	bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff);
511 
512 	rid = 1;
513 	sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
514 	    RF_ACTIVE);
515 	if (sc->msi_irq_res == NULL) {
516 		device_printf(dev, "could not allocate MSI irq resource.\n");
517 		return (ENXIO);
518 	}
519 
520 	sc->msi_isrcs = malloc(sizeof(*sc->msi_isrcs) * NUM_MSI, M_DEVBUF,
521 	    M_WAITOK | M_ZERO);
522 
523 	error = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO |
524 	    INTR_MPSAFE, bcm_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie);
525 	if (error != 0) {
526 		device_printf(dev, "error: failed to setup MSI handler.\n");
527 		return (error);
528 	}
529 
530 	bcm_name = device_get_nameunit(dev);
531 	for (i = 0; i < NUM_MSI; i++) {
532 		sc->msi_isrcs[i].irq = i;
533 		error = intr_isrc_register(&sc->msi_isrcs[i].isrc, dev, 0,
534 		    "%s,%u", bcm_name, i);
535 		if (error != 0) {
536 			device_printf(dev,
537 			    "error: failed to register interrupt %d.\n", i);
538 			return (error);
539 		}
540 	}
541 
542 	node = ofw_bus_get_node(dev);
543 	xref = OF_xref_from_node(node);
544 	OF_device_register_xref(xref, dev);
545 
546 	error = intr_msi_register(dev, xref);
547 	if (error != 0)
548 		return (error);
549 
550 	mtx_init(&sc->msi_mtx, "bcm_pcib: msi_mtx", NULL, MTX_DEF);
551 
552 	bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff);
553 	bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1);
554 	bcm_pcib_set_reg(sc, REG_MSI_ADDR_HIGH, (sc->msi_addr >> 32));
555 	bcm_pcib_set_reg(sc, REG_MSI_CONFIG, REG_VALUE_MSI_CONFIG);
556 
557 	return (0);
558 }
559 
560 static void
561 bcm_pcib_relocate_bridge_window(device_t dev)
562 {
563 	/*
564 	 * In principle an out-of-bounds bridge window could be automatically
565 	 * adjusted at resource-activation time to lie within the bus address
566 	 * space by pcib_grow_window(), but that is not possible because the
567 	 * out-of-bounds resource allocation fails at allocation time. Instead,
568 	 * we will just fix up the window on the controller here, before it is
569 	 * re-discovered by pcib_probe_windows().
570 	 */
571 
572 	struct bcm_pcib_softc *sc;
573 	pci_addr_t base, size, new_base, new_limit;
574 	uint16_t val;
575 
576 	sc = device_get_softc(dev);
577 
578 	val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMBASE_1, 2);
579 	base = PCI_PPBMEMBASE(0, val);
580 
581 	val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, 2);
582 	size = PCI_PPBMEMLIMIT(0, val) - base;
583 
584 	new_base = sc->base.base.ranges[0].pci_base;
585 	val = (uint16_t) (new_base >> 16);
586 	bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMBASE_1, val, 2);
587 
588 	new_limit = new_base + size;
589 	val = (uint16_t) (new_limit >> 16);
590 	bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, val, 2);
591 }
592 
593 static uint32_t
594 encode_cpu_window_low(pci_addr_t phys_base, bus_size_t size)
595 {
596 
597 	return (((phys_base >> 0x10) & 0xfff0) |
598 	    ((phys_base + size - 1) & 0xfff00000));
599 }
600 
601 static uint32_t
602 encode_cpu_window_start_high(pci_addr_t phys_base)
603 {
604 
605 	return ((phys_base >> 0x20) & 0xff);
606 }
607 
608 static uint32_t
609 encode_cpu_window_end_high(pci_addr_t phys_base, bus_size_t size)
610 {
611 
612 	return (((phys_base + size - 1) >> 0x20) & 0xff);
613 }
614 
615 static int
616 bcm_pcib_attach(device_t dev)
617 {
618 	struct bcm_pcib_softc *sc;
619 	pci_addr_t phys_base, pci_base;
620 	bus_size_t size;
621 	uint32_t hardware_rev, bridge_state, link_state;
622 	int error, tries;
623 
624 	sc = device_get_softc(dev);
625 	sc->dev = dev;
626 
627 	/*
628 	 * This tag will be used in preference to the one created in
629 	 * pci_host_generic.c.
630 	 */
631 	error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
632 	    1, 0,				/* alignment, bounds */
633 	    DMA_HIGH_LIMIT,			/* lowaddr */
634 	    BUS_SPACE_MAXADDR,			/* highaddr */
635 	    NULL, NULL,				/* filter, filterarg */
636 	    DMA_HIGH_LIMIT,			/* maxsize */
637 	    BUS_SPACE_UNRESTRICTED,		/* nsegments */
638 	    DMA_HIGH_LIMIT,			/* maxsegsize */
639 	    0, 					/* flags */
640 	    NULL, NULL,				/* lockfunc, lockarg */
641 	    &sc->dmat);
642 	if (error != 0)
643 		return (error);
644 
645 	error = pci_host_generic_setup_fdt(dev);
646 	if (error != 0)
647 		return (error);
648 
649 	error = bcm_pcib_check_ranges(dev);
650 	if (error != 0)
651 		return (error);
652 
653 	mtx_init(&sc->config_mtx, "bcm_pcib: config_mtx", NULL, MTX_DEF);
654 
655 	bcm_pcib_reset_controller(sc);
656 
657 	hardware_rev = bcm_pcib_read_reg(sc, REG_CONTROLLER_HW_REV) & 0xffff;
658 	device_printf(dev, "hardware identifies as revision 0x%x.\n",
659 	    hardware_rev);
660 
661 	/*
662 	 * Set PCI->CPU memory window. This encodes the inbound window showing
663 	 * the system memory to the controller.
664 	 */
665 	bcm_pcib_set_reg(sc, REG_DMA_WINDOW_LOW, REG_VALUE_DMA_WINDOW_LOW);
666 	bcm_pcib_set_reg(sc, REG_DMA_WINDOW_HIGH, REG_VALUE_DMA_WINDOW_HIGH);
667 	bcm_pcib_set_reg(sc, REG_DMA_CONFIG, REG_VALUE_DMA_WINDOW_CONFIG);
668 
669 	bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0);
670 	bcm_pcib_set_reg(sc, REG_DMA_WINDOW_1, 0);
671 
672 	bcm_pcib_enable_controller(sc);
673 
674 	/* Wait for controller to start. */
675 	for(tries = 0; ; ++tries) {
676 		bridge_state = bcm_pcib_read_reg(sc, REG_BRIDGE_STATE);
677 
678 		if ((bridge_state & 0x30) == 0x30)
679 			/* Controller ready. */
680 			break;
681 
682 		if (tries > 100) {
683 			device_printf(dev,
684 			    "error: controller failed to start.\n");
685 			return (ENXIO);
686 		}
687 
688 		DELAY(1000);
689 	}
690 
691 	link_state = bcm_pcib_read_reg(sc, REG_BRIDGE_LINK_STATE) >> 0x10;
692 	if (!link_state) {
693 		device_printf(dev, "error: controller started but link is not "
694 		    "up.\n");
695 		return (ENXIO);
696 	}
697 	if (bootverbose)
698 		device_printf(dev, "note: reported link speed is %s.\n",
699 		    bcm_pcib_link_state_string(link_state));
700 
701 	/*
702 	 * Set the CPU->PCI memory window. The map in this direction is not 1:1.
703 	 * Addresses seen by the CPU need to be adjusted to make sense to the
704 	 * controller as they pass through the window.
705 	 */
706 	pci_base  = sc->base.base.ranges[0].pci_base;
707 	phys_base = sc->base.base.ranges[0].phys_base;
708 	size      = sc->base.base.ranges[0].size;
709 
710 	bcm_pcib_set_reg(sc, REG_BUS_WINDOW_LOW, pci_base & 0xffffffff);
711 	bcm_pcib_set_reg(sc, REG_BUS_WINDOW_HIGH, pci_base >> 32);
712 
713 	bcm_pcib_set_reg(sc, REG_CPU_WINDOW_LOW,
714 	    encode_cpu_window_low(phys_base, size));
715 	bcm_pcib_set_reg(sc, REG_CPU_WINDOW_START_HIGH,
716 	    encode_cpu_window_start_high(phys_base));
717 	bcm_pcib_set_reg(sc, REG_CPU_WINDOW_END_HIGH,
718 	    encode_cpu_window_end_high(phys_base, size));
719 
720 	/*
721 	 * The controller starts up declaring itself an endpoint; readvertise it
722 	 * as a bridge.
723 	 */
724 	bcm_pcib_set_reg(sc, PCI_ID_VAL3,
725 	    PCIC_BRIDGE << CLASS_SHIFT | PCIS_BRIDGE_PCI << SUBCLASS_SHIFT);
726 
727 	bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0x2);
728 	DELAY(100);
729 
730 	bcm_pcib_relocate_bridge_window(dev);
731 
732 	/* Configure interrupts. */
733 	error = bcm_pcib_msi_attach(dev);
734 	if (error != 0)
735 		return (error);
736 
737 	/* Done. */
738 	device_add_child(dev, "pci", -1);
739 	return (bus_generic_attach(dev));
740 }
741 
742 /*
743  * Device method table.
744  */
745 static device_method_t bcm_pcib_methods[] = {
746 	/* Bus interface. */
747 	DEVMETHOD(bus_get_dma_tag,		bcm_pcib_get_dma_tag),
748 
749 	/* Device interface. */
750 	DEVMETHOD(device_probe,			bcm_pcib_probe),
751 	DEVMETHOD(device_attach,		bcm_pcib_attach),
752 
753 	/* PCIB interface. */
754 	DEVMETHOD(pcib_read_config,		bcm_pcib_read_config),
755 	DEVMETHOD(pcib_write_config,		bcm_pcib_write_config),
756 
757 	/* MSI interface. */
758 	DEVMETHOD(msi_alloc_msi,		bcm_pcib_alloc_msi),
759 	DEVMETHOD(msi_release_msi,		bcm_pcib_release_msi),
760 	DEVMETHOD(msi_map_msi,			bcm_pcib_map_msi),
761 
762 	DEVMETHOD_END
763 };
764 
765 DEFINE_CLASS_1(pcib, bcm_pcib_driver, bcm_pcib_methods,
766     sizeof(struct bcm_pcib_softc), generic_pcie_fdt_driver);
767 
768 DRIVER_MODULE(bcm_pcib, simplebus, bcm_pcib_driver, 0, 0);
769 
770