1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2020 Dr Robert Harvey Crowston <crowston@protonmail.com> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 */ 20 21 /* 22 * BCM2838-compatible PCI-express controller. 23 * 24 * Broadcom likes to give the same chip lots of different names. The name of 25 * this driver is taken from the Raspberry Pi 4 Broadcom 2838 chip. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/endian.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/bus.h> 34 #include <sys/proc.h> 35 #include <sys/rman.h> 36 #include <sys/intr.h> 37 #include <sys/mutex.h> 38 39 #include <dev/ofw/openfirm.h> 40 #include <dev/ofw/ofw_bus.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include <dev/pci/pci_host_generic.h> 44 #include <dev/pci/pci_host_generic_fdt.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcib_private.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include "pcib_if.h" 53 #include "msi_if.h" 54 55 #define PCI_ID_VAL3 0x43c 56 #define CLASS_SHIFT 0x10 57 #define SUBCLASS_SHIFT 0x8 58 59 #define REG_CONTROLLER_HW_REV 0x406c 60 #define REG_BRIDGE_CTRL 0x9210 61 #define BRIDGE_DISABLE_FLAG 0x1 62 #define BRIDGE_RESET_FLAG 0x2 63 #define REG_BRIDGE_SERDES_MODE 0x4204 64 #define REG_DMA_CONFIG 0x4008 65 #define REG_DMA_WINDOW_LOW 0x4034 66 #define REG_DMA_WINDOW_HIGH 0x4038 67 #define REG_DMA_WINDOW_1 0x403c 68 #define REG_BRIDGE_GISB_WINDOW 0x402c 69 #define REG_BRIDGE_STATE 0x4068 70 #define REG_BRIDGE_LINK_STATE 0x00bc 71 #define REG_BUS_WINDOW_LOW 0x400c 72 #define REG_BUS_WINDOW_HIGH 0x4010 73 #define REG_CPU_WINDOW_LOW 0x4070 74 #define REG_CPU_WINDOW_START_HIGH 0x4080 75 #define REG_CPU_WINDOW_END_HIGH 0x4084 76 77 #define REG_MSI_ADDR_LOW 0x4044 78 #define REG_MSI_ADDR_HIGH 0x4048 79 #define REG_MSI_CONFIG 0x404c 80 #define REG_MSI_CLR 0x4508 81 #define REG_MSI_MASK_CLR 0x4514 82 #define REG_MSI_RAISED 0x4500 83 #define REG_MSI_EOI 0x4060 84 #define NUM_MSI 32 85 86 #define REG_EP_CONFIG_CHOICE 0x9000 87 #define REG_EP_CONFIG_DATA 0x8000 88 89 /* 90 * The system memory controller can address up to 16 GiB of physical memory 91 * (although at time of writing the largest memory size available for purchase 92 * is 8 GiB). However, the system DMA controller is capable of accessing only a 93 * limited portion of the address space. Worse, the PCI-e controller has further 94 * constraints for DMA, and those limitations are not wholly clear to the 95 * author. NetBSD and Linux allow DMA on the lower 3 GiB of the physical memory, 96 * but experimentation shows DMA performed above 960 MiB results in data 97 * corruption with this driver. The limit of 960 MiB is taken from OpenBSD, but 98 * apparently that value was chosen for satisfying a constraint of an unrelated 99 * peripheral. 100 * 101 * Whatever the true maximum address, 960 MiB works. 102 */ 103 #define DMA_HIGH_LIMIT 0x3c000000 104 #define MAX_MEMORY_LOG2 0x21 105 #define REG_VALUE_DMA_WINDOW_LOW (MAX_MEMORY_LOG2 - 0xf) 106 #define REG_VALUE_DMA_WINDOW_HIGH 0x0 107 #define DMA_WINDOW_ENABLE 0x3000 108 #define REG_VALUE_DMA_WINDOW_CONFIG \ 109 (((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE) 110 111 #define REG_VALUE_MSI_CONFIG 0xffe06540 112 113 struct bcm_pcib_irqsrc { 114 struct intr_irqsrc isrc; 115 u_int irq; 116 bool allocated; 117 }; 118 119 struct bcm_pcib_softc { 120 struct generic_pcie_fdt_softc base; 121 device_t dev; 122 bus_dma_tag_t dmat; 123 struct mtx config_mtx; 124 struct mtx msi_mtx; 125 struct resource *msi_irq_res; 126 void *msi_intr_cookie; 127 struct bcm_pcib_irqsrc *msi_isrcs; 128 pci_addr_t msi_addr; 129 }; 130 131 static struct ofw_compat_data compat_data[] = { 132 {"brcm,bcm2711-pcie", 1}, 133 {"brcm,bcm7211-pcie", 1}, 134 {"brcm,bcm7445-pcie", 1}, 135 {NULL, 0} 136 }; 137 138 static int 139 bcm_pcib_probe(device_t dev) 140 { 141 142 if (!ofw_bus_status_okay(dev)) 143 return (ENXIO); 144 145 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 146 return (ENXIO); 147 148 device_set_desc(dev, 149 "BCM2838-compatible PCI-express controller"); 150 return (BUS_PROBE_DEFAULT); 151 } 152 153 static bus_dma_tag_t 154 bcm_pcib_get_dma_tag(device_t dev, device_t child) 155 { 156 struct bcm_pcib_softc *sc; 157 158 sc = device_get_softc(dev); 159 return (sc->dmat); 160 } 161 162 static void 163 bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val) 164 { 165 166 bus_write_4(sc->base.base.res, reg, htole32(val)); 167 } 168 169 static uint32_t 170 bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg) 171 { 172 173 return (le32toh(bus_read_4(sc->base.base.res, reg))); 174 } 175 176 static void 177 bcm_pcib_reset_controller(struct bcm_pcib_softc *sc) 178 { 179 uint32_t val; 180 181 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 182 val = val | BRIDGE_RESET_FLAG | BRIDGE_DISABLE_FLAG; 183 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 184 185 DELAY(100); 186 187 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 188 val = val & ~BRIDGE_RESET_FLAG; 189 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 190 191 DELAY(100); 192 193 bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0); 194 195 DELAY(100); 196 } 197 198 static void 199 bcm_pcib_enable_controller(struct bcm_pcib_softc *sc) 200 { 201 uint32_t val; 202 203 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 204 val = val & ~BRIDGE_DISABLE_FLAG; 205 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 206 207 DELAY(100); 208 } 209 210 static int 211 bcm_pcib_check_ranges(device_t dev) 212 { 213 struct bcm_pcib_softc *sc; 214 struct pcie_range *ranges; 215 int error = 0, i; 216 217 sc = device_get_softc(dev); 218 ranges = &sc->base.base.ranges[0]; 219 220 /* The first range needs to be non-zero. */ 221 if (ranges[0].size == 0) { 222 device_printf(dev, "error: first outbound memory range " 223 "(pci addr: 0x%jx, cpu addr: 0x%jx) has zero size.\n", 224 ranges[0].pci_base, ranges[0].phys_base); 225 error = ENXIO; 226 } 227 228 /* 229 * The controller can actually handle three distinct ranges, but we 230 * only implement support for one. 231 */ 232 for (i = 1; (bootverbose || error) && i < MAX_RANGES_TUPLES; ++i) { 233 if (ranges[i].size > 0) 234 device_printf(dev, 235 "note: outbound memory range %d (pci addr: 0x%jx, " 236 "cpu addr: 0x%jx, size: 0x%jx) will be ignored.\n", 237 i, ranges[i].pci_base, ranges[i].phys_base, 238 ranges[i].size); 239 } 240 241 return (error); 242 } 243 244 static const char * 245 bcm_pcib_link_state_string(uint32_t mode) 246 { 247 248 switch(mode & PCIEM_LINK_STA_SPEED) { 249 case 0: 250 return ("not up"); 251 case 1: 252 return ("2.5 GT/s"); 253 case 2: 254 return ("5.0 GT/s"); 255 case 4: 256 return ("8.0 GT/s"); 257 default: 258 return ("unknown"); 259 } 260 } 261 262 static bus_addr_t 263 bcm_get_offset_and_prepare_config(struct bcm_pcib_softc *sc, u_int bus, 264 u_int slot, u_int func, u_int reg) 265 { 266 /* 267 * Config for an end point is only available through a narrow window for 268 * one end point at a time. We first tell the controller which end point 269 * we want, then access it through the window. 270 */ 271 uint32_t func_index; 272 273 if (bus == 0 && slot == 0 && func == 0) 274 /* 275 * Special case for root device; its config is always available 276 * through the zero-offset. 277 */ 278 return (reg); 279 280 /* Tell the controller to show us the config in question. */ 281 func_index = PCIE_ADDR_OFFSET(bus, slot, func, 0); 282 bcm_pcib_set_reg(sc, REG_EP_CONFIG_CHOICE, func_index); 283 284 return (REG_EP_CONFIG_DATA + reg); 285 } 286 287 static bool 288 bcm_pcib_is_valid_quad(struct bcm_pcib_softc *sc, u_int bus, u_int slot, 289 u_int func, u_int reg) 290 { 291 292 if ((bus < sc->base.base.bus_start) || (bus > sc->base.base.bus_end)) 293 return (false); 294 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 295 return (false); 296 297 if (bus == 0 && slot == 0 && func == 0) 298 return (true); 299 if (bus == 0) 300 /* 301 * Probing other slots and funcs on bus 0 will lock up the 302 * memory controller. 303 */ 304 return (false); 305 306 return (true); 307 } 308 309 static uint32_t 310 bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 311 int bytes) 312 { 313 struct bcm_pcib_softc *sc; 314 bus_addr_t offset; 315 uint32_t data; 316 317 sc = device_get_softc(dev); 318 if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) 319 return (~0U); 320 321 mtx_lock(&sc->config_mtx); 322 offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); 323 324 switch (bytes) { 325 case 1: 326 data = bus_read_1(sc->base.base.res, offset); 327 break; 328 case 2: 329 data = le16toh(bus_read_2(sc->base.base.res, offset)); 330 break; 331 case 4: 332 data = le32toh(bus_read_4(sc->base.base.res, offset)); 333 break; 334 default: 335 data = ~0U; 336 break; 337 } 338 339 mtx_unlock(&sc->config_mtx); 340 return (data); 341 } 342 343 static void 344 bcm_pcib_write_config(device_t dev, u_int bus, u_int slot, 345 u_int func, u_int reg, uint32_t val, int bytes) 346 { 347 struct bcm_pcib_softc *sc; 348 uint32_t offset; 349 350 sc = device_get_softc(dev); 351 if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) 352 return; 353 354 mtx_lock(&sc->config_mtx); 355 offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); 356 357 switch (bytes) { 358 case 1: 359 bus_write_1(sc->base.base.res, offset, val); 360 break; 361 case 2: 362 bus_write_2(sc->base.base.res, offset, htole16(val)); 363 break; 364 case 4: 365 bus_write_4(sc->base.base.res, offset, htole32(val)); 366 break; 367 default: 368 break; 369 } 370 371 mtx_unlock(&sc->config_mtx); 372 } 373 374 static void 375 bcm_pcib_msi_intr_process(struct bcm_pcib_softc *sc, uint32_t interrupt_bitmap, 376 struct trapframe *tf) 377 { 378 struct bcm_pcib_irqsrc *irqsrc; 379 uint32_t bit, irq; 380 381 while ((bit = ffs(interrupt_bitmap))) { 382 irq = bit - 1; 383 384 /* Acknowledge interrupt. */ 385 bcm_pcib_set_reg(sc, REG_MSI_CLR, 1 << irq); 386 387 /* Send EOI. */ 388 bcm_pcib_set_reg(sc, REG_MSI_EOI, 1); 389 390 /* Despatch to handler. */ 391 irqsrc = &sc->msi_isrcs[irq]; 392 if (intr_isrc_dispatch(&irqsrc->isrc, tf)) 393 device_printf(sc->dev, 394 "note: unexpected interrupt (%d) triggered.\n", 395 irq); 396 397 /* Done with this interrupt. */ 398 interrupt_bitmap = interrupt_bitmap & ~(1 << irq); 399 } 400 } 401 402 static int 403 bcm_pcib_msi_intr(void *arg) 404 { 405 struct bcm_pcib_softc *sc; 406 struct trapframe *tf; 407 uint32_t interrupt_bitmap; 408 409 sc = (struct bcm_pcib_softc *) arg; 410 tf = curthread->td_intr_frame; 411 412 while ((interrupt_bitmap = bcm_pcib_read_reg(sc, REG_MSI_RAISED))) 413 bcm_pcib_msi_intr_process(sc, interrupt_bitmap, tf); 414 415 return (FILTER_HANDLED); 416 } 417 418 static int 419 bcm_pcib_alloc_msi(device_t dev, device_t child, int count, int maxcount, 420 device_t *pic, struct intr_irqsrc **srcs) 421 { 422 struct bcm_pcib_softc *sc; 423 int first_int, i; 424 425 sc = device_get_softc(dev); 426 mtx_lock(&sc->msi_mtx); 427 428 /* Find a continguous region of free message-signalled interrupts. */ 429 for (first_int = 0; first_int + count < NUM_MSI; ) { 430 for (i = first_int; i < first_int + count; ++i) { 431 if (sc->msi_isrcs[i].allocated) 432 goto next; 433 } 434 goto found; 435 next: 436 first_int = i + 1; 437 } 438 439 /* No appropriate region available. */ 440 mtx_unlock(&sc->msi_mtx); 441 device_printf(dev, "warning: failed to allocate %d MSI messages.\n", 442 count); 443 return (ENXIO); 444 445 found: 446 /* Mark the messages as in use. */ 447 for (i = 0; i < count; ++i) { 448 sc->msi_isrcs[i + first_int].allocated = true; 449 srcs[i] = &(sc->msi_isrcs[i + first_int].isrc); 450 } 451 452 mtx_unlock(&sc->msi_mtx); 453 *pic = device_get_parent(dev); 454 455 return (0); 456 } 457 458 static int 459 bcm_pcib_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 460 uint64_t *addr, uint32_t *data) 461 { 462 struct bcm_pcib_softc *sc; 463 struct bcm_pcib_irqsrc *msi_msg; 464 465 sc = device_get_softc(dev); 466 msi_msg = (struct bcm_pcib_irqsrc *) isrc; 467 468 *addr = sc->msi_addr; 469 *data = (REG_VALUE_MSI_CONFIG & 0xffff) | msi_msg->irq; 470 return (0); 471 } 472 473 static int 474 bcm_pcib_release_msi(device_t dev, device_t child, int count, 475 struct intr_irqsrc **isrc) 476 { 477 struct bcm_pcib_softc *sc; 478 struct bcm_pcib_irqsrc *msi_isrc; 479 int i; 480 481 sc = device_get_softc(dev); 482 mtx_lock(&sc->msi_mtx); 483 484 for (i = 0; i < count; i++) { 485 msi_isrc = (struct bcm_pcib_irqsrc *) isrc[i]; 486 msi_isrc->allocated = false; 487 } 488 489 mtx_unlock(&sc->msi_mtx); 490 return (0); 491 } 492 493 static int 494 bcm_pcib_msi_attach(device_t dev) 495 { 496 struct bcm_pcib_softc *sc; 497 phandle_t node, xref; 498 char const *bcm_name; 499 int error, i, rid; 500 501 sc = device_get_softc(dev); 502 sc->msi_addr = 0xffffffffc; 503 504 /* Clear any pending interrupts. */ 505 bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff); 506 507 rid = 1; 508 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 509 RF_ACTIVE); 510 if (sc->msi_irq_res == NULL) { 511 device_printf(dev, "could not allocate MSI irq resource.\n"); 512 return (ENXIO); 513 } 514 515 sc->msi_isrcs = malloc(sizeof(*sc->msi_isrcs) * NUM_MSI, M_DEVBUF, 516 M_WAITOK | M_ZERO); 517 518 error = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | 519 INTR_MPSAFE, bcm_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 520 if (error != 0) { 521 device_printf(dev, "error: failed to setup MSI handler.\n"); 522 return (error); 523 } 524 525 bcm_name = device_get_nameunit(dev); 526 for (i = 0; i < NUM_MSI; i++) { 527 sc->msi_isrcs[i].irq = i; 528 error = intr_isrc_register(&sc->msi_isrcs[i].isrc, dev, 0, 529 "%s,%u", bcm_name, i); 530 if (error != 0) { 531 device_printf(dev, 532 "error: failed to register interrupt %d.\n", i); 533 return (error); 534 } 535 } 536 537 node = ofw_bus_get_node(dev); 538 xref = OF_xref_from_node(node); 539 OF_device_register_xref(xref, dev); 540 541 error = intr_msi_register(dev, xref); 542 if (error != 0) 543 return (error); 544 545 mtx_init(&sc->msi_mtx, "bcm_pcib: msi_mtx", NULL, MTX_DEF); 546 547 bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff); 548 bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1); 549 bcm_pcib_set_reg(sc, REG_MSI_ADDR_HIGH, (sc->msi_addr >> 32)); 550 bcm_pcib_set_reg(sc, REG_MSI_CONFIG, REG_VALUE_MSI_CONFIG); 551 552 return (0); 553 } 554 555 static void 556 bcm_pcib_relocate_bridge_window(device_t dev) 557 { 558 /* 559 * In principle an out-of-bounds bridge window could be automatically 560 * adjusted at resource-activation time to lie within the bus address 561 * space by pcib_grow_window(), but that is not possible because the 562 * out-of-bounds resource allocation fails at allocation time. Instead, 563 * we will just fix up the window on the controller here, before it is 564 * re-discovered by pcib_probe_windows(). 565 */ 566 567 struct bcm_pcib_softc *sc; 568 pci_addr_t base, size, new_base, new_limit; 569 uint16_t val; 570 571 sc = device_get_softc(dev); 572 573 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMBASE_1, 2); 574 base = PCI_PPBMEMBASE(0, val); 575 576 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, 2); 577 size = PCI_PPBMEMLIMIT(0, val) - base; 578 579 new_base = sc->base.base.ranges[0].pci_base; 580 val = (uint16_t) (new_base >> 16); 581 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMBASE_1, val, 2); 582 583 new_limit = new_base + size; 584 val = (uint16_t) (new_limit >> 16); 585 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, val, 2); 586 } 587 588 static uint32_t 589 encode_cpu_window_low(pci_addr_t phys_base, bus_size_t size) 590 { 591 592 return (((phys_base >> 0x10) & 0xfff0) | 593 ((phys_base + size - 1) & 0xfff00000)); 594 } 595 596 static uint32_t 597 encode_cpu_window_start_high(pci_addr_t phys_base) 598 { 599 600 return ((phys_base >> 0x20) & 0xff); 601 } 602 603 static uint32_t 604 encode_cpu_window_end_high(pci_addr_t phys_base, bus_size_t size) 605 { 606 607 return (((phys_base + size - 1) >> 0x20) & 0xff); 608 } 609 610 static int 611 bcm_pcib_attach(device_t dev) 612 { 613 struct bcm_pcib_softc *sc; 614 pci_addr_t phys_base, pci_base; 615 bus_size_t size; 616 uint32_t hardware_rev, bridge_state, link_state; 617 int error, tries; 618 619 sc = device_get_softc(dev); 620 sc->dev = dev; 621 622 /* 623 * This tag will be used in preference to the one created in 624 * pci_host_generic.c. 625 */ 626 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 627 1, 0, /* alignment, bounds */ 628 DMA_HIGH_LIMIT, /* lowaddr */ 629 BUS_SPACE_MAXADDR, /* highaddr */ 630 NULL, NULL, /* filter, filterarg */ 631 DMA_HIGH_LIMIT, /* maxsize */ 632 BUS_SPACE_UNRESTRICTED, /* nsegments */ 633 DMA_HIGH_LIMIT, /* maxsegsize */ 634 0, /* flags */ 635 NULL, NULL, /* lockfunc, lockarg */ 636 &sc->dmat); 637 if (error != 0) 638 return (error); 639 640 error = pci_host_generic_setup_fdt(dev); 641 if (error != 0) 642 return (error); 643 644 error = bcm_pcib_check_ranges(dev); 645 if (error != 0) 646 return (error); 647 648 mtx_init(&sc->config_mtx, "bcm_pcib: config_mtx", NULL, MTX_DEF); 649 650 bcm_pcib_reset_controller(sc); 651 652 hardware_rev = bcm_pcib_read_reg(sc, REG_CONTROLLER_HW_REV) & 0xffff; 653 device_printf(dev, "hardware identifies as revision 0x%x.\n", 654 hardware_rev); 655 656 /* 657 * Set PCI->CPU memory window. This encodes the inbound window showing 658 * the system memory to the controller. 659 */ 660 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_LOW, REG_VALUE_DMA_WINDOW_LOW); 661 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_HIGH, REG_VALUE_DMA_WINDOW_HIGH); 662 bcm_pcib_set_reg(sc, REG_DMA_CONFIG, REG_VALUE_DMA_WINDOW_CONFIG); 663 664 bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0); 665 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_1, 0); 666 667 bcm_pcib_enable_controller(sc); 668 669 /* Wait for controller to start. */ 670 for(tries = 0; ; ++tries) { 671 bridge_state = bcm_pcib_read_reg(sc, REG_BRIDGE_STATE); 672 673 if ((bridge_state & 0x30) == 0x30) 674 /* Controller ready. */ 675 break; 676 677 if (tries > 100) { 678 device_printf(dev, 679 "error: controller failed to start.\n"); 680 return (ENXIO); 681 } 682 683 DELAY(1000); 684 } 685 686 link_state = bcm_pcib_read_reg(sc, REG_BRIDGE_LINK_STATE) >> 0x10; 687 if (!link_state) { 688 device_printf(dev, "error: controller started but link is not " 689 "up.\n"); 690 return (ENXIO); 691 } 692 if (bootverbose) 693 device_printf(dev, "note: reported link speed is %s.\n", 694 bcm_pcib_link_state_string(link_state)); 695 696 /* 697 * Set the CPU->PCI memory window. The map in this direction is not 1:1. 698 * Addresses seen by the CPU need to be adjusted to make sense to the 699 * controller as they pass through the window. 700 */ 701 pci_base = sc->base.base.ranges[0].pci_base; 702 phys_base = sc->base.base.ranges[0].phys_base; 703 size = sc->base.base.ranges[0].size; 704 705 bcm_pcib_set_reg(sc, REG_BUS_WINDOW_LOW, pci_base & 0xffffffff); 706 bcm_pcib_set_reg(sc, REG_BUS_WINDOW_HIGH, pci_base >> 32); 707 708 bcm_pcib_set_reg(sc, REG_CPU_WINDOW_LOW, 709 encode_cpu_window_low(phys_base, size)); 710 bcm_pcib_set_reg(sc, REG_CPU_WINDOW_START_HIGH, 711 encode_cpu_window_start_high(phys_base)); 712 bcm_pcib_set_reg(sc, REG_CPU_WINDOW_END_HIGH, 713 encode_cpu_window_end_high(phys_base, size)); 714 715 /* 716 * The controller starts up declaring itself an endpoint; readvertise it 717 * as a bridge. 718 */ 719 bcm_pcib_set_reg(sc, PCI_ID_VAL3, 720 PCIC_BRIDGE << CLASS_SHIFT | PCIS_BRIDGE_PCI << SUBCLASS_SHIFT); 721 722 bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0x2); 723 DELAY(100); 724 725 bcm_pcib_relocate_bridge_window(dev); 726 727 /* Configure interrupts. */ 728 error = bcm_pcib_msi_attach(dev); 729 if (error != 0) 730 return (error); 731 732 /* Done. */ 733 device_add_child(dev, "pci", -1); 734 return (bus_generic_attach(dev)); 735 } 736 737 /* 738 * Device method table. 739 */ 740 static device_method_t bcm_pcib_methods[] = { 741 /* Bus interface. */ 742 DEVMETHOD(bus_get_dma_tag, bcm_pcib_get_dma_tag), 743 744 /* Device interface. */ 745 DEVMETHOD(device_probe, bcm_pcib_probe), 746 DEVMETHOD(device_attach, bcm_pcib_attach), 747 748 /* PCIB interface. */ 749 DEVMETHOD(pcib_read_config, bcm_pcib_read_config), 750 DEVMETHOD(pcib_write_config, bcm_pcib_write_config), 751 752 /* MSI interface. */ 753 DEVMETHOD(msi_alloc_msi, bcm_pcib_alloc_msi), 754 DEVMETHOD(msi_release_msi, bcm_pcib_release_msi), 755 DEVMETHOD(msi_map_msi, bcm_pcib_map_msi), 756 757 DEVMETHOD_END 758 }; 759 760 DEFINE_CLASS_1(pcib, bcm_pcib_driver, bcm_pcib_methods, 761 sizeof(struct bcm_pcib_softc), generic_pcie_fdt_driver); 762 763 DRIVER_MODULE(bcm_pcib, simplebus, bcm_pcib_driver, 0, 0); 764 765