1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sysctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/cpu.h> 44 #include <machine/cpufunc.h> 45 #include <machine/resource.h> 46 #include <machine/fdt.h> 47 #include <machine/intr.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <dev/spibus/spi.h> 54 #include <dev/spibus/spibusvar.h> 55 56 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 57 #include <arm/broadcom/bcm2835/bcm2835_spireg.h> 58 #include <arm/broadcom/bcm2835/bcm2835_spivar.h> 59 60 #include "spibus_if.h" 61 62 static void bcm_spi_intr(void *); 63 64 #ifdef BCM_SPI_DEBUG 65 static void 66 bcm_spi_printr(device_t dev) 67 { 68 struct bcm_spi_softc *sc; 69 uint32_t reg; 70 71 sc = device_get_softc(dev); 72 reg = BCM_SPI_READ(sc, SPI_CS); 73 device_printf(dev, "CS=%b\n", reg, 74 "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL" 75 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" 76 "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1" 77 "\30CSPOL2\31DMA_LEN\32LEN_LONG"); 78 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK; 79 if (reg % 2) 80 reg--; 81 if (reg == 0) 82 reg = 65536; 83 device_printf(dev, "CLK=%uMhz/%d=%luhz\n", 84 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg); 85 reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK; 86 device_printf(dev, "DLEN=%d\n", reg); 87 reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK; 88 device_printf(dev, "LTOH=%d\n", reg); 89 reg = BCM_SPI_READ(sc, SPI_DC); 90 device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n", 91 (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT, 92 (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT, 93 (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT, 94 (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT); 95 } 96 #endif 97 98 static void 99 bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask, 100 uint32_t value) 101 { 102 uint32_t reg; 103 104 mtx_assert(&sc->sc_mtx, MA_OWNED); 105 reg = BCM_SPI_READ(sc, off); 106 reg &= ~mask; 107 reg |= value; 108 BCM_SPI_WRITE(sc, off, reg); 109 } 110 111 static int 112 bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS) 113 { 114 struct bcm_spi_softc *sc; 115 uint32_t clk; 116 int error; 117 118 sc = (struct bcm_spi_softc *)arg1; 119 120 BCM_SPI_LOCK(sc); 121 clk = BCM_SPI_READ(sc, SPI_CLK); 122 BCM_SPI_UNLOCK(sc); 123 clk &= 0xffff; 124 if (clk == 0) 125 clk = 65536; 126 clk = SPI_CORE_CLK / clk; 127 128 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); 129 if (error != 0 || req->newptr == NULL) 130 return (error); 131 132 clk = SPI_CORE_CLK / clk; 133 if (clk <= 1) 134 clk = 2; 135 else if (clk % 2) 136 clk--; 137 if (clk > 0xffff) 138 clk = 0; 139 BCM_SPI_LOCK(sc); 140 BCM_SPI_WRITE(sc, SPI_CLK, clk); 141 BCM_SPI_UNLOCK(sc); 142 143 return (0); 144 } 145 146 static int 147 bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit) 148 { 149 struct bcm_spi_softc *sc; 150 uint32_t reg; 151 int error; 152 153 sc = (struct bcm_spi_softc *)arg1; 154 BCM_SPI_LOCK(sc); 155 reg = BCM_SPI_READ(sc, SPI_CS); 156 BCM_SPI_UNLOCK(sc); 157 reg = (reg & bit) ? 1 : 0; 158 159 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 160 if (error != 0 || req->newptr == NULL) 161 return (error); 162 163 if (reg) 164 reg = bit; 165 BCM_SPI_LOCK(sc); 166 bcm_spi_modifyreg(sc, SPI_CS, bit, reg); 167 BCM_SPI_UNLOCK(sc); 168 169 return (0); 170 } 171 172 static int 173 bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS) 174 { 175 176 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL)); 177 } 178 179 static int 180 bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS) 181 { 182 183 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA)); 184 } 185 186 static int 187 bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS) 188 { 189 190 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0)); 191 } 192 193 static int 194 bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS) 195 { 196 197 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1)); 198 } 199 200 static void 201 bcm_spi_sysctl_init(struct bcm_spi_softc *sc) 202 { 203 struct sysctl_ctx_list *ctx; 204 struct sysctl_oid *tree_node; 205 struct sysctl_oid_list *tree; 206 207 /* 208 * Add system sysctl tree/handlers. 209 */ 210 ctx = device_get_sysctl_ctx(sc->sc_dev); 211 tree_node = device_get_sysctl_tree(sc->sc_dev); 212 tree = SYSCTL_CHILDREN(tree_node); 213 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", 214 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 215 bcm_spi_clock_proc, "IU", "SPI BUS clock frequency"); 216 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol", 217 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 218 bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity"); 219 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha", 220 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 221 bcm_spi_cpha_proc, "IU", "SPI BUS clock phase"); 222 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0", 223 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 224 bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity"); 225 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1", 226 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 227 bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity"); 228 } 229 230 static int 231 bcm_spi_probe(device_t dev) 232 { 233 234 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-spi")) 235 return (ENXIO); 236 237 device_set_desc(dev, "BCM2708/2835 SPI controller"); 238 239 return (BUS_PROBE_DEFAULT); 240 } 241 242 static int 243 bcm_spi_attach(device_t dev) 244 { 245 struct bcm_spi_softc *sc; 246 device_t gpio; 247 int i, rid; 248 249 if (device_get_unit(dev) != 0) { 250 device_printf(dev, "only one SPI controller supported\n"); 251 return (ENXIO); 252 } 253 254 sc = device_get_softc(dev); 255 sc->sc_dev = dev; 256 257 /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */ 258 gpio = devclass_get_device(devclass_find("gpio"), 0); 259 if (!gpio) { 260 device_printf(dev, "cannot find gpio0\n"); 261 return (ENXIO); 262 } 263 for (i = 0; i < nitems(bcm_spi_pins); i++) 264 bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0); 265 266 rid = 0; 267 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 268 RF_ACTIVE); 269 if (!sc->sc_mem_res) { 270 device_printf(dev, "cannot allocate memory window\n"); 271 return (ENXIO); 272 } 273 274 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 275 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 276 277 rid = 0; 278 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 279 RF_ACTIVE); 280 if (!sc->sc_irq_res) { 281 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 282 device_printf(dev, "cannot allocate interrupt\n"); 283 return (ENXIO); 284 } 285 286 /* Hook up our interrupt handler. */ 287 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 288 NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) { 289 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 290 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 291 device_printf(dev, "cannot setup the interrupt handler\n"); 292 return (ENXIO); 293 } 294 295 mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF); 296 297 /* Add sysctl nodes. */ 298 bcm_spi_sysctl_init(sc); 299 300 #ifdef BCM_SPI_DEBUG 301 bcm_spi_printr(dev); 302 #endif 303 304 /* 305 * Enable the SPI controller. Clear the rx and tx FIFO. 306 * Defaults to SPI mode 0. 307 */ 308 BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); 309 310 /* Set the SPI clock to 500Khz. */ 311 BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000); 312 313 #ifdef BCM_SPI_DEBUG 314 bcm_spi_printr(dev); 315 #endif 316 317 device_add_child(dev, "spibus", -1); 318 319 return (bus_generic_attach(dev)); 320 } 321 322 static int 323 bcm_spi_detach(device_t dev) 324 { 325 struct bcm_spi_softc *sc; 326 327 bus_generic_detach(dev); 328 329 sc = device_get_softc(dev); 330 mtx_destroy(&sc->sc_mtx); 331 if (sc->sc_intrhand) 332 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 333 if (sc->sc_irq_res) 334 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 335 if (sc->sc_mem_res) 336 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 337 338 return (0); 339 } 340 341 static void 342 bcm_spi_fill_fifo(struct bcm_spi_softc *sc) 343 { 344 struct spi_command *cmd; 345 uint32_t cs, written; 346 uint8_t *data; 347 348 cmd = sc->sc_cmd; 349 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); 350 while (sc->sc_written < sc->sc_len && 351 cs == (SPI_CS_TA | SPI_CS_TXD)) { 352 data = (uint8_t *)cmd->tx_cmd; 353 written = sc->sc_written++; 354 if (written >= cmd->tx_cmd_sz) { 355 data = (uint8_t *)cmd->tx_data; 356 written -= cmd->tx_cmd_sz; 357 } 358 BCM_SPI_WRITE(sc, SPI_FIFO, data[written]); 359 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); 360 } 361 } 362 363 static void 364 bcm_spi_drain_fifo(struct bcm_spi_softc *sc) 365 { 366 struct spi_command *cmd; 367 uint32_t cs, read; 368 uint8_t *data; 369 370 cmd = sc->sc_cmd; 371 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; 372 while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) { 373 data = (uint8_t *)cmd->rx_cmd; 374 read = sc->sc_read++; 375 if (read >= cmd->rx_cmd_sz) { 376 data = (uint8_t *)cmd->rx_data; 377 read -= cmd->rx_cmd_sz; 378 } 379 data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff; 380 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; 381 } 382 } 383 384 static void 385 bcm_spi_intr(void *arg) 386 { 387 struct bcm_spi_softc *sc; 388 389 sc = (struct bcm_spi_softc *)arg; 390 BCM_SPI_LOCK(sc); 391 392 /* Filter stray interrupts. */ 393 if ((sc->sc_flags & BCM_SPI_BUSY) == 0) { 394 BCM_SPI_UNLOCK(sc); 395 return; 396 } 397 398 /* TX - Fill up the FIFO. */ 399 bcm_spi_fill_fifo(sc); 400 401 /* RX - Drain the FIFO. */ 402 bcm_spi_drain_fifo(sc); 403 404 /* Check for end of transfer. */ 405 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { 406 /* Disable interrupts and the SPI engine. */ 407 bcm_spi_modifyreg(sc, SPI_CS, 408 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); 409 wakeup(sc->sc_dev); 410 } 411 412 BCM_SPI_UNLOCK(sc); 413 } 414 415 static int 416 bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 417 { 418 struct bcm_spi_softc *sc; 419 int cs, err; 420 421 sc = device_get_softc(dev); 422 423 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 424 ("TX/RX command sizes should be equal")); 425 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 426 ("TX/RX data sizes should be equal")); 427 428 BCM_SPI_LOCK(sc); 429 430 /* If the controller is in use wait until it is available. */ 431 while (sc->sc_flags & BCM_SPI_BUSY) 432 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0); 433 434 /* Now we have control over SPI controller. */ 435 sc->sc_flags = BCM_SPI_BUSY; 436 437 /* Clear the FIFO. */ 438 bcm_spi_modifyreg(sc, SPI_CS, 439 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO, 440 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); 441 442 /* Get the proper chip select for this child. */ 443 spibus_get_cs(child, &cs); 444 if (cs < 0 || cs > 2) { 445 device_printf(dev, 446 "Invalid chip select %d requested by %s\n", cs, 447 device_get_nameunit(child)); 448 BCM_SPI_UNLOCK(sc); 449 return (EINVAL); 450 } 451 452 /* Save a pointer to the SPI command. */ 453 sc->sc_cmd = cmd; 454 sc->sc_read = 0; 455 sc->sc_written = 0; 456 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; 457 458 /* 459 * Set the CS for this transaction, enable interrupts and announce 460 * we're ready to tx. This will kick off the first interrupt. 461 */ 462 bcm_spi_modifyreg(sc, SPI_CS, 463 SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 464 cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD); 465 466 /* Wait for the transaction to complete. */ 467 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2); 468 469 /* Make sure the SPI engine and interrupts are disabled. */ 470 bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); 471 472 /* Clear the controller flags. */ 473 sc->sc_flags = 0; 474 475 /* 476 * Check for transfer timeout. The SPI controller doesn't 477 * return errors. 478 */ 479 if (err == EWOULDBLOCK) { 480 device_printf(sc->sc_dev, "SPI error\n"); 481 err = EIO; 482 } 483 484 BCM_SPI_UNLOCK(sc); 485 486 return (err); 487 } 488 489 static phandle_t 490 bcm_spi_get_node(device_t bus, device_t dev) 491 { 492 493 /* We only have one child, the SPI bus, which needs our own node. */ 494 return (ofw_bus_get_node(bus)); 495 } 496 497 static device_method_t bcm_spi_methods[] = { 498 /* Device interface */ 499 DEVMETHOD(device_probe, bcm_spi_probe), 500 DEVMETHOD(device_attach, bcm_spi_attach), 501 DEVMETHOD(device_detach, bcm_spi_detach), 502 503 /* SPI interface */ 504 DEVMETHOD(spibus_transfer, bcm_spi_transfer), 505 506 /* ofw_bus interface */ 507 DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node), 508 509 DEVMETHOD_END 510 }; 511 512 static devclass_t bcm_spi_devclass; 513 514 static driver_t bcm_spi_driver = { 515 "spi", 516 bcm_spi_methods, 517 sizeof(struct bcm_spi_softc), 518 }; 519 520 DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0); 521