1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/mmc/bridge.h> 49 #include <dev/mmc/mmcreg.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include <dev/sdhci/sdhci.h> 53 #include "sdhci_if.h" 54 55 #include "bcm2835_dma.h" 56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 57 #include "bcm2835_vcbus.h" 58 59 #define BCM2835_DEFAULT_SDHCI_FREQ 50 60 61 #define BCM_SDHCI_BUFFER_SIZE 512 62 #define NUM_DMA_SEGS 2 63 64 #ifdef DEBUG 65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define dprintf(fmt, args...) 69 #endif 70 71 static int bcm2835_sdhci_hs = 1; 72 static int bcm2835_sdhci_pio_mode = 0; 73 74 static struct ofw_compat_data compat_data[] = { 75 {"broadcom,bcm2835-sdhci", 1}, 76 {"brcm,bcm2835-mmc", 1}, 77 {NULL, 0} 78 }; 79 80 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 81 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 82 83 struct bcm_sdhci_softc { 84 device_t sc_dev; 85 struct resource * sc_mem_res; 86 struct resource * sc_irq_res; 87 bus_space_tag_t sc_bst; 88 bus_space_handle_t sc_bsh; 89 void * sc_intrhand; 90 struct mmc_request * sc_req; 91 struct sdhci_slot sc_slot; 92 int sc_dma_ch; 93 bus_dma_tag_t sc_dma_tag; 94 bus_dmamap_t sc_dma_map; 95 vm_paddr_t sc_sdhci_buffer_phys; 96 uint32_t cmd_and_mode; 97 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 98 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 99 int dmamap_seg_count; 100 int dmamap_seg_index; 101 int dmamap_status; 102 }; 103 104 static int bcm_sdhci_probe(device_t); 105 static int bcm_sdhci_attach(device_t); 106 static int bcm_sdhci_detach(device_t); 107 static void bcm_sdhci_intr(void *); 108 109 static int bcm_sdhci_get_ro(device_t, device_t); 110 static void bcm_sdhci_dma_intr(int ch, void *arg); 111 112 static void 113 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 114 { 115 struct bcm_sdhci_softc *sc = arg; 116 int i; 117 118 sc->dmamap_status = err; 119 sc->dmamap_seg_count = nseg; 120 121 /* Note nseg is guaranteed to be zero if err is non-zero. */ 122 for (i = 0; i < nseg; i++) { 123 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 124 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 125 } 126 } 127 128 static int 129 bcm_sdhci_probe(device_t dev) 130 { 131 132 if (!ofw_bus_status_okay(dev)) 133 return (ENXIO); 134 135 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 136 return (ENXIO); 137 138 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 139 140 return (BUS_PROBE_DEFAULT); 141 } 142 143 static int 144 bcm_sdhci_attach(device_t dev) 145 { 146 struct bcm_sdhci_softc *sc = device_get_softc(dev); 147 int rid, err; 148 phandle_t node; 149 pcell_t cell; 150 u_int default_freq; 151 152 sc->sc_dev = dev; 153 sc->sc_req = NULL; 154 155 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 156 TRUE); 157 if (err != 0) { 158 if (bootverbose) 159 device_printf(dev, "Unable to enable the power\n"); 160 return (err); 161 } 162 163 default_freq = 0; 164 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 165 &default_freq); 166 if (err == 0) { 167 /* Convert to MHz */ 168 default_freq /= 1000000; 169 } 170 if (default_freq == 0) { 171 node = ofw_bus_get_node(sc->sc_dev); 172 if ((OF_getencprop(node, "clock-frequency", &cell, 173 sizeof(cell))) > 0) 174 default_freq = cell / 1000000; 175 } 176 if (default_freq == 0) 177 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 178 179 if (bootverbose) 180 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 181 182 rid = 0; 183 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 184 RF_ACTIVE); 185 if (!sc->sc_mem_res) { 186 device_printf(dev, "cannot allocate memory window\n"); 187 err = ENXIO; 188 goto fail; 189 } 190 191 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 192 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 193 194 rid = 0; 195 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 196 RF_ACTIVE); 197 if (!sc->sc_irq_res) { 198 device_printf(dev, "cannot allocate interrupt\n"); 199 err = ENXIO; 200 goto fail; 201 } 202 203 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 204 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 205 device_printf(dev, "cannot setup interrupt handler\n"); 206 err = ENXIO; 207 goto fail; 208 } 209 210 if (!bcm2835_sdhci_pio_mode) 211 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 212 213 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 214 if (bcm2835_sdhci_hs) 215 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 216 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 217 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 218 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 219 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 220 | SDHCI_QUIRK_MISSING_CAPS; 221 222 sdhci_init_slot(dev, &sc->sc_slot, 0); 223 224 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 225 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 226 goto fail; 227 228 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 229 230 /* Allocate bus_dma resources. */ 231 err = bus_dma_tag_create(bus_get_dma_tag(dev), 232 1, 0, BUS_SPACE_MAXADDR_32BIT, 233 BUS_SPACE_MAXADDR, NULL, NULL, 234 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 235 BUS_DMA_ALLOCNOW, NULL, NULL, 236 &sc->sc_dma_tag); 237 238 if (err) { 239 device_printf(dev, "failed allocate DMA tag"); 240 goto fail; 241 } 242 243 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 244 if (err) { 245 device_printf(dev, "bus_dmamap_create failed\n"); 246 goto fail; 247 } 248 249 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 250 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 251 SDHCI_BUFFER; 252 253 bus_generic_probe(dev); 254 bus_generic_attach(dev); 255 256 sdhci_start_slot(&sc->sc_slot); 257 258 return (0); 259 260 fail: 261 if (sc->sc_intrhand) 262 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 263 if (sc->sc_irq_res) 264 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 265 if (sc->sc_mem_res) 266 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 267 268 return (err); 269 } 270 271 static int 272 bcm_sdhci_detach(device_t dev) 273 { 274 275 return (EBUSY); 276 } 277 278 static void 279 bcm_sdhci_intr(void *arg) 280 { 281 struct bcm_sdhci_softc *sc = arg; 282 283 sdhci_generic_intr(&sc->sc_slot); 284 } 285 286 static int 287 bcm_sdhci_get_ro(device_t bus, device_t child) 288 { 289 290 return (0); 291 } 292 293 static inline uint32_t 294 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 295 { 296 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 297 return val; 298 } 299 300 static inline void 301 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 302 { 303 304 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 305 /* 306 * The Arasan HC has a bug where it may lose the content of 307 * consecutive writes to registers that are within two SD-card 308 * clock cycles of each other (a clock domain crossing problem). 309 */ 310 if (sc->sc_slot.clock > 0) 311 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 312 } 313 314 static uint8_t 315 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 316 { 317 struct bcm_sdhci_softc *sc = device_get_softc(dev); 318 uint32_t val = RD4(sc, off & ~3); 319 320 return ((val >> (off & 3)*8) & 0xff); 321 } 322 323 static uint16_t 324 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 325 { 326 struct bcm_sdhci_softc *sc = device_get_softc(dev); 327 uint32_t val = RD4(sc, off & ~3); 328 329 /* 330 * Standard 32-bit handling of command and transfer mode. 331 */ 332 if (off == SDHCI_TRANSFER_MODE) { 333 return (sc->cmd_and_mode >> 16); 334 } else if (off == SDHCI_COMMAND_FLAGS) { 335 return (sc->cmd_and_mode & 0x0000ffff); 336 } 337 return ((val >> (off & 3)*8) & 0xffff); 338 } 339 340 static uint32_t 341 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 342 { 343 struct bcm_sdhci_softc *sc = device_get_softc(dev); 344 345 return RD4(sc, off); 346 } 347 348 static void 349 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 350 uint32_t *data, bus_size_t count) 351 { 352 struct bcm_sdhci_softc *sc = device_get_softc(dev); 353 354 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 355 } 356 357 static void 358 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 359 { 360 struct bcm_sdhci_softc *sc = device_get_softc(dev); 361 uint32_t val32 = RD4(sc, off & ~3); 362 val32 &= ~(0xff << (off & 3)*8); 363 val32 |= (val << (off & 3)*8); 364 WR4(sc, off & ~3, val32); 365 } 366 367 static void 368 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 369 { 370 struct bcm_sdhci_softc *sc = device_get_softc(dev); 371 uint32_t val32; 372 if (off == SDHCI_COMMAND_FLAGS) 373 val32 = sc->cmd_and_mode; 374 else 375 val32 = RD4(sc, off & ~3); 376 val32 &= ~(0xffff << (off & 3)*8); 377 val32 |= (val << (off & 3)*8); 378 if (off == SDHCI_TRANSFER_MODE) 379 sc->cmd_and_mode = val32; 380 else { 381 WR4(sc, off & ~3, val32); 382 if (off == SDHCI_COMMAND_FLAGS) 383 sc->cmd_and_mode = val32; 384 } 385 } 386 387 static void 388 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 389 { 390 struct bcm_sdhci_softc *sc = device_get_softc(dev); 391 WR4(sc, off, val); 392 } 393 394 static void 395 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 396 uint32_t *data, bus_size_t count) 397 { 398 struct bcm_sdhci_softc *sc = device_get_softc(dev); 399 400 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 401 } 402 403 static void 404 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 405 { 406 struct sdhci_slot *slot; 407 vm_paddr_t pdst, psrc; 408 int err, idx, len, sync_op; 409 410 slot = &sc->sc_slot; 411 idx = sc->dmamap_seg_index++; 412 len = sc->dmamap_seg_sizes[idx]; 413 slot->offset += len; 414 415 if (slot->curcmd->data->flags & MMC_DATA_READ) { 416 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 417 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 418 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 419 BCM_DMA_INC_ADDR, 420 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 421 psrc = sc->sc_sdhci_buffer_phys; 422 pdst = sc->dmamap_seg_addrs[idx]; 423 sync_op = BUS_DMASYNC_PREREAD; 424 } else { 425 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 426 BCM_DMA_INC_ADDR, 427 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 428 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 429 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 430 psrc = sc->dmamap_seg_addrs[idx]; 431 pdst = sc->sc_sdhci_buffer_phys; 432 sync_op = BUS_DMASYNC_PREWRITE; 433 } 434 435 /* 436 * When starting a new DMA operation do the busdma sync operation, and 437 * disable SDCHI data interrrupts because we'll be driven by DMA 438 * interrupts (or SDHCI error interrupts) until the IO is done. 439 */ 440 if (idx == 0) { 441 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 442 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 443 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 444 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 445 slot->intmask); 446 } 447 448 /* 449 * Start the DMA transfer. Only programming errors (like failing to 450 * allocate a channel) cause a non-zero return from bcm_dma_start(). 451 */ 452 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 453 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 454 } 455 456 static void 457 bcm_sdhci_dma_intr(int ch, void *arg) 458 { 459 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 460 struct sdhci_slot *slot = &sc->sc_slot; 461 uint32_t reg, mask; 462 int left, sync_op; 463 464 mtx_lock(&slot->mtx); 465 466 /* 467 * If there are more segments for the current dma, start the next one. 468 * Otherwise unload the dma map and decide what to do next based on the 469 * status of the sdhci controller and whether there's more data left. 470 */ 471 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 472 bcm_sdhci_start_dma_seg(sc); 473 mtx_unlock(&slot->mtx); 474 return; 475 } 476 477 if (slot->curcmd->data->flags & MMC_DATA_READ) { 478 sync_op = BUS_DMASYNC_POSTREAD; 479 mask = SDHCI_INT_DATA_AVAIL; 480 } else { 481 sync_op = BUS_DMASYNC_POSTWRITE; 482 mask = SDHCI_INT_SPACE_AVAIL; 483 } 484 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 485 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 486 487 sc->dmamap_seg_count = 0; 488 sc->dmamap_seg_index = 0; 489 490 left = min(BCM_SDHCI_BUFFER_SIZE, 491 slot->curcmd->data->len - slot->offset); 492 493 /* DATA END? */ 494 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 495 496 if (reg & SDHCI_INT_DATA_END) { 497 /* ACK for all outstanding interrupts */ 498 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 499 500 /* enable INT */ 501 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 502 | SDHCI_INT_DATA_END; 503 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 504 slot->intmask); 505 506 /* finish this data */ 507 sdhci_finish_data(slot); 508 } 509 else { 510 /* already available? */ 511 if (reg & mask) { 512 513 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 514 bcm_sdhci_write_4(slot->bus, slot, 515 SDHCI_INT_STATUS, mask); 516 517 /* continue next DMA transfer */ 518 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 519 (uint8_t *)slot->curcmd->data->data + 520 slot->offset, left, bcm_sdhci_dmacb, sc, 521 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 522 slot->curcmd->error = MMC_ERR_NO_MEMORY; 523 sdhci_finish_data(slot); 524 } else { 525 bcm_sdhci_start_dma_seg(sc); 526 } 527 } else { 528 /* wait for next data by INT */ 529 530 /* enable INT */ 531 slot->intmask |= SDHCI_INT_DATA_AVAIL | 532 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 533 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 534 slot->intmask); 535 } 536 } 537 538 mtx_unlock(&slot->mtx); 539 } 540 541 static void 542 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 543 { 544 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 545 size_t left; 546 547 if (sc->dmamap_seg_count != 0) { 548 device_printf(sc->sc_dev, "DMA in use\n"); 549 return; 550 } 551 552 left = min(BCM_SDHCI_BUFFER_SIZE, 553 slot->curcmd->data->len - slot->offset); 554 555 KASSERT((left & 3) == 0, 556 ("%s: len = %zu, not word-aligned", __func__, left)); 557 558 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 559 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 560 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 561 sc->dmamap_status != 0) { 562 slot->curcmd->error = MMC_ERR_NO_MEMORY; 563 return; 564 } 565 566 /* DMA start */ 567 bcm_sdhci_start_dma_seg(sc); 568 } 569 570 static void 571 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 572 { 573 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 574 size_t left; 575 576 if (sc->dmamap_seg_count != 0) { 577 device_printf(sc->sc_dev, "DMA in use\n"); 578 return; 579 } 580 581 left = min(BCM_SDHCI_BUFFER_SIZE, 582 slot->curcmd->data->len - slot->offset); 583 584 KASSERT((left & 3) == 0, 585 ("%s: len = %zu, not word-aligned", __func__, left)); 586 587 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 588 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 589 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 590 sc->dmamap_status != 0) { 591 slot->curcmd->error = MMC_ERR_NO_MEMORY; 592 return; 593 } 594 595 /* DMA start */ 596 bcm_sdhci_start_dma_seg(sc); 597 } 598 599 static int 600 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 601 { 602 size_t left; 603 604 /* 605 * Do not use DMA for transfers less than block size or with a length 606 * that is not a multiple of four. 607 */ 608 left = min(BCM_DMA_BLOCK_SIZE, 609 slot->curcmd->data->len - slot->offset); 610 if (left < BCM_DMA_BLOCK_SIZE) 611 return (0); 612 if (left & 0x03) 613 return (0); 614 615 return (1); 616 } 617 618 static void 619 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 620 uint32_t *intmask) 621 { 622 623 /* DMA transfer FIFO 1KB */ 624 if (slot->curcmd->data->flags & MMC_DATA_READ) 625 bcm_sdhci_read_dma(dev, slot); 626 else 627 bcm_sdhci_write_dma(dev, slot); 628 } 629 630 static void 631 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 632 { 633 634 sdhci_finish_data(slot); 635 } 636 637 static device_method_t bcm_sdhci_methods[] = { 638 /* Device interface */ 639 DEVMETHOD(device_probe, bcm_sdhci_probe), 640 DEVMETHOD(device_attach, bcm_sdhci_attach), 641 DEVMETHOD(device_detach, bcm_sdhci_detach), 642 643 /* Bus interface */ 644 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 645 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 646 DEVMETHOD(bus_print_child, bus_generic_print_child), 647 648 /* MMC bridge interface */ 649 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 650 DEVMETHOD(mmcbr_request, sdhci_generic_request), 651 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 652 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 653 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 654 655 /* Platform transfer methods */ 656 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 657 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 658 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 659 /* SDHCI registers accessors */ 660 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 661 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 662 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 663 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 664 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 665 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 666 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 667 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 668 669 { 0, 0 } 670 }; 671 672 static devclass_t bcm_sdhci_devclass; 673 674 static driver_t bcm_sdhci_driver = { 675 "sdhci_bcm", 676 bcm_sdhci_methods, 677 sizeof(struct bcm_sdhci_softc), 678 }; 679 680 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 681 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 682 DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); 683 MODULE_DEPEND(sdhci_bcm, mmc, 1, 1, 1); 684