1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 50 #include <dev/sdhci/sdhci.h> 51 52 #include "mmcbr_if.h" 53 #include "sdhci_if.h" 54 55 #include "opt_mmccam.h" 56 57 #include "bcm2835_dma.h" 58 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 59 #include "bcm2835_vcbus.h" 60 61 #define BCM2835_DEFAULT_SDHCI_FREQ 50 62 63 #define BCM_SDHCI_BUFFER_SIZE 512 64 #define NUM_DMA_SEGS 2 65 66 #ifdef DEBUG 67 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 68 printf(fmt,##args); } while (0) 69 #else 70 #define dprintf(fmt, args...) 71 #endif 72 73 static int bcm2835_sdhci_hs = 1; 74 static int bcm2835_sdhci_pio_mode = 0; 75 76 static struct ofw_compat_data compat_data[] = { 77 {"broadcom,bcm2835-sdhci", 1}, 78 {"brcm,bcm2835-mmc", 1}, 79 {NULL, 0} 80 }; 81 82 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 83 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 84 85 struct bcm_sdhci_softc { 86 device_t sc_dev; 87 struct resource * sc_mem_res; 88 struct resource * sc_irq_res; 89 bus_space_tag_t sc_bst; 90 bus_space_handle_t sc_bsh; 91 void * sc_intrhand; 92 struct mmc_request * sc_req; 93 struct sdhci_slot sc_slot; 94 int sc_dma_ch; 95 bus_dma_tag_t sc_dma_tag; 96 bus_dmamap_t sc_dma_map; 97 vm_paddr_t sc_sdhci_buffer_phys; 98 uint32_t cmd_and_mode; 99 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 100 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 101 int dmamap_seg_count; 102 int dmamap_seg_index; 103 int dmamap_status; 104 }; 105 106 static int bcm_sdhci_probe(device_t); 107 static int bcm_sdhci_attach(device_t); 108 static int bcm_sdhci_detach(device_t); 109 static void bcm_sdhci_intr(void *); 110 111 static int bcm_sdhci_get_ro(device_t, device_t); 112 static void bcm_sdhci_dma_intr(int ch, void *arg); 113 114 static void 115 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 116 { 117 struct bcm_sdhci_softc *sc = arg; 118 int i; 119 120 sc->dmamap_status = err; 121 sc->dmamap_seg_count = nseg; 122 123 /* Note nseg is guaranteed to be zero if err is non-zero. */ 124 for (i = 0; i < nseg; i++) { 125 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 126 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 127 } 128 } 129 130 static int 131 bcm_sdhci_probe(device_t dev) 132 { 133 134 if (!ofw_bus_status_okay(dev)) 135 return (ENXIO); 136 137 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 138 return (ENXIO); 139 140 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 141 142 return (BUS_PROBE_DEFAULT); 143 } 144 145 static int 146 bcm_sdhci_attach(device_t dev) 147 { 148 struct bcm_sdhci_softc *sc = device_get_softc(dev); 149 int rid, err; 150 phandle_t node; 151 pcell_t cell; 152 u_int default_freq; 153 154 sc->sc_dev = dev; 155 sc->sc_req = NULL; 156 157 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 158 TRUE); 159 if (err != 0) { 160 if (bootverbose) 161 device_printf(dev, "Unable to enable the power\n"); 162 return (err); 163 } 164 165 default_freq = 0; 166 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 167 &default_freq); 168 if (err == 0) { 169 /* Convert to MHz */ 170 default_freq /= 1000000; 171 } 172 if (default_freq == 0) { 173 node = ofw_bus_get_node(sc->sc_dev); 174 if ((OF_getencprop(node, "clock-frequency", &cell, 175 sizeof(cell))) > 0) 176 default_freq = cell / 1000000; 177 } 178 if (default_freq == 0) 179 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 180 181 if (bootverbose) 182 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 183 184 rid = 0; 185 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 186 RF_ACTIVE); 187 if (!sc->sc_mem_res) { 188 device_printf(dev, "cannot allocate memory window\n"); 189 err = ENXIO; 190 goto fail; 191 } 192 193 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 194 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 195 196 rid = 0; 197 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 198 RF_ACTIVE); 199 if (!sc->sc_irq_res) { 200 device_printf(dev, "cannot allocate interrupt\n"); 201 err = ENXIO; 202 goto fail; 203 } 204 205 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 206 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 207 device_printf(dev, "cannot setup interrupt handler\n"); 208 err = ENXIO; 209 goto fail; 210 } 211 212 if (!bcm2835_sdhci_pio_mode) 213 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 214 215 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 216 if (bcm2835_sdhci_hs) 217 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 218 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 219 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 220 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 221 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 222 | SDHCI_QUIRK_MISSING_CAPS; 223 224 sdhci_init_slot(dev, &sc->sc_slot, 0); 225 226 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 227 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 228 goto fail; 229 230 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 231 232 /* Allocate bus_dma resources. */ 233 err = bus_dma_tag_create(bus_get_dma_tag(dev), 234 1, 0, BUS_SPACE_MAXADDR_32BIT, 235 BUS_SPACE_MAXADDR, NULL, NULL, 236 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 237 BUS_DMA_ALLOCNOW, NULL, NULL, 238 &sc->sc_dma_tag); 239 240 if (err) { 241 device_printf(dev, "failed allocate DMA tag"); 242 goto fail; 243 } 244 245 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 246 if (err) { 247 device_printf(dev, "bus_dmamap_create failed\n"); 248 goto fail; 249 } 250 251 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 252 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 253 SDHCI_BUFFER; 254 255 bus_generic_probe(dev); 256 bus_generic_attach(dev); 257 258 sdhci_start_slot(&sc->sc_slot); 259 260 return (0); 261 262 fail: 263 if (sc->sc_intrhand) 264 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 265 if (sc->sc_irq_res) 266 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 267 if (sc->sc_mem_res) 268 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 269 270 return (err); 271 } 272 273 static int 274 bcm_sdhci_detach(device_t dev) 275 { 276 277 return (EBUSY); 278 } 279 280 static void 281 bcm_sdhci_intr(void *arg) 282 { 283 struct bcm_sdhci_softc *sc = arg; 284 285 sdhci_generic_intr(&sc->sc_slot); 286 } 287 288 static int 289 bcm_sdhci_get_ro(device_t bus, device_t child) 290 { 291 292 return (0); 293 } 294 295 static inline uint32_t 296 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 297 { 298 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 299 return val; 300 } 301 302 static inline void 303 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 304 { 305 306 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 307 /* 308 * The Arasan HC has a bug where it may lose the content of 309 * consecutive writes to registers that are within two SD-card 310 * clock cycles of each other (a clock domain crossing problem). 311 */ 312 if (sc->sc_slot.clock > 0) 313 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 314 } 315 316 static uint8_t 317 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 318 { 319 struct bcm_sdhci_softc *sc = device_get_softc(dev); 320 uint32_t val = RD4(sc, off & ~3); 321 322 return ((val >> (off & 3)*8) & 0xff); 323 } 324 325 static uint16_t 326 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 327 { 328 struct bcm_sdhci_softc *sc = device_get_softc(dev); 329 uint32_t val = RD4(sc, off & ~3); 330 331 /* 332 * Standard 32-bit handling of command and transfer mode. 333 */ 334 if (off == SDHCI_TRANSFER_MODE) { 335 return (sc->cmd_and_mode >> 16); 336 } else if (off == SDHCI_COMMAND_FLAGS) { 337 return (sc->cmd_and_mode & 0x0000ffff); 338 } 339 return ((val >> (off & 3)*8) & 0xffff); 340 } 341 342 static uint32_t 343 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 344 { 345 struct bcm_sdhci_softc *sc = device_get_softc(dev); 346 347 return RD4(sc, off); 348 } 349 350 static void 351 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 352 uint32_t *data, bus_size_t count) 353 { 354 struct bcm_sdhci_softc *sc = device_get_softc(dev); 355 356 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 357 } 358 359 static void 360 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 361 { 362 struct bcm_sdhci_softc *sc = device_get_softc(dev); 363 uint32_t val32 = RD4(sc, off & ~3); 364 val32 &= ~(0xff << (off & 3)*8); 365 val32 |= (val << (off & 3)*8); 366 WR4(sc, off & ~3, val32); 367 } 368 369 static void 370 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 371 { 372 struct bcm_sdhci_softc *sc = device_get_softc(dev); 373 uint32_t val32; 374 if (off == SDHCI_COMMAND_FLAGS) 375 val32 = sc->cmd_and_mode; 376 else 377 val32 = RD4(sc, off & ~3); 378 val32 &= ~(0xffff << (off & 3)*8); 379 val32 |= (val << (off & 3)*8); 380 if (off == SDHCI_TRANSFER_MODE) 381 sc->cmd_and_mode = val32; 382 else { 383 WR4(sc, off & ~3, val32); 384 if (off == SDHCI_COMMAND_FLAGS) 385 sc->cmd_and_mode = val32; 386 } 387 } 388 389 static void 390 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 391 { 392 struct bcm_sdhci_softc *sc = device_get_softc(dev); 393 WR4(sc, off, val); 394 } 395 396 static void 397 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 398 uint32_t *data, bus_size_t count) 399 { 400 struct bcm_sdhci_softc *sc = device_get_softc(dev); 401 402 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 403 } 404 405 static void 406 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 407 { 408 struct sdhci_slot *slot; 409 vm_paddr_t pdst, psrc; 410 int err, idx, len, sync_op; 411 412 slot = &sc->sc_slot; 413 idx = sc->dmamap_seg_index++; 414 len = sc->dmamap_seg_sizes[idx]; 415 slot->offset += len; 416 417 if (slot->curcmd->data->flags & MMC_DATA_READ) { 418 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 419 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 420 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 421 BCM_DMA_INC_ADDR, 422 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 423 psrc = sc->sc_sdhci_buffer_phys; 424 pdst = sc->dmamap_seg_addrs[idx]; 425 sync_op = BUS_DMASYNC_PREREAD; 426 } else { 427 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 428 BCM_DMA_INC_ADDR, 429 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 430 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 431 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 432 psrc = sc->dmamap_seg_addrs[idx]; 433 pdst = sc->sc_sdhci_buffer_phys; 434 sync_op = BUS_DMASYNC_PREWRITE; 435 } 436 437 /* 438 * When starting a new DMA operation do the busdma sync operation, and 439 * disable SDCHI data interrrupts because we'll be driven by DMA 440 * interrupts (or SDHCI error interrupts) until the IO is done. 441 */ 442 if (idx == 0) { 443 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 444 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 445 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 446 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 447 slot->intmask); 448 } 449 450 /* 451 * Start the DMA transfer. Only programming errors (like failing to 452 * allocate a channel) cause a non-zero return from bcm_dma_start(). 453 */ 454 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 455 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 456 } 457 458 static void 459 bcm_sdhci_dma_intr(int ch, void *arg) 460 { 461 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 462 struct sdhci_slot *slot = &sc->sc_slot; 463 uint32_t reg, mask; 464 int left, sync_op; 465 466 mtx_lock(&slot->mtx); 467 468 /* 469 * If there are more segments for the current dma, start the next one. 470 * Otherwise unload the dma map and decide what to do next based on the 471 * status of the sdhci controller and whether there's more data left. 472 */ 473 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 474 bcm_sdhci_start_dma_seg(sc); 475 mtx_unlock(&slot->mtx); 476 return; 477 } 478 479 if (slot->curcmd->data->flags & MMC_DATA_READ) { 480 sync_op = BUS_DMASYNC_POSTREAD; 481 mask = SDHCI_INT_DATA_AVAIL; 482 } else { 483 sync_op = BUS_DMASYNC_POSTWRITE; 484 mask = SDHCI_INT_SPACE_AVAIL; 485 } 486 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 487 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 488 489 sc->dmamap_seg_count = 0; 490 sc->dmamap_seg_index = 0; 491 492 left = min(BCM_SDHCI_BUFFER_SIZE, 493 slot->curcmd->data->len - slot->offset); 494 495 /* DATA END? */ 496 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 497 498 if (reg & SDHCI_INT_DATA_END) { 499 /* ACK for all outstanding interrupts */ 500 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 501 502 /* enable INT */ 503 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 504 | SDHCI_INT_DATA_END; 505 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 506 slot->intmask); 507 508 /* finish this data */ 509 sdhci_finish_data(slot); 510 } 511 else { 512 /* already available? */ 513 if (reg & mask) { 514 515 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 516 bcm_sdhci_write_4(slot->bus, slot, 517 SDHCI_INT_STATUS, mask); 518 519 /* continue next DMA transfer */ 520 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 521 (uint8_t *)slot->curcmd->data->data + 522 slot->offset, left, bcm_sdhci_dmacb, sc, 523 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 524 slot->curcmd->error = MMC_ERR_NO_MEMORY; 525 sdhci_finish_data(slot); 526 } else { 527 bcm_sdhci_start_dma_seg(sc); 528 } 529 } else { 530 /* wait for next data by INT */ 531 532 /* enable INT */ 533 slot->intmask |= SDHCI_INT_DATA_AVAIL | 534 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 535 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 536 slot->intmask); 537 } 538 } 539 540 mtx_unlock(&slot->mtx); 541 } 542 543 static void 544 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 545 { 546 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 547 size_t left; 548 549 if (sc->dmamap_seg_count != 0) { 550 device_printf(sc->sc_dev, "DMA in use\n"); 551 return; 552 } 553 554 left = min(BCM_SDHCI_BUFFER_SIZE, 555 slot->curcmd->data->len - slot->offset); 556 557 KASSERT((left & 3) == 0, 558 ("%s: len = %zu, not word-aligned", __func__, left)); 559 560 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 561 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 562 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 563 sc->dmamap_status != 0) { 564 slot->curcmd->error = MMC_ERR_NO_MEMORY; 565 return; 566 } 567 568 /* DMA start */ 569 bcm_sdhci_start_dma_seg(sc); 570 } 571 572 static void 573 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 574 { 575 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 576 size_t left; 577 578 if (sc->dmamap_seg_count != 0) { 579 device_printf(sc->sc_dev, "DMA in use\n"); 580 return; 581 } 582 583 left = min(BCM_SDHCI_BUFFER_SIZE, 584 slot->curcmd->data->len - slot->offset); 585 586 KASSERT((left & 3) == 0, 587 ("%s: len = %zu, not word-aligned", __func__, left)); 588 589 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 590 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 591 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 592 sc->dmamap_status != 0) { 593 slot->curcmd->error = MMC_ERR_NO_MEMORY; 594 return; 595 } 596 597 /* DMA start */ 598 bcm_sdhci_start_dma_seg(sc); 599 } 600 601 static int 602 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 603 { 604 size_t left; 605 606 /* 607 * Do not use DMA for transfers less than block size or with a length 608 * that is not a multiple of four. 609 */ 610 left = min(BCM_DMA_BLOCK_SIZE, 611 slot->curcmd->data->len - slot->offset); 612 if (left < BCM_DMA_BLOCK_SIZE) 613 return (0); 614 if (left & 0x03) 615 return (0); 616 617 return (1); 618 } 619 620 static void 621 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 622 uint32_t *intmask) 623 { 624 625 /* DMA transfer FIFO 1KB */ 626 if (slot->curcmd->data->flags & MMC_DATA_READ) 627 bcm_sdhci_read_dma(dev, slot); 628 else 629 bcm_sdhci_write_dma(dev, slot); 630 } 631 632 static void 633 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 634 { 635 636 sdhci_finish_data(slot); 637 } 638 639 static device_method_t bcm_sdhci_methods[] = { 640 /* Device interface */ 641 DEVMETHOD(device_probe, bcm_sdhci_probe), 642 DEVMETHOD(device_attach, bcm_sdhci_attach), 643 DEVMETHOD(device_detach, bcm_sdhci_detach), 644 645 /* Bus interface */ 646 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 647 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 648 649 /* MMC bridge interface */ 650 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 651 DEVMETHOD(mmcbr_request, sdhci_generic_request), 652 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 653 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 654 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 655 656 /* Platform transfer methods */ 657 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 658 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 659 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 660 /* SDHCI registers accessors */ 661 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 662 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 663 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 664 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 665 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 666 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 667 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 668 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 669 670 DEVMETHOD_END 671 }; 672 673 static devclass_t bcm_sdhci_devclass; 674 675 static driver_t bcm_sdhci_driver = { 676 "sdhci_bcm", 677 bcm_sdhci_methods, 678 sizeof(struct bcm_sdhci_softc), 679 }; 680 681 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 682 NULL, NULL); 683 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 684 #ifndef MMCCAM 685 MMC_DECLARE_BRIDGE(sdhci_bcm); 686 #endif 687