1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bio.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/kthread.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/timetc.h> 48 #include <sys/watchdog.h> 49 50 #include <sys/kdb.h> 51 52 #include <machine/bus.h> 53 #include <machine/cpu.h> 54 #include <machine/cpufunc.h> 55 #include <machine/resource.h> 56 #include <machine/intr.h> 57 58 #include <dev/fdt/fdt_common.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include <dev/mmc/bridge.h> 63 #include <dev/mmc/mmcreg.h> 64 #include <dev/mmc/mmcbrvar.h> 65 66 #include <dev/sdhci/sdhci.h> 67 #include "sdhci_if.h" 68 69 #include "bcm2835_dma.h" 70 #include "bcm2835_vcbus.h" 71 72 #define BCM2835_DEFAULT_SDHCI_FREQ 50 73 74 #define BCM_SDHCI_BUFFER_SIZE 512 75 76 #ifdef DEBUG 77 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 78 printf(fmt,##args); } while (0) 79 #else 80 #define dprintf(fmt, args...) 81 #endif 82 83 /* 84 * Arasan HC seems to have problem with Data CRC on lower frequencies. 85 * Use this tunable to cap initialization sequence frequency at higher 86 * value. Default is standard 400kHz 87 */ 88 static int bcm2835_sdhci_min_freq = 400000; 89 static int bcm2835_sdhci_hs = 1; 90 static int bcm2835_sdhci_pio_mode = 0; 91 92 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 93 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 94 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 95 96 struct bcm_sdhci_dmamap_arg { 97 bus_addr_t sc_dma_busaddr; 98 }; 99 100 struct bcm_sdhci_softc { 101 device_t sc_dev; 102 struct mtx sc_mtx; 103 struct resource * sc_mem_res; 104 struct resource * sc_irq_res; 105 bus_space_tag_t sc_bst; 106 bus_space_handle_t sc_bsh; 107 void * sc_intrhand; 108 struct mmc_request * sc_req; 109 struct mmc_data * sc_data; 110 uint32_t sc_flags; 111 #define LPC_SD_FLAGS_IGNORECRC (1 << 0) 112 int sc_xfer_direction; 113 #define DIRECTION_READ 0 114 #define DIRECTION_WRITE 1 115 int sc_xfer_done; 116 int sc_bus_busy; 117 struct sdhci_slot sc_slot; 118 int sc_dma_inuse; 119 int sc_dma_ch; 120 bus_dma_tag_t sc_dma_tag; 121 bus_dmamap_t sc_dma_map; 122 vm_paddr_t sc_sdhci_buffer_phys; 123 }; 124 125 static int bcm_sdhci_probe(device_t); 126 static int bcm_sdhci_attach(device_t); 127 static int bcm_sdhci_detach(device_t); 128 static void bcm_sdhci_intr(void *); 129 130 static int bcm_sdhci_get_ro(device_t, device_t); 131 static void bcm_sdhci_dma_intr(int ch, void *arg); 132 133 #define bcm_sdhci_lock(_sc) \ 134 mtx_lock(&_sc->sc_mtx); 135 #define bcm_sdhci_unlock(_sc) \ 136 mtx_unlock(&_sc->sc_mtx); 137 138 static void 139 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 140 int nseg, int err) 141 { 142 bus_addr_t *addr; 143 144 if (err) 145 return; 146 147 addr = (bus_addr_t*)arg; 148 *addr = segs[0].ds_addr; 149 } 150 151 static int 152 bcm_sdhci_probe(device_t dev) 153 { 154 155 if (!ofw_bus_status_okay(dev)) 156 return (ENXIO); 157 158 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 159 return (ENXIO); 160 161 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 162 return (BUS_PROBE_DEFAULT); 163 } 164 165 static int 166 bcm_sdhci_attach(device_t dev) 167 { 168 struct bcm_sdhci_softc *sc = device_get_softc(dev); 169 int rid, err; 170 phandle_t node; 171 pcell_t cell; 172 int default_freq; 173 174 sc->sc_dev = dev; 175 sc->sc_req = NULL; 176 err = 0; 177 178 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 179 node = ofw_bus_get_node(sc->sc_dev); 180 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 181 default_freq = (int)fdt32_to_cpu(cell)/1000000; 182 183 dprintf("SDHCI frequency: %dMHz\n", default_freq); 184 185 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 186 187 rid = 0; 188 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 189 RF_ACTIVE); 190 if (!sc->sc_mem_res) { 191 device_printf(dev, "cannot allocate memory window\n"); 192 err = ENXIO; 193 goto fail; 194 } 195 196 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 197 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 198 199 rid = 0; 200 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 201 RF_ACTIVE); 202 if (!sc->sc_irq_res) { 203 device_printf(dev, "cannot allocate interrupt\n"); 204 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 205 err = ENXIO; 206 goto fail; 207 } 208 209 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 210 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 211 { 212 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 213 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 214 device_printf(dev, "cannot setup interrupt handler\n"); 215 err = ENXIO; 216 goto fail; 217 } 218 219 if (!bcm2835_sdhci_pio_mode) 220 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 221 222 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 223 if (bcm2835_sdhci_hs) 224 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 225 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 226 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 227 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 228 | SDHCI_QUIRK_MISSING_CAPS; 229 230 sdhci_init_slot(dev, &sc->sc_slot, 0); 231 232 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 233 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 234 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 235 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 236 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 237 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 238 goto fail; 239 240 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 241 242 /* Allocate bus_dma resources. */ 243 err = bus_dma_tag_create(bus_get_dma_tag(dev), 244 1, 0, BUS_SPACE_MAXADDR_32BIT, 245 BUS_SPACE_MAXADDR, NULL, NULL, 246 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE, 247 BUS_DMA_ALLOCNOW, NULL, NULL, 248 &sc->sc_dma_tag); 249 250 if (err) { 251 device_printf(dev, "failed allocate DMA tag"); 252 goto fail; 253 } 254 255 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 256 if (err) { 257 device_printf(dev, "bus_dmamap_create failed\n"); 258 goto fail; 259 } 260 261 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 262 SDHCI_BUFFER); 263 264 bus_generic_probe(dev); 265 bus_generic_attach(dev); 266 267 sdhci_start_slot(&sc->sc_slot); 268 269 return (0); 270 271 fail: 272 if (sc->sc_intrhand) 273 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 274 if (sc->sc_irq_res) 275 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 276 if (sc->sc_mem_res) 277 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 278 279 return (err); 280 } 281 282 static int 283 bcm_sdhci_detach(device_t dev) 284 { 285 286 return (EBUSY); 287 } 288 289 static void 290 bcm_sdhci_intr(void *arg) 291 { 292 struct bcm_sdhci_softc *sc = arg; 293 294 sdhci_generic_intr(&sc->sc_slot); 295 } 296 297 static int 298 bcm_sdhci_get_ro(device_t bus, device_t child) 299 { 300 301 return (0); 302 } 303 304 static inline uint32_t 305 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 306 { 307 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 308 return val; 309 } 310 311 static inline void 312 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 313 { 314 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 315 316 if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL)) 317 { 318 int timeout = 100000; 319 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off) 320 && --timeout > 0) 321 continue; 322 323 if (timeout <= 0) 324 printf("sdhci_brcm: writing 0x%X to reg 0x%X " 325 "always gives 0x%X\n", 326 val, (uint32_t)off, 327 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)); 328 } 329 } 330 331 static uint8_t 332 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 333 { 334 struct bcm_sdhci_softc *sc = device_get_softc(dev); 335 uint32_t val = RD4(sc, off & ~3); 336 337 return ((val >> (off & 3)*8) & 0xff); 338 } 339 340 static uint16_t 341 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 342 { 343 struct bcm_sdhci_softc *sc = device_get_softc(dev); 344 uint32_t val = RD4(sc, off & ~3); 345 346 return ((val >> (off & 3)*8) & 0xffff); 347 } 348 349 static uint32_t 350 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 351 { 352 struct bcm_sdhci_softc *sc = device_get_softc(dev); 353 354 return RD4(sc, off); 355 } 356 357 static void 358 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 359 uint32_t *data, bus_size_t count) 360 { 361 struct bcm_sdhci_softc *sc = device_get_softc(dev); 362 363 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 364 } 365 366 static void 367 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 368 { 369 struct bcm_sdhci_softc *sc = device_get_softc(dev); 370 uint32_t val32 = RD4(sc, off & ~3); 371 val32 &= ~(0xff << (off & 3)*8); 372 val32 |= (val << (off & 3)*8); 373 WR4(sc, off & ~3, val32); 374 } 375 376 static void 377 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 378 { 379 struct bcm_sdhci_softc *sc = device_get_softc(dev); 380 static uint32_t cmd_and_trandfer_mode; 381 uint32_t val32; 382 if (off == SDHCI_COMMAND_FLAGS) 383 val32 = cmd_and_trandfer_mode; 384 else 385 val32 = RD4(sc, off & ~3); 386 val32 &= ~(0xffff << (off & 3)*8); 387 val32 |= (val << (off & 3)*8); 388 if (off == SDHCI_TRANSFER_MODE) 389 cmd_and_trandfer_mode = val32; 390 else 391 WR4(sc, off & ~3, val32); 392 } 393 394 static void 395 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 396 { 397 struct bcm_sdhci_softc *sc = device_get_softc(dev); 398 WR4(sc, off, val); 399 } 400 401 static void 402 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 403 uint32_t *data, bus_size_t count) 404 { 405 struct bcm_sdhci_softc *sc = device_get_softc(dev); 406 407 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 408 } 409 410 static uint32_t 411 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 412 { 413 414 return bcm2835_sdhci_min_freq; 415 } 416 417 static void 418 bcm_sdhci_dma_intr(int ch, void *arg) 419 { 420 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 421 struct sdhci_slot *slot = &sc->sc_slot; 422 uint32_t reg, mask; 423 bus_addr_t pmem; 424 vm_paddr_t pdst, psrc; 425 size_t len; 426 int left, sync_op; 427 428 mtx_lock(&slot->mtx); 429 430 len = bcm_dma_length(sc->sc_dma_ch); 431 if (slot->curcmd->data->flags & MMC_DATA_READ) { 432 sync_op = BUS_DMASYNC_POSTREAD; 433 mask = SDHCI_INT_DATA_AVAIL; 434 } else { 435 sync_op = BUS_DMASYNC_POSTWRITE; 436 mask = SDHCI_INT_SPACE_AVAIL; 437 } 438 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 439 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 440 441 slot->offset += len; 442 sc->sc_dma_inuse = 0; 443 444 left = min(BCM_SDHCI_BUFFER_SIZE, 445 slot->curcmd->data->len - slot->offset); 446 447 /* DATA END? */ 448 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 449 450 if (reg & SDHCI_INT_DATA_END) { 451 /* ACK for all outstanding interrupts */ 452 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 453 454 /* enable INT */ 455 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 456 | SDHCI_INT_DATA_END; 457 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 458 slot->intmask); 459 460 /* finish this data */ 461 sdhci_finish_data(slot); 462 } 463 else { 464 /* already available? */ 465 if (reg & mask) { 466 sc->sc_dma_inuse = 1; 467 468 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 469 bcm_sdhci_write_4(slot->bus, slot, 470 SDHCI_INT_STATUS, mask); 471 472 /* continue next DMA transfer */ 473 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 474 (uint8_t *)slot->curcmd->data->data + 475 slot->offset, left, bcm_dmamap_cb, &pmem, 0); 476 if (slot->curcmd->data->flags & MMC_DATA_READ) { 477 psrc = sc->sc_sdhci_buffer_phys; 478 pdst = pmem; 479 sync_op = BUS_DMASYNC_PREREAD; 480 } else { 481 psrc = pmem; 482 pdst = sc->sc_sdhci_buffer_phys; 483 sync_op = BUS_DMASYNC_PREWRITE; 484 } 485 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 486 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) { 487 /* XXX stop xfer, other error recovery? */ 488 device_printf(sc->sc_dev, "failed DMA start\n"); 489 } 490 } else { 491 /* wait for next data by INT */ 492 493 /* enable INT */ 494 slot->intmask |= SDHCI_INT_DATA_AVAIL | 495 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 496 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 497 slot->intmask); 498 } 499 } 500 501 mtx_unlock(&slot->mtx); 502 } 503 504 static void 505 bcm_sdhci_read_dma(struct sdhci_slot *slot) 506 { 507 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 508 size_t left; 509 bus_addr_t paddr; 510 511 if (sc->sc_dma_inuse) { 512 device_printf(sc->sc_dev, "DMA in use\n"); 513 return; 514 } 515 516 sc->sc_dma_inuse = 1; 517 518 left = min(BCM_SDHCI_BUFFER_SIZE, 519 slot->curcmd->data->len - slot->offset); 520 521 KASSERT((left & 3) == 0, 522 ("%s: len = %d, not word-aligned", __func__, left)); 523 524 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 525 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 526 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 527 BCM_DMA_INC_ADDR, 528 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 529 530 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 531 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 532 bcm_dmamap_cb, &paddr, 0); 533 534 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 535 BUS_DMASYNC_PREREAD); 536 537 /* DMA start */ 538 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys, 539 paddr, left) != 0) 540 device_printf(sc->sc_dev, "failed DMA start\n"); 541 } 542 543 static void 544 bcm_sdhci_write_dma(struct sdhci_slot *slot) 545 { 546 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 547 size_t left; 548 bus_addr_t paddr; 549 550 if (sc->sc_dma_inuse) { 551 device_printf(sc->sc_dev, "DMA in use\n"); 552 return; 553 } 554 555 sc->sc_dma_inuse = 1; 556 557 left = min(BCM_SDHCI_BUFFER_SIZE, 558 slot->curcmd->data->len - slot->offset); 559 560 KASSERT((left & 3) == 0, 561 ("%s: len = %d, not word-aligned", __func__, left)); 562 563 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 564 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 565 bcm_dmamap_cb, &paddr, 0); 566 567 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 568 BCM_DMA_INC_ADDR, 569 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 570 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 571 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 572 573 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 574 BUS_DMASYNC_PREWRITE); 575 576 /* DMA start */ 577 if (bcm_dma_start(sc->sc_dma_ch, paddr, 578 sc->sc_sdhci_buffer_phys, left) != 0) 579 device_printf(sc->sc_dev, "failed DMA start\n"); 580 } 581 582 static int 583 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 584 { 585 size_t left; 586 587 /* 588 * Do not use DMA for transfers less than block size or with a length 589 * that is not a multiple of four. 590 */ 591 left = min(BCM_DMA_BLOCK_SIZE, 592 slot->curcmd->data->len - slot->offset); 593 if (left < BCM_DMA_BLOCK_SIZE) 594 return (0); 595 if (left & 0x03) 596 return (0); 597 598 return (1); 599 } 600 601 static void 602 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 603 uint32_t *intmask) 604 { 605 606 /* Disable INT */ 607 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 608 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 609 610 /* DMA transfer FIFO 1KB */ 611 if (slot->curcmd->data->flags & MMC_DATA_READ) 612 bcm_sdhci_read_dma(slot); 613 else 614 bcm_sdhci_write_dma(slot); 615 } 616 617 static void 618 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 619 { 620 621 sdhci_finish_data(slot); 622 } 623 624 static device_method_t bcm_sdhci_methods[] = { 625 /* Device interface */ 626 DEVMETHOD(device_probe, bcm_sdhci_probe), 627 DEVMETHOD(device_attach, bcm_sdhci_attach), 628 DEVMETHOD(device_detach, bcm_sdhci_detach), 629 630 /* Bus interface */ 631 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 632 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 633 DEVMETHOD(bus_print_child, bus_generic_print_child), 634 635 /* MMC bridge interface */ 636 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 637 DEVMETHOD(mmcbr_request, sdhci_generic_request), 638 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 639 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 640 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 641 642 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 643 /* Platform transfer methods */ 644 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 645 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 646 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 647 /* SDHCI registers accessors */ 648 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 649 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 650 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 651 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 652 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 653 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 654 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 655 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 656 657 { 0, 0 } 658 }; 659 660 static devclass_t bcm_sdhci_devclass; 661 662 static driver_t bcm_sdhci_driver = { 663 "sdhci_bcm", 664 bcm_sdhci_methods, 665 sizeof(struct bcm_sdhci_softc), 666 }; 667 668 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 669 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 670