1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <machine/bus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 52 #include <dev/sdhci/sdhci.h> 53 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 #include "opt_mmccam.h" 58 59 #include "bcm2835_dma.h" 60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 61 #include "bcm2835_vcbus.h" 62 63 #define BCM2835_DEFAULT_SDHCI_FREQ 50 64 65 #define BCM_SDHCI_BUFFER_SIZE 512 66 #define NUM_DMA_SEGS 2 67 68 #ifdef DEBUG 69 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 70 printf(fmt,##args); } while (0) 71 #else 72 #define dprintf(fmt, args...) 73 #endif 74 75 static int bcm2835_sdhci_hs = 1; 76 static int bcm2835_sdhci_pio_mode = 0; 77 78 static struct ofw_compat_data compat_data[] = { 79 {"broadcom,bcm2835-sdhci", 1}, 80 {"brcm,bcm2835-mmc", 1}, 81 {NULL, 0} 82 }; 83 84 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 85 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 86 87 struct bcm_sdhci_softc { 88 device_t sc_dev; 89 struct resource * sc_mem_res; 90 struct resource * sc_irq_res; 91 bus_space_tag_t sc_bst; 92 bus_space_handle_t sc_bsh; 93 void * sc_intrhand; 94 struct mmc_request * sc_req; 95 struct sdhci_slot sc_slot; 96 int sc_dma_ch; 97 bus_dma_tag_t sc_dma_tag; 98 bus_dmamap_t sc_dma_map; 99 vm_paddr_t sc_sdhci_buffer_phys; 100 uint32_t cmd_and_mode; 101 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 102 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 103 int dmamap_seg_count; 104 int dmamap_seg_index; 105 int dmamap_status; 106 }; 107 108 static int bcm_sdhci_probe(device_t); 109 static int bcm_sdhci_attach(device_t); 110 static int bcm_sdhci_detach(device_t); 111 static void bcm_sdhci_intr(void *); 112 113 static int bcm_sdhci_get_ro(device_t, device_t); 114 static void bcm_sdhci_dma_intr(int ch, void *arg); 115 116 static void 117 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 118 { 119 struct bcm_sdhci_softc *sc = arg; 120 int i; 121 122 sc->dmamap_status = err; 123 sc->dmamap_seg_count = nseg; 124 125 /* Note nseg is guaranteed to be zero if err is non-zero. */ 126 for (i = 0; i < nseg; i++) { 127 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 128 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 129 } 130 } 131 132 static int 133 bcm_sdhci_probe(device_t dev) 134 { 135 136 if (!ofw_bus_status_okay(dev)) 137 return (ENXIO); 138 139 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 140 return (ENXIO); 141 142 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 143 144 return (BUS_PROBE_DEFAULT); 145 } 146 147 static int 148 bcm_sdhci_attach(device_t dev) 149 { 150 struct bcm_sdhci_softc *sc = device_get_softc(dev); 151 int rid, err; 152 phandle_t node; 153 pcell_t cell; 154 u_int default_freq; 155 156 sc->sc_dev = dev; 157 sc->sc_req = NULL; 158 159 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 160 TRUE); 161 if (err != 0) { 162 if (bootverbose) 163 device_printf(dev, "Unable to enable the power\n"); 164 return (err); 165 } 166 167 default_freq = 0; 168 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 169 &default_freq); 170 if (err == 0) { 171 /* Convert to MHz */ 172 default_freq /= 1000000; 173 } 174 if (default_freq == 0) { 175 node = ofw_bus_get_node(sc->sc_dev); 176 if ((OF_getencprop(node, "clock-frequency", &cell, 177 sizeof(cell))) > 0) 178 default_freq = cell / 1000000; 179 } 180 if (default_freq == 0) 181 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 182 183 if (bootverbose) 184 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 185 186 rid = 0; 187 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 188 RF_ACTIVE); 189 if (!sc->sc_mem_res) { 190 device_printf(dev, "cannot allocate memory window\n"); 191 err = ENXIO; 192 goto fail; 193 } 194 195 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 196 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 197 198 rid = 0; 199 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 200 RF_ACTIVE); 201 if (!sc->sc_irq_res) { 202 device_printf(dev, "cannot allocate interrupt\n"); 203 err = ENXIO; 204 goto fail; 205 } 206 207 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 208 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 209 device_printf(dev, "cannot setup interrupt handler\n"); 210 err = ENXIO; 211 goto fail; 212 } 213 214 if (!bcm2835_sdhci_pio_mode) 215 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 216 217 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 218 if (bcm2835_sdhci_hs) 219 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 220 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 221 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 222 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 223 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 224 | SDHCI_QUIRK_MISSING_CAPS; 225 226 sdhci_init_slot(dev, &sc->sc_slot, 0); 227 228 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 229 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 230 goto fail; 231 232 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 233 234 /* Allocate bus_dma resources. */ 235 err = bus_dma_tag_create(bus_get_dma_tag(dev), 236 1, 0, BUS_SPACE_MAXADDR_32BIT, 237 BUS_SPACE_MAXADDR, NULL, NULL, 238 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 239 BUS_DMA_ALLOCNOW, NULL, NULL, 240 &sc->sc_dma_tag); 241 242 if (err) { 243 device_printf(dev, "failed allocate DMA tag"); 244 goto fail; 245 } 246 247 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 248 if (err) { 249 device_printf(dev, "bus_dmamap_create failed\n"); 250 goto fail; 251 } 252 253 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 254 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 255 SDHCI_BUFFER; 256 257 bus_generic_probe(dev); 258 bus_generic_attach(dev); 259 260 sdhci_start_slot(&sc->sc_slot); 261 262 return (0); 263 264 fail: 265 if (sc->sc_intrhand) 266 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 267 if (sc->sc_irq_res) 268 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 269 if (sc->sc_mem_res) 270 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 271 272 return (err); 273 } 274 275 static int 276 bcm_sdhci_detach(device_t dev) 277 { 278 279 return (EBUSY); 280 } 281 282 static void 283 bcm_sdhci_intr(void *arg) 284 { 285 struct bcm_sdhci_softc *sc = arg; 286 287 sdhci_generic_intr(&sc->sc_slot); 288 } 289 290 static int 291 bcm_sdhci_get_ro(device_t bus, device_t child) 292 { 293 294 return (0); 295 } 296 297 static inline uint32_t 298 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 299 { 300 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 301 return val; 302 } 303 304 static inline void 305 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 306 { 307 308 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 309 /* 310 * The Arasan HC has a bug where it may lose the content of 311 * consecutive writes to registers that are within two SD-card 312 * clock cycles of each other (a clock domain crossing problem). 313 */ 314 if (sc->sc_slot.clock > 0) 315 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 316 } 317 318 static uint8_t 319 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 320 { 321 struct bcm_sdhci_softc *sc = device_get_softc(dev); 322 uint32_t val = RD4(sc, off & ~3); 323 324 return ((val >> (off & 3)*8) & 0xff); 325 } 326 327 static uint16_t 328 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 329 { 330 struct bcm_sdhci_softc *sc = device_get_softc(dev); 331 uint32_t val = RD4(sc, off & ~3); 332 333 /* 334 * Standard 32-bit handling of command and transfer mode. 335 */ 336 if (off == SDHCI_TRANSFER_MODE) { 337 return (sc->cmd_and_mode >> 16); 338 } else if (off == SDHCI_COMMAND_FLAGS) { 339 return (sc->cmd_and_mode & 0x0000ffff); 340 } 341 return ((val >> (off & 3)*8) & 0xffff); 342 } 343 344 static uint32_t 345 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 346 { 347 struct bcm_sdhci_softc *sc = device_get_softc(dev); 348 349 return RD4(sc, off); 350 } 351 352 static void 353 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 354 uint32_t *data, bus_size_t count) 355 { 356 struct bcm_sdhci_softc *sc = device_get_softc(dev); 357 358 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 359 } 360 361 static void 362 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 363 { 364 struct bcm_sdhci_softc *sc = device_get_softc(dev); 365 uint32_t val32 = RD4(sc, off & ~3); 366 val32 &= ~(0xff << (off & 3)*8); 367 val32 |= (val << (off & 3)*8); 368 WR4(sc, off & ~3, val32); 369 } 370 371 static void 372 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 373 { 374 struct bcm_sdhci_softc *sc = device_get_softc(dev); 375 uint32_t val32; 376 if (off == SDHCI_COMMAND_FLAGS) 377 val32 = sc->cmd_and_mode; 378 else 379 val32 = RD4(sc, off & ~3); 380 val32 &= ~(0xffff << (off & 3)*8); 381 val32 |= (val << (off & 3)*8); 382 if (off == SDHCI_TRANSFER_MODE) 383 sc->cmd_and_mode = val32; 384 else { 385 WR4(sc, off & ~3, val32); 386 if (off == SDHCI_COMMAND_FLAGS) 387 sc->cmd_and_mode = val32; 388 } 389 } 390 391 static void 392 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 393 { 394 struct bcm_sdhci_softc *sc = device_get_softc(dev); 395 WR4(sc, off, val); 396 } 397 398 static void 399 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 400 uint32_t *data, bus_size_t count) 401 { 402 struct bcm_sdhci_softc *sc = device_get_softc(dev); 403 404 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 405 } 406 407 static void 408 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 409 { 410 struct sdhci_slot *slot; 411 vm_paddr_t pdst, psrc; 412 int err, idx, len, sync_op; 413 414 slot = &sc->sc_slot; 415 idx = sc->dmamap_seg_index++; 416 len = sc->dmamap_seg_sizes[idx]; 417 slot->offset += len; 418 419 if (slot->curcmd->data->flags & MMC_DATA_READ) { 420 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 421 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 422 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 423 BCM_DMA_INC_ADDR, 424 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 425 psrc = sc->sc_sdhci_buffer_phys; 426 pdst = sc->dmamap_seg_addrs[idx]; 427 sync_op = BUS_DMASYNC_PREREAD; 428 } else { 429 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 430 BCM_DMA_INC_ADDR, 431 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 432 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 433 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 434 psrc = sc->dmamap_seg_addrs[idx]; 435 pdst = sc->sc_sdhci_buffer_phys; 436 sync_op = BUS_DMASYNC_PREWRITE; 437 } 438 439 /* 440 * When starting a new DMA operation do the busdma sync operation, and 441 * disable SDCHI data interrrupts because we'll be driven by DMA 442 * interrupts (or SDHCI error interrupts) until the IO is done. 443 */ 444 if (idx == 0) { 445 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 446 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 447 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 448 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 449 slot->intmask); 450 } 451 452 /* 453 * Start the DMA transfer. Only programming errors (like failing to 454 * allocate a channel) cause a non-zero return from bcm_dma_start(). 455 */ 456 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 457 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 458 } 459 460 static void 461 bcm_sdhci_dma_intr(int ch, void *arg) 462 { 463 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 464 struct sdhci_slot *slot = &sc->sc_slot; 465 uint32_t reg, mask; 466 int left, sync_op; 467 468 mtx_lock(&slot->mtx); 469 470 /* 471 * If there are more segments for the current dma, start the next one. 472 * Otherwise unload the dma map and decide what to do next based on the 473 * status of the sdhci controller and whether there's more data left. 474 */ 475 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 476 bcm_sdhci_start_dma_seg(sc); 477 mtx_unlock(&slot->mtx); 478 return; 479 } 480 481 if (slot->curcmd->data->flags & MMC_DATA_READ) { 482 sync_op = BUS_DMASYNC_POSTREAD; 483 mask = SDHCI_INT_DATA_AVAIL; 484 } else { 485 sync_op = BUS_DMASYNC_POSTWRITE; 486 mask = SDHCI_INT_SPACE_AVAIL; 487 } 488 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 489 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 490 491 sc->dmamap_seg_count = 0; 492 sc->dmamap_seg_index = 0; 493 494 left = min(BCM_SDHCI_BUFFER_SIZE, 495 slot->curcmd->data->len - slot->offset); 496 497 /* DATA END? */ 498 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 499 500 if (reg & SDHCI_INT_DATA_END) { 501 /* ACK for all outstanding interrupts */ 502 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 503 504 /* enable INT */ 505 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 506 | SDHCI_INT_DATA_END; 507 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 508 slot->intmask); 509 510 /* finish this data */ 511 sdhci_finish_data(slot); 512 } 513 else { 514 /* already available? */ 515 if (reg & mask) { 516 517 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 518 bcm_sdhci_write_4(slot->bus, slot, 519 SDHCI_INT_STATUS, mask); 520 521 /* continue next DMA transfer */ 522 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 523 (uint8_t *)slot->curcmd->data->data + 524 slot->offset, left, bcm_sdhci_dmacb, sc, 525 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 526 slot->curcmd->error = MMC_ERR_NO_MEMORY; 527 sdhci_finish_data(slot); 528 } else { 529 bcm_sdhci_start_dma_seg(sc); 530 } 531 } else { 532 /* wait for next data by INT */ 533 534 /* enable INT */ 535 slot->intmask |= SDHCI_INT_DATA_AVAIL | 536 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 537 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 538 slot->intmask); 539 } 540 } 541 542 mtx_unlock(&slot->mtx); 543 } 544 545 static void 546 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 547 { 548 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 549 size_t left; 550 551 if (sc->dmamap_seg_count != 0) { 552 device_printf(sc->sc_dev, "DMA in use\n"); 553 return; 554 } 555 556 left = min(BCM_SDHCI_BUFFER_SIZE, 557 slot->curcmd->data->len - slot->offset); 558 559 KASSERT((left & 3) == 0, 560 ("%s: len = %zu, not word-aligned", __func__, left)); 561 562 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 563 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 564 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 565 sc->dmamap_status != 0) { 566 slot->curcmd->error = MMC_ERR_NO_MEMORY; 567 return; 568 } 569 570 /* DMA start */ 571 bcm_sdhci_start_dma_seg(sc); 572 } 573 574 static void 575 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 576 { 577 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 578 size_t left; 579 580 if (sc->dmamap_seg_count != 0) { 581 device_printf(sc->sc_dev, "DMA in use\n"); 582 return; 583 } 584 585 left = min(BCM_SDHCI_BUFFER_SIZE, 586 slot->curcmd->data->len - slot->offset); 587 588 KASSERT((left & 3) == 0, 589 ("%s: len = %zu, not word-aligned", __func__, left)); 590 591 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 592 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 593 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 594 sc->dmamap_status != 0) { 595 slot->curcmd->error = MMC_ERR_NO_MEMORY; 596 return; 597 } 598 599 /* DMA start */ 600 bcm_sdhci_start_dma_seg(sc); 601 } 602 603 static int 604 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 605 { 606 size_t left; 607 608 /* 609 * Do not use DMA for transfers less than block size or with a length 610 * that is not a multiple of four. 611 */ 612 left = min(BCM_DMA_BLOCK_SIZE, 613 slot->curcmd->data->len - slot->offset); 614 if (left < BCM_DMA_BLOCK_SIZE) 615 return (0); 616 if (left & 0x03) 617 return (0); 618 619 return (1); 620 } 621 622 static void 623 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 624 uint32_t *intmask) 625 { 626 627 /* DMA transfer FIFO 1KB */ 628 if (slot->curcmd->data->flags & MMC_DATA_READ) 629 bcm_sdhci_read_dma(dev, slot); 630 else 631 bcm_sdhci_write_dma(dev, slot); 632 } 633 634 static void 635 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 636 { 637 638 sdhci_finish_data(slot); 639 } 640 641 static device_method_t bcm_sdhci_methods[] = { 642 /* Device interface */ 643 DEVMETHOD(device_probe, bcm_sdhci_probe), 644 DEVMETHOD(device_attach, bcm_sdhci_attach), 645 DEVMETHOD(device_detach, bcm_sdhci_detach), 646 647 /* Bus interface */ 648 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 649 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 650 651 /* MMC bridge interface */ 652 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 653 DEVMETHOD(mmcbr_request, sdhci_generic_request), 654 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 655 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 656 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 657 658 /* Platform transfer methods */ 659 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 660 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 661 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 662 /* SDHCI registers accessors */ 663 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 664 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 665 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 666 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 667 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 668 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 669 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 670 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 671 672 DEVMETHOD_END 673 }; 674 675 static devclass_t bcm_sdhci_devclass; 676 677 static driver_t bcm_sdhci_driver = { 678 "sdhci_bcm", 679 bcm_sdhci_methods, 680 sizeof(struct bcm_sdhci_softc), 681 }; 682 683 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 684 NULL, NULL); 685 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 686 #ifndef MMCCAM 687 MMC_DECLARE_BRIDGE(sdhci_bcm); 688 #endif 689